127 results on '"Kuroda, Tadahiro"'
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2. A bonding-less 5 GHz RFID module using inductive coupling between IC and antenna.
3. A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC.
4. Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design
5. Low-Power and ppm-Level Multimolecule Detection by Integration of Self-Heated Metal Nanosheet Sensors.
6. Wireless proximity interfaces with a pulse-based inductive coupling technique
7. Architecture design of versatile recognition processor for sensornet applications
8. QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.
9. BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W.
10. Analytical thruchip inductive coupling channel design optimization.
11. Basic study of non-contact connector for high-speed space cable transmission: Space fibre, short paper.
12. Low-energy algorithm for self-controlled Wireless Sensor Nodes.
13. A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver.
14. An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories.
15. Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces.
16. Low-latency wireless 3D NoCs via randomized shortcut chips.
17. Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation.
18. An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS.
19. Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation.
20. Adaptive window search using semantic texton forests for real-time object detection.
21. A 0.7V intermittently operating LNA with optimal on-time controller for pulse-based inductive-coupling transceiver.
22. A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL.
23. A case for wireless 3D NoCs for CMPs.
24. A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating.
25. A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS.
26. A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers.
27. A 100Mb/s 13.7pJ/bit DC-960MHz band plesiochronous IR-UWB receiver with costas-loop based synchronization scheme in 65nm CMOS.
28. A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array.
29. A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS.
30. CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect.
31. An 8bit 0.35–0.8V 0.5–30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator.
32. A vertical bubble flow network using inductive-coupling for 3-D CMPs.
33. Proximity IOs using inductive coupling.
34. Practical methodology of post-layout gate sizing for 15% more power saving.
35. 3D NoC with Inductive-Coupling Links for Building-Block SiPs.
36. Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions.
37. A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler.
38. A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface.
39. A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS.
40. 3D integration using inductive coupling and coupled resonator (Invited).
41. 24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%.
42. 10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver.
43. A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines.
44. 1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller.
45. Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication.
46. A 0.025–0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards.
47. Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card.
48. A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration.
49. A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS.
50. A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS.
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