Search

His current research interests include defining DFT architecture of complex SoCs, system security related to debug interfaces, and effective and efficient small-delay defect-oriented test generation. The most stringent security requirements and protocols in today's state-of-the-art systems are governed by Federal Information Processing Standards (FIPS). B Abstract b - Protecting user's secret data on the devices like smartphones, tablets, wearable devices etc., from memory attacks is always a challenge for system designers. [Extracted from the article]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

In this paper, the electrothermal coupling model of metal oxide resistive random access memory (RRAM) is analyzed by using a 2D axisymmetrical structure in COMSOL Multiphysics simulation software. The RRAM structure is a Ti/HfO2/ZrO2/Pt bilayer structure, and the SET and RESET processes of Ti/HfO2/ZrO2/Pt are verified and analyzed. It is found that the width and thickness of CF1 (the conductive filament of the HfO2 layer), CF2 (the conductive filament of the ZrO2 layer), and resistive dielectric layers affect the electrical performance of the device. Under the condition of the width ratio of conductive filament to transition layer (6:14) and the thickness ratio of HfO2 to ZrO2 (7.5:7.5), Ti/HfO2/ZrO2/Pt has stable high and low resistance states. On this basis, the comparison of three commonly used RRAM metal top electrode materials (Ti, Pt, and Al) shows that the resistance switching ratio of the Ti electrode is the highest at about 11.67. Finally, combining the optimal conductive filament size and the optimal top electrode material, the I-V hysteresis loop was obtained, and the switching ratio Roff/Ron = 10.46 was calculated. Therefore, in this paper, a perfect RRAM model is established, the resistance mechanism is explained and analyzed, and the optimal geometrical size and electrode material for the hysteresis characteristics of the Ti/HfO2/ZrO2/Pt structure are found. [ABSTRACT FROM AUTHOR]

This paper presents F2C, a cooperative resource management system for Infrastructure-as-a-Service (IaaS) clouds. Inspired by group-buying mechanisms in real product and service markets, F2C advocates a group of cloud tenants (called tenant coalition) to buy resource capacity in bulk and share the resource pool in the form of virtual machines (VMs). Tenant coalitions leads to vast opportunities for fine-grained resource sharing among multiple tenants. However, resource sharing, especially for multiple resource types, poses several challenging problems in pay-as-you-use cloud environments, such as sharing incentive, free-riding, lying and economic fairness. To address those problems, we propose Reciprocal Resource Fairness (RRF) , a novel resource allocation mechanism to enable fair sharing on multiple resource types within a tenant coalition. RRF is implemented in two complementary and hierarchical mechanisms: inter-tenant resource trading and intra-tenant weight adjustment. RRF satisfies several highly desirable properties to ensure fairness. We implement F2C in Xen platform. The experimental results show F2C is promising for both cloud providers and tenants. For cloud providers, F2C improves VM density and cloud providers’ revenue by 2.2X compared to the current IaaS cloud models. For tenants, F2C improves application performance by 45 percent and guarantees 95 percent economic fairness among multiple tenants. [ABSTRACT FROM PUBLISHER]

For a resistance random access memory whose insulating matrix is based on transition metal oxides, the underlying microscopic mechanism of its conductive filaments is crucial yet challenging to understand. In this paper, our first-principles calculations predict that titanium oxide prefers its anatase phase over rutile either with or without aluminum doping. We report that an oxygen vacancy in the anatase titanium oxide is stable in its neutral charge state when free of an external field, while it is unstable in the singly and doubly charged states. By calculating the dissociation energy of a single vacancy from a conductive filament, we also study the filament rupture that is modeled by an array of oxygen vacancies, with or without a nearby aluminum dopant. We find that for the dopants at a specific site, the conductive filaments tend to disconnect, which, in turn, enhances the endurance of a non-filamentary resistance random access memory. [ABSTRACT FROM AUTHOR]

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption. [ABSTRACT FROM AUTHOR]

The article presents a study that determines the applications of the spin-up for marine ecosystem model based on the Transport Matrix method on the graphics processing units (GPUs). It details the method of the study that uses two matrix-vector multiplications and biogeochemical model. It notes the result of the study, which shows that consumer GPU can beat significant number of central processing unit (CPU) without further using code optimization.

The COVID-19 pandemic has imposed significant challenges on global health, emphasizing the persistent threat of large-scale infectious diseases in the future. This study addresses the need to enhance pooled testing efficiency for large populations. The common approach in pooled testing involves consolidating multiple test samples into a single tube to efficiently detect positivity at a lower cost. However, what is the optimal number of samples to be grouped together in order to minimize costs? i.e. allocating ten individuals per group may not be the most cost-effective strategy. In response, this paper introduces the hierarchical quotient space, an extension of fuzzy equivalence relations, as a method to optimize group allocations. In this study, we propose a cost-sensitive multi-granularity intelligent decision model to further minimize testing costs. This model considers both testing and collection costs, aiming to achieve the lowest total cost through optimal grouping at a single layer. Building upon this foundation, two multi-granularity models are proposed, exploring hierarchical group optimization. The experimental simulations were conducted using MATLAB R2022a on a desktop with Intel i5-10500 CPU and 8G RAM, considering scenarios with a fixed number of individuals and fixed positive probability. The main findings from our simulations demonstrate that the proposed models significantly enhance the efficiency and reduce the overall costs associated with pooled testing. For example, testing costs were reduced by nearly half when the optimal grouping strategy was applied, compared to the traditional method of grouping ten individuals. Additionally, the multi-granularity approach further optimized the hierarchical groupings, leading to substantial cost savings and improved testing efficiency. [ABSTRACT FROM AUTHOR]

Running machine learning algorithms for image classification locally on small, cheap, and low-power microcontroller units (MCUs) has advantages in terms of bandwidth, inference time, energy, reliability, and privacy for different applications. Therefore, TinyML focuses on deploying neural networks on MCUs with random access memory sizes between 2 KB and 512 KB and read-only memory storage capacities between 32 KB and 2 MB. Models designed for high-end devices are usually ported to MCUs using model scaling factors provided by the model architecture's designers. However, our analysis shows that this naive approach of substantially scaling down convolutional neural networks (CNNs) for image classification using such default scaling factors results in suboptimal performance. Consequently, in this paper we present a systematic strategy for efficiently scaling down CNN model architectures to run on MCUs. Moreover, we present our CNN Analyzer, a dashboard-based tool for determining optimal CNN model architecture scaling factors for the downscaling strategy by gaining layer-wise insights into the model architecture scaling factors that drive model size, peak memory, and inference time. Using our strategy, we were able to introduce additional new model architecture scaling factors for MobileNet v1, MobileNet v2, MobileNet v3, and ShuffleNet v2 and to optimize these model architectures. Our best model variation outperforms the MobileNet v1 version provided in the MLPerf Tiny Benchmark on the Visual Wake Words image classification task, reducing the model size by 20.5% while increasing the accuracy by 4.0%. [ABSTRACT FROM AUTHOR]

In one of the several manifestations, the future cellular networks are required to accommodate a massive number of devices, several orders of magnitude compared to today’s networks. At the same time, the future cellular networks will have to fulfill stringent latency constraints. To that end, one problem that is posed as a potential showstopper is extreme congestion for requesting uplink scheduling over the physical random access channel (PRACH). Indeed, such congestion drags along scheduling delay problems. In this paper, the use of self-organized device-to-device (D2D) clustering is advocated for mitigating PRACH congestion. To this end, this paper proposes two D2D clustering schemes, namely, random-based clustering and channel-gain-based clustering. Accordingly, this paper sheds light on random access within the proposed D2D clustering schemes and presents a case study based on a stochastic geometry framework. For the sake of objective evaluation, the D2D clustering is benchmarked by the conventional scheduling request procedure. Accordingly, this paper offers insights into useful scenarios that minimize the scheduling delay for each clustering scheme. Finally, this paper discusses the implementation algorithm and some potential implementation issues and remedies. [ABSTRACT FROM AUTHOR]

A RAM cell, one of the components that greatly affects the performance of quantum computing, outputs mostly stored values on quantum-dot cellular automata (QCA) as they are. Currently, a problem is that the stored value may be initialized according to the selection input. To solve this problem, circuits that separate the stored value from the output value have recently been designed, but most of them have long latency, large areas, and many plane structure intersections, resulting in unstable signals. Therefore, in this paper, we propose a new secure QRAM (QCA-based RAM) cell logic by analyzing and modifying the existing cell logic in nanotechnology. We initially propose 2-to-1 multiplexers based on cell interaction, and a QRAM cell is proposed based on our multiplexer and an optimized QRAM cell logic diagram. Compared with existing designs, the proposed circuits produce superior results in terms of circuit performance and energy dissipation. Additionally, the operation of our multiplexers is verified mathematically using physical proof. The secure QRAM cell proposed in this paper does not have the initialization problem based on the selection input that is present in some existing circuits, thus it is very easy to design an extension to N × N RAM, and it has high signal stability, reliability, connectivity, and scalability because there is no intersection. [ABSTRACT FROM AUTHOR]

The seismic reflection method is one of the most important methods in geophysical exploration. There are three stages in a seismic exploration survey: acquisition, processing, and interpretation. This paper focuses on a pre-processing tool, the Non-Local Means (NLM) filter algorithm, which is a powerful technique that can significantly suppress noise in seismic data. However, the domain of the NLM algorithm is the whole dataset and 3D seismic data being very large, often exceeding one terabyte (TB), it is impossible to store all the data in Random Access Memory (RAM). Furthermore, the NLM filter would require a considerably long runtime. These factors make a straightforward implementation of the NLM algorithm on real geophysical exploration data infeasible. This paper redesigned and implemented the NLM filter algorithm to fit the challenges of seismic exploration. The optimized implementation of the NLM filter is capable of processing production-size seismic data on modern clusters and is 87 times faster than the straightforward implementation of NLM. [ABSTRACT FROM AUTHOR]

Using DNA as the next-generation medium for data storage offers unparalleled advantages in terms of data density, storage duration, and power consumption as compared to existing data storage technologies. To meet the high-speed data writing requirements in DNA data storage, this paper proposes a novel design for an ultra-high-density and high-throughput DNA synthesis platform. The presented design mainly leverages two functional modules: a dynamic random-access memory (DRAM)-like integrated circuit (IC) responsible for electrode addressing and voltage supply, and the static droplet array (SDA)-based microfluidic structure to eliminate any reaction species diffusion concern in electrochemical DNA synthesis. Through theoretical analysis and simulation studies, we validate the effective addressing of 10 million electrodes and stable, adjustable voltage supply by the integrated circuit. We also demonstrate a reaction unit size down to 3.16 × 3.16 μm2, equivalent to 10 million/cm2, that can rapidly and stably generate static droplets at each site, effectively constraining proton diffusion. Finally, we conducted a synthesis cycle experiment by incorporating fluorescent beacons on a microfabricated electrode array to examine the feasibility of our design. [ABSTRACT FROM AUTHOR]

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM's competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors. [ABSTRACT FROM AUTHOR]

Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems. [ABSTRACT FROM AUTHOR]

This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used bit error rate (BER) values from literature for static random-access memory and dynamic random-access memory technologies. We perform an error resilience evaluation based on peak signal-to-noise ratio and structural similarity for twelve video sequences, considering different decoding settings, with four quantization parameters, two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences. [ABSTRACT FROM AUTHOR]

This paper investigates the bipolar resistive switching and synaptic characteristics of IZO single-layer and IZO/SiO2 bilayer two-terminal memory devices. The chemical properties and structure of the device with a SiO2 layer are confirmed by x-ray photoemission spectroscopy (XPS) and transmission electron microscopy (TEM) imaging. The device with the SiO2 layer showed better memory characteristics with a low current level, as well as better cell-to-cell and cycle-to-cycle uniformity. Moreover, the neuromorphic applications of the IZO/SiO2 bilayer device are demonstrated by pulse response. Paired pulse facilitation, excitatory postsynaptic current, and pulse-width-dependent conductance changes are conducted by the coexistence of short- and long-term memory characteristics. Moreover, Hebbian rules are emulated to mimic biological synapse function. The result of potentiation, depression, spike-rate-dependent plasticity, and spike-time-dependent plasticity prove their favorable abilities for future applications in neuromorphic computing architecture. [ABSTRACT FROM AUTHOR]

To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications. [ABSTRACT FROM AUTHOR]

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( L_ \text gap) between the gates, and an underlap region ( L\text {un}) between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of L\text {gap} at 85 °C, which can be further improved to ~600 ms with the introduction of L\text {un} . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation. [ABSTRACT FROM PUBLISHER]

Resource optimization is becoming a prime factor in the progress of Internet-based technology, Cloud Computing. A resource management model is highly required in cloud data center paradigms to utilize available resources effectively. Bin-Packing problem is an applicable combinatorial optimization for Virtual Machine (VM) to Physical Machine (PM) allocation to minimize the required PMs. In this paper, we have proposed an efficient resource allocation and management algorithm in two phases. During the first phase, a Load Balanced Multi-Dimensional Bin-Packing (LBMBP) heuristic for Virtual Machine (VM) to Physical Machine (PMs or host) allocation is introduced, considering multidimensional resources: CPU, RAM, and Network Bandwidth. In the Second Phase, to perform VM migration, a mechanism to detect overloaded and underloaded hosts based on outliers has been described. The proposed work illustrated the simulation results using CloudSim Plus Simulator and observed a reduction in the number of active PMs. Energy consumption and the number of migrations with improved resource utilization. [ABSTRACT FROM AUTHOR]

Non-volatile memory express (NVMe) solid-state drives (SSDs) have been widely adopted in multi-tenant cloud computing environments or multi-programming systems. The on-board DRAM cache inside NVMe SSDs can efficiently reduce the disk accesses and extend the lifetime of SSDs. Current SSD cache management research either improves cache hit ratio while ignoring fairness, or improves fairness while sacrificing overall performance. In this paper, we present MLCache, a space-efficient shared cache management scheme for NVMe SSDs. By learning the impact of reuse distance on cache allocation, a workload-generic neural network model is built. At runtime, MLCache continuously monitors the reuse distance distribution for the neural network module to obtain space-efficient allocation decisions. MLCache also proposes an efficient parallel writing back strategy based on hit ratio and response time, to improve fairness. Experimental results show MLCache improves the write hit ratio when compared to baseline, and MLCache strongly safeguards the fairness of SSDs with parallel write-back and maintains a low level of degradation. [ABSTRACT FROM AUTHOR]

One of the fundamental challenges in geophysics is the calculation of distribution models for physical properties in the subsurface that accurately reproduce the measurements obtained in the survey and are geologically plausible in the context of the study area. This is known as inverse modeling. Performing a 3D joint inversion of multimodal geophysical data is a computationally intensive task. Additionally, since it involves a modeling process, finding a solution that matches the desired characteristics requires iterative calculations, which can take days or even weeks to obtain final results. In this paper, we propose a robust numerical solution for 3D joint inversion of gravimetric and magnetic data with Gramian-based structural similarity and structural direction constraints using parallelization as a high-performance computing technique, which allows us to significantly reduce the total processing time based on the available Random-Access Memory (RAM) and Video Random-Access Memory (VRAM)and improve the efficiency of interpretation. The solution is implemented in the high-level programming languages Fortran and Compute Unified Device Architecture (CUDA) Fortran, capable of optimal resource management while being straightforward to implement. Through the analysis of performance and computational costs of serial, parallel, and hybrid implementations, we conclude that as the inversion domain expands, the processing speed could increase from 4× up to 100× times faster, rendering it particularly advantageous for applications in larger domains. We tested our algorithm with two synthetic data sets and field data, showing better results than standard separate inversion. The proposed method will be useful for joint geological and geophysical interpretation of gravimetric and magnetic data used in exploration geophysics for example minerals, ore, and petroleum search and prospecting. Its application will significantly increase the reliability of physical-geological models and accelerate the process of data processing. [ABSTRACT FROM AUTHOR]

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW. [ABSTRACT FROM AUTHOR]

This paper introduces thorough comparative and interoperability analyses involving a browser-based P2P video streaming approach utilizing WebRTC (web real-time communication), along with WebRTC hybrid solutions developed using the React Native framework (for mobile) and the electron framework (for desktop and Raspberry Pi). The assessment is carried out based on various metrics, including CPU (central processing unit) load, RAM (random access memory) utilization, and network data consumption. The obtained findings highlight the potential of integrating WebRTC P2P video streaming into hybrid applications as a promising alternative for real-time video streaming applications in embedded systems; given that, compared to the current mainstreams, e.g., Chrome or Firefox, the proposed approach has superiority performance in terms of CPU load, RAM usage, and network occupancy. The results also demonstrated that interoperability is ensured between the two types of applications (web-based and hybrid-based one). [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata is pioneering nanotechnology, which has gained attention amongst the research community as a solid potential substitute against complementary metal oxide semiconductor (CMOS) technology. This paper explores a unique loop-based random-access memory (RAM) circuit with an asynchronous set and resets by utilizing an innovative (2 × 1) multiplexer and a D-latch in the design. Efficient designs of (1 × 4) RAM and (4 × 4) RAM, structured in three-layer, are implemented. The proposed multilayer designs are improved up to 20–30% over the existing single-layer and multilayer designs in terms of the total number of cells counts, area, latency, and overall cost. The proposed (4 × 4) RAM and (m × n) RAM structures show the excellent scalability of the projected RAM cells in designing complex circuits. The simulation results have been obtained, and their accuracy has been checked using QCADesigner 2.0.3 tool. [ABSTRACT FROM AUTHOR]

Data compression is a well-studied (and well-solved) problem in the setup of long coding blocks. But important emerging applications need to compress data to memory words of small fixed widths. This new setup is the subject of this paper. In the problem we consider, we have two sources with known discrete distributions, and we wish to find codes that maximize the success probability that the two source outputs are represented in $L$ bits or less. A good practical use for this problem is a table with two-field entries that is stored in a memory of a fixed width $L$ . Such tables of very large sizes are common in network switches/routers and in data-intensive machine-learning applications. After defining the problem formally, we solve it optimally with an efficient code-design algorithm. We also solve the problem in the more constrained case where a single code is used in both fields (to save space for storing code dictionaries). For both code-design problems we find decompositions that yield efficient dynamic-programming algorithms. With the help of an empirical study we show the success probabilities of the optimal codes for different distributions and memory widths. In particular, this paper demonstrates the superiority of the new codes over existing compression algorithms. [ABSTRACT FROM AUTHOR]

The frequency, nature, and scope of Soft Error Events (SEEs) is becoming an increasingly significant reliability concern as transistors continuously scale down into ever smaller nanometer memory chip geometries. As part of the on-going research efforts required to address this steadily developing situation, two significant research questions were addressed by the research work presented within this paper. The first research question addressed the possibility of crafting a novel methodology whose application would consistently lead to the creation of viable Monte Carlo SEE Simulators. Each of these Monte Carlo SEE Simulators would need to be capable of adequately profiling SEEs as well as simulating and modeling their impacts on the reliability of a variety of simulated 45-nm SRAM computer memories. The Standard 2-Parameter Weibull Soft Error Event (S2P-WSE) Simulator proposed within this paper as a direct application of this novel methodology successfully produced simulation results that were comparatively equivalent both directly and statistically to the results calculated by the empirically validated Weibull Row-Clustered Soft Error Reliability (WRCSER) model. This WRCSER Model was independently developed and empirically validated against proprietary reliability datasets obtained from testing a CISCO 45-nm SRAM computer memory device in a laboratory setting. The S2P-WSE Simulator itself was validated by means of a Kruskal–Wallis ANOVA test and by direct comparison of both the model and the simulator as a function of their respective failure probability and reliability results on 45-nm SRAM simulated computer memory devices subjected to the same SEE impacts over the course of an entire simulation run. The second research question sought to determine the significance of SEE topography versus a Row-Depth-Only bit error severity assumption on the reliability of simulated 45-nm SRAM computer memories shielded from the accumulating impacts of SEEs by variable error-correction codes, row-depth interleaving distances, and periodic scrubbing time intervals. The simulation runs for both the S2P-WSE Simulator and the T2P-WSE Simulator were carefully setup to ensure that only the potentially divergent factor between the results generated by the two simulators was the T2P-WSE Simulator's stochastically estimated topographical shape for each SEE impacting the simulated computer memory device. The work within this paper successfully demonstrated through direct plots of the two simulators’ failure probability and reliability results and the results of the Kruskal–Wallis ANOVA tests that the topography of SEEs does represent a significant impact on the overall failure probability and reliability of 45-nm SRAM computer memory devices. [ABSTRACT FROM PUBLISHER]

It is a significant problem to efficiently identify the frequently occurring patterns in a given dataset, so as to unveil the trends hidden behind the dataset. This paper is motivated by the serious demands of a high-performance in-memory frequent-pattern mining strategy, with joint optimization over the mining performance and system durability. While the widely used frequent-pattern tree (FP-tree) serves as an efficient approach for frequent-pattern mining, its construction procedure often makes it unfriendly for nonvolatile memories (NVMs). In particular, the incremental construction of FP-tree could generate many unnecessary writes to the NVM and greatly degrade the energy efficiency, because NVM writes typically take more time and energy than reads. To overcome the drawbacks of FP-tree on NVMs, this paper proposes evergreen FP-tree (EvFP-tree), which includes a lazy counter and a minimum-bit-altered (MBA) encoding scheme to make FP-tree friendly for NVMs. The basic idea of the lazy counter is to greatly eliminate the redundant writes generated in FP-tree construction. On the other hand, the MBA encoding scheme is to complement existing wear-leveling techniques to evenly write each memory cell to extend the NVM lifetime. As verified by experiments, EvFP-tree greatly enhances the mining performance and system lifetime by 40.28% and 87.20% on average, respectively. And EvFP-tree reduces the energy consumption by 50.30% on average. [ABSTRACT FROM PUBLISHER]

As an instance-level recognition problem, re-identification (re-ID) requires models to capture diverse features. However, with continuous training, re-ID models pay more and more attention to the salient areas. As a result, the model may only focus on few small regions with salient representations and ignore other important information. This phenomenon leads to inferior performance, especially when models are evaluated on small inter-identity variation data. In this paper, we propose a novel network, Erasing-Salient Net (ES-Net), to learn comprehensive features by erasing the salient areas in an image. ES-Net proposes a novel method to locate the salient areas by the confidence of objects and erases them efficiently in a training batch. Meanwhile, to mitigate the over-erasing problem, this paper uses a trainable pooling layer P-pooling that generalizes global max and global average pooling. Experiments are conducted on two specific re-identification tasks (i.e., Person re-ID, Vehicle re-ID). Our ES-Net outperforms state-of-the-art methods on three Person re-ID benchmarks and two Vehicle re-ID benchmarks. Specifically, mAP / Rank-1 rate: 88.6% / 95.7% on Market1501, 78.8% / 89.2% on DuckMTMC-reID, 57.3% / 80.9% on MSMT17, 81.9% / 97.0% on Veri-776, respectively. Rank-1 / Rank-5 rate: 83.6% / 96.9% on VehicleID (Small), 79.9% / 93.5% on VehicleID (Medium), 76.9% / 90.7% on VehicleID (Large), respectively. Moreover, the visualized salient areas show human-interpretable visual explanations for the ranking results. [ABSTRACT FROM AUTHOR]

Resistive random‐access memories are promising candidates for novel computer architectures such as in‐memory computing, multilevel data storage, and neuromorphics. Their working principle is based on electrically stimulated materials changes that allow access to two (digital), multiple (multilevel), or quasi‐continuous (analog) resistive states. However, the stochastic nature of forming and switching the conductive pathway involves complex atomistic defect configurations resulting in considerable variability. This paper reveals that the intricate interplay of 0D and 2D defects can be engineered to achieve reproducible and controlled low‐voltage formation of conducting filaments. The author find that the orientation of grain boundaries in polycrystalline HfOx is directly related to the required forming voltage of the conducting filaments, unravelling a neglected origin of variability. Based on the realistic atomic structure of grain boundaries obtained from ultra‐high resolution imaging combined with first‐principles calculations including local strain, this paper shows how oxygen vacancy segregation energies and the associated electronic states in the vicinity of the Fermi level govern the formation of conductive pathways in memristive devices. These findings are applicable to non‐amorphous valence change filamentary type memristive device. The results demonstrate that a fundamental atomistic understanding of defect chemistry is pivotal to design memristors as key element of future electronics. [ABSTRACT FROM AUTHOR]

In this paper, we identify that memory performance plays a crucial role in the feasibility and effectiveness for performing denial-of-service attacks on shared cache. Based on this insight, we introduce new cache DoS attacks, which can be mounted from the user-space and can cause extreme worst-case execution time (WCET) impacts to cross-core victims—even if the shared cache is partitioned—by taking advantage of the platform’s memory address mapping information and HugePage support. We deploy these enhanced attacks on two popular embedded out-of-order multicore platforms using both synthetic and real-world benchmarks. The proposed DoS attacks achieve up to 111X WCET increases on the tested platforms. [ABSTRACT FROM AUTHOR]

The millimeter-wave (mmWave) frequency band is seen as a key enabler of multigigabit wireless access in future cellular networks. In order to overcome the propagation challenges, mmWave systems use a large number of antenna elements both at the base station and at the user equipment, which leads to high directivity gains, fully directional communications, and possible noise-limited operations. The fundamental differences between mmWave networks and traditional ones challenge the classical design constraints, objectives, and available degrees of freedom. This paper addresses the implications that highly directional communication has on the design of an efficient medium access control (MAC) layer. The paper discusses key MAC layer issues, such as synchronization, random access, handover, channelization, interference management, scheduling, and association. This paper provides an integrated view on MAC layer issues for cellular networks, identifies new challenges and tradeoffs, and provides novel insights and solution approaches. [ABSTRACT FROM PUBLISHER]

Advanced Encryption Standard (AES) has been a prevalent cryptographic structure in the world. Existing AES-related cryptographic accelerators generally face the problem of high power consumption. To deal with this challenge, this paper presents a cryptographic structure that employs iterative reuse to decrease resource utilization. Through the efficient use of delay-line RAM, the implementation of long-length key storage results in a reduction in the utilization of registers. The computational complexity of AES cryptographic algorithm is reduced by using homomorphic mapping to the inversion operation in S-box from the Galois Fields GF(28) to GF[(24)2]. Such proposed AES cryptographic accelerator is characterized by its low resource utilization and low power consumption. In addition, we have also conducted some simulation analysis to evaluate its performance. The synthesis result indicates that the AES cryptographic accelerator exhibits a 0.74% reduction in utilization of LUT and a 35% decrease in power consumption, as compared to the original version. The proposed AES cryptographic accelerator results in an area of 0.101mm2, a throughput of 12.28Gbps, and a power consumption of 2.56mW in TSMC 90nm. [ABSTRACT FROM AUTHOR]

This paper presents simple yet effective optimizations for implementing data stream frequency estimation sketch kernels using High-Level Synthesis (HLS). The paper addresses design issues common to sketches utilizing large portions of the embedded RAM resources in a Field Programmable Gate Array (FPGA). First, a solution based on Load-Store Queue (LSQ) architecture is proposed for resolving the memory dependencies associated with the hash tables in a frequency estimation sketch. Second, performance fine-tuning through high-level pragmas is explored to achieve the best possible throughput. Finally, a technique based on pre-processing the data stream in a small cache memory prior to updating the sketch is evaluated to reduce the dynamic power consumption. Using an Intel HLS compiler, a proposed optimized hardware version of the popular Count-Min sketch utilizing 80% of the embedded RAM in an Intel Arria 10 FPGA, achieved more than 3x the throughput of an unoptimized baseline implementation. Furthermore, the sketch update rate is significantly reduced when the input stream is skewed. This, in turn, minimizes the effect of high throughput on dynamic power consumption. Compared to FPGA sketches in the published literature, the presented sketch is the most well-rounded sketch in terms of features and versatility. In terms of throughput, the presented sketch is on a par with the fastest sketches fine-tuned at the Register Transfer Level (RTL). [ABSTRACT FROM AUTHOR]

Resistive memory is a promising technology for achieving unprecedented storage densities and new in-memory computing features. However, to fulfill their promise, resistive memories require array architectures suffering from a severe interference effect called “sneak paths.” In this paper, we address the sneak-path problem through a communication-theory framework. Starting from the fundamental problem of readout with parallel-resistance interference, we develop several tools for detection and coding that significantly improve memory reliability. For the detection problem, we formulate and derive the optimal detector for a realistic array model, and then propose simplifications that enjoy similarly good performance and simpler implementation. Complementing detection for better error rates is done by a new coding scheme that shapes the stored bits to get lower sneak-path incidence. For the same storage rates, the new coding scheme exhibits error rates lower by an order of magnitude compared to known shaping techniques. [ABSTRACT FROM AUTHOR]

Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications. [ABSTRACT FROM AUTHOR]

In modern electronic devices, a variety of novel materials have been introduced such as transition metal oxides, chalcogenides, ferroelectric, and magnetic materials. The electrical response of such materials, used also as active layers, is strongly affected by atomic defects, which affect device performances, variability, and reliability. Extracting the defect properties (i.e., density, energy, and atomic nature) is, thus, crucial to both engineer the performances of electron devices and correctly project their scaling potential and reliability. In this paper, we propose a simple method to extract the atomic properties of defects from the thermal activation energy of the leakage current using a charge trapping relaxation model. [ABSTRACT FROM AUTHOR]

Due to additive operation’s dominated computation and simplified network in binary convolutional neural network (BCNN), it is promising for Internet of Things scenarios which demand ultralow power consumption. By means of fully exploiting the in-memory computing advantages and low current consumption design using multilevel cell (MLC) spin-toque transfer magnetic random access memory (STT-MRAM), this paper proposes an MLC-STT-computing in-memory-based computing in-memory architecture to achieve convolutional operation for BCNN to further reduce the power consumption. Simulation results show that compared with the resistive random access memory (RRAM)- and spin orbit torque-STT-MRAM-based counterparts, the architecture proposed in this paper reduces power consumption by ~ $35{\times}$ and 59% in Modified National Institute of Standards and Technology data set, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a diode-based multi-level cell spin–orbit torque magnetic random-access memory (SOT-MRAM) for high density memory applications. By stacking a shared diode over two in-parallel magnetic tunnel junctions (MTJs) that share a common heavy metal electrode, our proposed cell requires only one silicon-based transistor to access 2 bits. Having just one transistor to access 2 bits results in at least $2\times $ higher density when compared to various designs in the literature. Moreover, utilizing a high-density MRAM process, a $4F^{2}$ effective 1 bit area can be achieved. Furthermore, our proposed design maintains the high energy efficiency of the conventional SOT-MRAM. In addition, an improvement in figure of merit of at least 30% defined as energy area product is obtained compared to various designs. This paper also discusses the essential requirements to realize our proposed SOT-MRAM, such as the realization of diode MTJ stack and SOT-MTJs, with different critical currents and electrical resistances. [ABSTRACT FROM AUTHOR]

Ultrahigh-speed magnetization switching mechanism is strongly pursued, as it can improve the write performance of the magnetic random access memory (MRAM) and further extend the application area of spintronics. Currently, a well-studied switching mechanism is the spin transfer torque (STT), whose speed, however, is limited by an intrinsic incubation delay. Recently, spin–orbit torque (SOT) was proposed to solve the speed bottleneck of the STT. In this paper, we evaluate the potential of two types of SOT-MRAMs, whose data can be ultrafast written based on the recently discovered field-free SOT mechanisms, respectively. A cross-layer analysis is presented involving device modeling, circuit-level optimization, and architecture-level evaluation. First, the principle of the magnetization switching is analyzed with the macrospin simulation. Then, the optimization strategies at the circuit level are generalized through the SPICE-type simulation. Finally, we build up the memory architecture with the SOT-MRAMs, STT-MRAM, and static RAM. Their read/write performances are evaluated with NVSim software. It is demonstrated that one of the studied SOT-MRAMs shows the promising prospect in the non-volatile memory, especially suitable for high-capacity cache. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]