1. A review paper on memory fault models and test algorithms
- Author
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Aiman Zakwan Jidin, Lee Weng Fook, Mohd Syafiq Mispan, and Razaidi Hussin
- Subjects
Control and Optimization ,Design for testability ,Computer Networks and Communications ,Computer science ,Design for testing ,March test algorithm ,Random access memory ,Chip ,Fault (power engineering) ,Fault detection and isolation ,Test (assessment) ,Computer engineering ,Built-in self-test ,Hardware and Architecture ,Control and Systems Engineering ,Memory fault model ,Fault coverage ,Computer Science (miscellaneous) ,Electrical and Electronic Engineering ,Instrumentation ,Row ,Information Systems - Abstract
Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.
- Published
- 2021