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Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, twoinput EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods. [ABSTRACT FROM AUTHOR]

Pulse width of single event transient can be shrunk by pulse quenching effect in combinational circuits. And it is found that the pulse quenching effect is closely related to the layout of the circuits. In this paper, we propose a placement method for reducing soft errors in combinational circuits by increasing the number of quenching unit and enhancing the pulse quenching effect between them. To evaluate the soft error automatically, an evaluation platform is also implemented and embedded into commercial EDA tools with our placer. Simulation results show that our proposed method can reduce the soft error vulnerabilities by 14%–26%. [ABSTRACT FROM AUTHOR]

A novel high-voltage single-emitter horizontal current bipolar transistor (HCBT) is presented. Breakdown voltage improvement compared to high-speed transistor is obtainedwith full depletion of the intrinsic collectorby using implanted CMOS p-well region. Transistors with \text BV\text {CEO} = {10.5} V and fT = {15.8} GHz are demonstrated. Higher operating currents can be easily obtained by stretching the emitter length resulting in a flexible physical design of circuits. The transistor is fabricated in 0.18- \mu \textm HCBT BiCMOS process flow without the additional process steps and the use of additional lithography masks. [ABSTRACT FROM AUTHOR]

The charge-sharing (CS) switching scheme appeared recently as an alternative to the charge-redistribution (CR) ADC for moderate-resolution low-power applications. One advantage of the CS is that it requires less demanding reference and input buffers. On the other hand, the CS ADC is very sensitive to the comparator offset, because the latter is translated into non-linearity on the ADC transfer curve. This paper examines the mechanism that causes this non-linearity and proposes a closed-form expression for the maximum effective resolution that a CS ADC may achieve in the presence of comparator offset. Finally, the model is verified with behavioral simulations. [ABSTRACT FROM AUTHOR]

Due to the intrinsic lack of restoring paths, dynamic logic circuits have significant single-event susceptibility, and thus, they are not preferred in applications requiring high reliability when compared to static logic. However, in high speed applications, this circuit family is still very attractive. This papers presents two layout-based single-event resilient dynamic logic designs. The resultant SET pulse is suppressed because of charge-sharing in the layout-level. Simulation results verify that they enjoy higher single event tolerance. Experimental results validate the fact that approximately 20 ~ 30 % of magnitude reduction in cross-section is achieved in both designs. On the other hand, the increase in single-event performance is achieved at the expense of power and area overheads of 10 and 15 %, respectively, using our layout style in 130 nm CMOS bulk technology. [ABSTRACT FROM AUTHOR]

A built-in single event upsets (SEUs) detector is presented in this paper. This detector utilizes charge sharing to detect an SEU in a sequential cell, and the detection process is analyzed through Accuro simulations in a 65 nm technology. The normal operation of this detector would not induce obvious performance degradation of the target circuit. Through using this detector, error correction can be achieved based on dual modular redundancy (DMR) while the related power is about 20.4 % lower than that induced by triple modular redundancy (TMR). [ABSTRACT FROM AUTHOR]

A Monte Carlo model based on the signal-dependent charge sharing mechanism during charge collection has been developed to explain the nonlinearity of the photon transfer curve (PTC) in image sensors. The model is based on tracing of individual electrons generated by Poisson-distributed photons and describes the PTC nonlinearity as a process with sub-Poisson variance, with an excellent qualitative agreement with the experimental data. A new PTC curve fitting formula is proposed, considering this nonlinearity. The new formula is an excellent fit to the data, does not require selection of linear section of data points and allows more robust calculation of the system conversion gain. [ABSTRACT FROM PUBLISHER]

This paper aims to address the growing need for ultra-low power analog-to-digital converters (ADC). For this purpose, we pushed the limitations of conventional successive approximation register ADCs through the use of deep voltage scaling, a novel iterative precharging scheme, and topological improvements over recent works. From the simulations results we achieve a figure of merit of 31 fJ per conversion step, with an 8.45 effective number of bits, working at 5 MSps. [ABSTRACT FROM AUTHOR]

Automotive bus systems like FlexRay or CAN transmit safety critical data. To ensure correct functionality under all circumstances, extensive investigations about signal integrity and EMC have to be performed. To be able to use simulation in this validation process, suitable models for the components of the bus systems have to be developed. This paper shows how a combined transceiver model for signal integrity and EMC investigations can be created. The model shows good results in comparison to measurement data. [ABSTRACT FROM AUTHOR]

An average current controller (ACC) that can accurately regulate the light-emitting diode (LED) forward current for lighting applications is proposed. The proposed ACC employs a charge sharing method to achieve a highly accurate average LED forward current by compensating for an error occurred when the LED forward current is sampled. It was fabricated using a 0.35 μm CMOS process technology and occupied a small chip area of 1028 μm × 728 μm. The measurement results showed that the proposed ACC achieved a deviation in the average LED forward current of <0.6% over the entire input voltage range while achieving a maximum power efficiency of 93.6%. Therefore, the proposed ACC is suitable for high-quality LED lighting systems requiring an accurate LED forward current. [ABSTRACT FROM AUTHOR]

A highly reconfigurable charge-domain switched-gm-C complex band-pass filter (CBPF) topology that utilises a semi-passive charge-sharing technique is proposed. It uses only switches, capacitors, digital circuitry for three-phase non-overlapping clock generation and efficient gm-stages. Simulated in a 65 nm CMOS, a first-order CBPF operating at 1 GS/s sampling rate demonstrates flexible tunability of the centre frequency and bandwidth with a highly passive/digital implementation. The presented filter architecture features excellent power efficiency and compatibility with process scaling. [ABSTRACT FROM AUTHOR]

As technology scales down, soft errors, because of single event upsets (SEUs) that affect multiple nodes (through multiple node charge sharing), become a serious concern in nanometre technology integrated circuits. Existing radiation hardening techniques provide partial or no immunity when more than one node are affected. A new latch topology is presented that guarantees soft error tolerance when a single node or any arbitrary combination of node pairs is affected by an SEU. The proposed scheme exploits a positive feedback loop which consists of C-elements. Simulation results validate the efficiency of the new design over existing soft error hardening techniques such as BISER, FERST and TPDICE. [ABSTRACT FROM AUTHOR]