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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

The electromigration (EM) activation energy ( $\text {E}_{\text {A}}$ ) of alternative metals, such as Ru and Co, was obtained using low-frequency noise (LFN) measurements. High activation energies were expected, but values of ≈1 eV are found, most likely related to diffusion along with the metal-dielectric interface. Wafer-level accelerated EM tests were carried out to compare the LFN $\text {E}_{\text {A}}$ to the EM $\text {E}_{\text {A}}$ in the Ru wires. The calculation of the EM $\text {E}_{\text {A}}$ is found to be strongly dependent on the assumed temperature profile in the wire due to Joule heating (JH). The temperature profile was calculated analytically, assuming the contacts are at ambient temperature. For a void forming in direct proximity of the contact, the EM $\text {E}_{\text {A}}$ then matches the LFN $\text {E}_{\text {A}}$ . For a void at average wire temperature (ambient + JH), $\text {E}_{\text {A}}\approx $ 2 eV. In addition to demonstrating the application of LFN to study EM in alternative metals, this article also cautions for the impact of JH on the calculation of $\text {E}_{\text {A}}$ in interconnects.

In this paper, we report on the design, fabrication, packaging, and testing of very reliable CMOS-integrated 10-cm2 11-megapixel SiGe-based micromirror arrays on top of planarized six-level metal 0.18-?m CMOS wafers. The array, which is to be used as a spatial light modulator (SLM) for optical maskless lithography, consists of 8 ?m × 8 ?m pixels, which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. Due to very stringent requirements on mounted-die flatness (< 0.01 mrad), the first level packaging of SLM die is done using specially designed SiC holders. To avoid trapped particles between the die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (less than or equal to one 0.8-?m particle/cm2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling, and wire bonding, a temporary waferor zero-level packaging cap, which can be placed and removed at room temperature, was developed. The dynamic white light interferometer measurements of packaged dies showed that 99.5% of the 123 648 mirrors tested are within the spec. In addition, a stable average cupping of below 7 nm, an rms roughness of below 1 nm, and a stable actuation of over 2.5 teracycles are demonstrated.