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Mapping intellectual properties (IPs) on network-on-chip (NoC) has a notable impact on the timing, performance, and energy consumption of NoC. In this paper, we present a novel performance and power-aware task mapping technique based on mesh NoC that combines the latency constraint and branch and bound concepts. Our proposal for the definition of latency constraint helps intensify the bounds for pattern searching. With appropriate latency constraints, the best mapping solution can be achieved with less CPU time. This algorithm can be used with any NoC mesh shape. The mapping solutions are emulated on the FPGA-based NoC emulation platform. The experimental results demonstrate that the latency-constraint branch and bound technique can achieve better timing and lower energy consumption in nearly half the CPU time of the traditional branch and bound mapping algorithm.

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

A radiation hardened by design (RHBD) latch and its temporally hardened version to tolerate double node upsets are proposed in this paper. C-Elements are used to construct structures for fault correction. The temporally hardened version can further tolerate some single-event transients (SETs) at input port and clock line. Compared with Quintuple Modular Redundancy (QMR), the proposed non-temporally and temporally hardened latches are more area and power efficient with improved propagation delays. Compared with several previously reported temporally hardened latches, the proposed temporally hardened latch may introduce lower performance loss induced as setup time increase. Several multi-node upset tolerant latches are also compared with these two designs in terms of area, power, and delay. A cell level soft error analysis (TFIT) shows that the upset threshold LETs of the proposed latches in 180 nm process are higher than 16 MeV-cm2/mg.

Task mapping strategies on NoC (Network-on-Chip) have a huge impact on the timing performance and power consumption. So does the topology. In this paper, we describe the exploration flow of task mapping algorithms using different NoC mesh shapes. The flow is used to evaluate timing and energy consumption based on a NoC emulation platform. It is open to any task mapping algorithms and to any shapes of NoC mesh. A heterogeneous (PC and FPGA) platform is used to fully perform each step of the flow. The experiments demonstrate that the most appropriate task mapping strategy and the most suitable NoC shape strongly depend on the algorithm used. Depending on the timing latency results obtained and the FPGA resources used, the designer can select the appropriate task mapping strategy on the suitable shape in a short exploration time and with precise timing evaluation.

A quasi-constant on-time controlled buck front end in combined discontinuous conduction mode and boundary conduction mode is proposed to improve power factor (PF).When instantaneous AC input voltage is lower than the output bus voltage per period, the buck converter turns into buck-boost converter with the addition of a level comparator to compare input voltage and output voltage. The gate drive voltage is provided by an additional oscillator during distortion time to eliminate the cross-over distortion of the input current. This high PF comes from the avoidance of the input current distortion, thereby enabling energy to be delivered constantly. This paper presents a series analysis of controlling techniques and efficiency, PF, and total harmonic distortion. A comparison in terms of efficiency and PF between the proposed converter and a previous work is performed. The specifications of the converter include the following: input AC voltage is from 90V to 264V, output DC voltage is 80V, and output power is 94W.This converter can achieve PF of 98.74% and efficiency of 97.21% in 220V AC input voltage process.

The impacts of parasitic phenomenon on the performance of the analog accumulator in CMOS TDI image sensor are analyzed in this paper, and a modified accumulator with decoupling capacitor Cd to combat the parasitic phenomenon is also proposed. A 128-stage modified accumulator is designed and simulated. A prototype 1024 × 128 CMOS TDI image sensor with the 128-stage modified accumulator is fabricated in 0.18- μm one-poly four-metal 1.8 V/3.3 V CMOS technology. With a line rate of 3875 lines/s, at 128 stages the measured sensitivity and SNR improvement of the fabricated sensor are 617.1 V/lux·s and 16.6 dB respectively. The simulation and experiment results have proved the effectiveness of the decoupling capacitor C d when combating the parasitic phenomenon in the analog accumulator. The proposed modified accumulator is suitable for application in CMOS TDI image sensor with high stages.

A new multiple orientation event-based neurobiological recognition system is proposed by integrating recognition and tracking function in this paper, which is used for asynchronous address-event representation (AER) image sensors. The characteristic of this system has been enriched to recognize the objects in multiple orientations with only training samples moving in a single orientation. The system extracts multi-scale and multi-orientation line features inspired by models of the primate visual cortex. An orientation detector based on modified Gaussian blob tracking algorithm is introduced for object tracking and orientation detection. The orientation detector and feature extraction block work in simultaneous mode, without any increase in categorization time. An addresses lookup table (addresses LUT) is also presented to adjust the feature maps by addresses mapping and reordering, and they are categorized in the trained spiking neural network. This recognition system is evaluated with the MNIST dataset which have played important roles in the development of computer vision, and the accuracy is increased owing to the use of both ON and OFF events. AER data acquired by a dynamic vision senses (DVS) are also tested on the system, such as moving digits, pokers, and vehicles. The experimental results show that the proposed system can realize event-based multi-orientation recognition. The work presented in this paper makes a number of contributions to the event-based vision processing system for multi-orientation object recognition. It develops a new tracking-recognition architecture to feedforward categorization system and an address reorder approach to classify multi-orientation objects using event-based data. It provides a new way to recognize multiple orientation objects with only samples in single orientation.

A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered 0.35 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the detector bias error in this structure is less than 0.1 mV. The input resistance is close to an ideal value of zero, and the injection efficiency is almost 100%. The output voltage linearity of the designed circuit is more than 99%. The background suppression level is tunable between 8 nA–1.5 μA, and the background suppression uniformity is as high as 100%. A unit-cell occupies a 10 μm × 15 μm area and consumes less than 0.07 mW power.

As the most popular nonlinear denoise technique, the median filter has attracted significant attention in recent years. In this paper, a novel adaptive median filter is presented to remove random-valued impulse noise in images, named Adaptive Partition-Cluster-Based Median (APCM) Filter. Based on the partition cluster idea, the noise detector classifies pixels into different groups and identifies the noisy pixels in different regions adaptively without iterations. According to the results of noise detection, an improved adaptive decision-based filter is presented to restore the pixels which are corrupted by random-valued impulse noise. The proposed filter technique is open to any impulse noise. Extensive simulation results demonstrate that the proposed method substantially outperforms other state-of-the-arts impulse noise filter techniques both visually and in terms of objective quality measures. Furthermore, the proposed method is much friendly to the hardware parallel implementation of image processing because of its low computation complexity and simple realizable structure.

A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

With the trends of intelligent terminal and broadband network, all kinds of intelligent terminal application based on internet emerge in an endless stream. How to ensure the security of the various applications running on the next generation operating system TVOS is a key technical problem to be solved urgently. In this paper, we analyse the security mechanism of broadcast intelligent terminal application environment, put forward the security model and technology on TVOS, developed a safe and reliable application environment of broadcast intelligent terminal.

A method to reduce the side effects of dual-line timed address-event (TAE) vision system is proposed in this paper. The side effects include edge discontinuity and the natural insensitivity to object edges in the motion direction. X-event, a kind of artificial event is introduced to represent light intensity difference perpendicular to the motion direction of the target object. New timestamps are attached to the raw TAE data to adjust temporary resolution to the same order of magnitude with the vertical axis in the TAE representation. After removing noisy and redundant events, designed templates are used to generate X-events to renovate broken lines and reproduce perpendicular edges. It is a real-time process which is unnecessary to wait for the collection of all the raw TAE data. A behavioral model of a 2 × 256 TAE vision sensor is established in Matlab, and X-events Generation block is realized in FPGA. Experimental results show that the proposed method can patch the TAE representation effectively to obtain a one-pixel-wide, precise, closed and connected contour.

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application.

In system level design or architecture design stage of SoCs, it is important to estimate the system parameters such as bus utilization and buffer capacity. A novel bus modeling method which was derived from Markov model for obtaining these parameters of an on-chip-bus system has been proposed in this paper. This modeling approach employs Markov chain to describe the state change of the system. This method was used in architecture design verification of a video format converting (VFC) chip. By comparing the simulation result and the pessimistic estimate value, the rationality and high efficiency of this method were verified, and more than 55% of FIFOs size are saved. It is suitable for analyzing various bus systems, such as user-defined buses, industrial standard buses, multi-core and multi-bus systems.

A multi-integration technology with compact readout method to extend CMOS image sensor's dynamic range is presented. Compared with the timing of rolling readout, compact readout extends the available pixel readout time by adjusting the time-domain offset between two adjacent rows and each integration time in one frame. Thus the column readout bus is working continuously rather than intermittently, which makes good use of the whole integration time and the available readout time can be extended. This dynamic range extension technology was implemented on a prototype chip with a 128 × 128 pixel array. The pixel readout time with compact readout method is almost as 3 times long as the one with rolling readout method while 39 dB dynamic range extension is achieved at 120 fps.

A current source circuit for high-resolution CMOS image sensors is introduced in this paper, which can provide a stable current with immunity from IR-drop along the power and ground wires. In the circuit, two pre-charged floating capacitors controlled by two-phase non-overlap clock are connected between the gate and source of a MOS transistor alternately to maintain a constant V GS of the MOS transistor. In this way, the current flowing through the MOS transistor will be stable and has nothing to do with power level. The post simulation results show that the current supplied by the proposed circuit decreases only by 1.6% when the voltage of the power supply decreases by 30%. The simulations have proved that the proposed circuit can improve the performance of high-resolution CMOS image sensors.