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Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results. [ABSTRACT FROM AUTHOR]

Switched-capacitor-based multilevel inverters have been gaining increasing attention in recent years in view of their voltage-boosting capability and capacitor self-balancing properties. However, the existing topologies, which comprise frontend switched-capacitor cells and a backend H-bridge, result in longer discharging duration in some of their switched-capacitors. In addition, the adoption of backend H-bridge introduces common-mode voltage and necessitates multiple dc sources for voltage level extension. To resolve these problems, this article proposes a novel topology comprises a T-type inverter and n cascaded switched-capacitor cells. It requires only a single dc source and it manages to mitigate the common-mode voltage by connecting the neutral of ac output to the mid-point of dc link. All switched-capacitors in the proposed topology are ensured to be charged for at least half of the fundamental period to alleviate the capacitor voltage ripples and current spikes. The operation of the proposed topology is analyzed and experimental results are presented for validation. [ABSTRACT FROM AUTHOR]

The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies. [ABSTRACT FROM AUTHOR]

The conventional three-level active-neutral-point-clamped (ANPC) inverter requires high dc-link voltage at least twice the peak of ac output. To reduce the dc-link voltage, a recent topology that enhanced the voltage gain from half to unity has been presented. In this letter, an alternative ANPC topology is established by using two T-type inverters. Two floating capacitors with self-voltage balancing capability are integrated to achieve a voltage-boosting gain of 1.5. In addition, the proposed topology is capable of generating seven voltage levels. Its operation is validated through circuit analysis followed by experimental results of a prototype. [ABSTRACT FROM AUTHOR]

This paper proposes an improved offset selection method for discontinuous-pulse-width-modulation (DPWM)-based back-to-back converters to reduce dc-link current ripple. DPWM is introduced to power converters to diminish the stress on power transistors and prolong their lifespan. However, when using the DPWM method, the dc-link current ripple is increased in nonswitching regions of the power transistors. Moreover, in DPWM-based back-to-back converters, the dc-link current ripple reaches its maximum when the two transistors of both inverters are clamped in opposite directions. Therefore, the dc-link capacitors endure more stress, resulting in decreased life duration. To overcome this issue, the switching method should consider the clamping periods, when the current ripple increases. This can be achieved by modifying the DPWM offset, so that the clamping states of both converters are matched. The effectiveness of the proposed method is confirmed by both simulation and experimental results. [ABSTRACT FROM PUBLISHER]

The purpose of neutral-point voltage balancing algorithms in the three-level neutral-point clamped (3L-NPC) topology is to eliminate the voltage unbalance of top- and bottom-side dc-link voltages (neutral-point voltage). These algorithms are divided into dc unbalance and ac unbalance compensation methods. The dc unbalance causes distortion of output currents; therefore, this problem has to be solved. The ac unbalance implies that there is an ac ripple in the top- and bottom-side dc-link voltages. In applications using 3L-NPC topology, a large dc-link capacitor value is required to mitigate this ac unbalance problem. As a result, the size and the cost of applications become large and expensive. In this paper, a compensation method for mitigating the ac unbalance of the neutral-point voltage is proposed, which causes the dc-link capacitor value to be small, when a carrier-based pulse width modulation method is applied. The proposed method compensates the ac unbalance of the neutral-point voltage by adding an optimal compensation value to the reference duty signals. This compensation value is calculated simply by currents and reference duty signals. The calculation process of the optimal compensation value is discussed, and the effectiveness of the proposed method is verified with simulations and experiments. [ABSTRACT FROM PUBLISHER]

This article presents a dc-link capacitor lifetime improvement method for three-level photovoltaic hybrid active neutral-point clamped inverters in full modulation index range. The capacitors are one of the components with vulnerable reliability in a power conversion system. The dc-link capacitor current ripples lead to temperature rise and wear-out failure of the capacitors. The accumulated thermo-mechanical damages from the temperature rise reduce the capacitor lifetime and reliability of the system. The proposed modulation method suppresses effectively the dc-link capacitor current ripple to improve the capacitor lifetime. In this article, the proposed method is discussed via a comparison with conventional space-vector pulsewidth modulation in full modulation index range. The modulation index range is divided into two regions, namely medium-vector modulation and hybrid modulation region. The capacitor lifetime is evaluated by the capacitor lifetime model according to the modulation methods and modulation regions. The effectiveness of the proposed modulation method is verified through simulation and experimental results. [ABSTRACT FROM AUTHOR]

This article proposes a harmonic voltage injection pulsewidth modulation (PWM) method for a Vienna rectifier with an LCL filter. Existing PWM methods for Vienna rectifiers with full power factor can lead to resonance problems. It generates current oscillation at the resonant frequency. It is analyzed that why the resonance problem occurs in Vienna rectifier with the existing PWM methods. To solve these resonance problems, the proposed method injects a sinusoidal harmonic voltage into the sinusoidal reference voltage. The magnitude and phase of the injection voltage are determined by the power factor of the rectifier-side. Compared to other PWM methods, the proposed PWM method eliminates the possibility of resonant problems. Considering the operation characteristics of the proposed PWM method, this article suggests a design process for an LCL filter. The effectiveness and performance of the proposed PWM method and the design process for an LCL filter are verified by simulation and experiment. [ABSTRACT FROM AUTHOR]

Conventional active-neutral-point-clamped (ANPC) inverters exhibit low voltage gain that inherently leads to a high dc-link voltage requirement. An improved ANPC inverter that is capable of generating five voltage levels has recently reduced the dc-link voltage twofold to achieve unity gain. This led to the development of a single-stage dc–ac power converter with no frontend boost dc–dc converter. This article proposes novel ANPC inverters capable of unity or boosted voltage gain while generating higher voltage levels. The first topology can provide a voltage gain of 1.5 and extends the number of levels to seven by incorporating only one additional switch. The topology can also be extended by adding three switches and one floating capacitor to generate nine levels with unity voltage gain, or 11 levels with a voltage gain of 2.5. The proposed ANPC inverters and their operations are comprehensively discussed. Experimental results are provided to validate the feasibility of the proposed ANPC inverters. [ABSTRACT FROM AUTHOR]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

The centralized topology with three-level inverters are widely used in photovoltaic (PV) systems due to their less installation costs and complexity. However, the common maximum power point tracking (MPPT) is a disadvantage of the centralized topology particularly under the partial shading and panel mismatch conditions. In this system, if PV modules are separately connected to the split capacitor voltage, the MPPT efficiency can be improved by the proposed control strategy. By the proposed method, the two capacitor voltages can be controlled asymmetrically to perform the separate MPPTs of each PV module connected to separate capacitors. The outputs can be generated without distortion even if two capacitors are asymmetrically regulated. Simulation and experimental results verify the validity and feasibility of the proposed methods. [ABSTRACT FROM PUBLISHER]

The emerging switched-capacitor-based multilevel inverters offer interesting merits such as self-balancing of capacitor voltages and boosting of voltage gain. While the switched capacitors (SCs) in these topologies are charged in parallel with the dc source, severe current spikes issue is inevitable, rendering them impractical at high power. This article proposes a novel switched-capacitor-based T-type inverter that mitigates the current spikes by enabling soft charging for its integrated SCs, where both SC in the topological structure charges through a dedicated circuit comprises of an inductor and two switches. The proposed topology is capable of five-level ac voltage generation and when compared to a classical T-type/ANPC (active neutral-point-clamped) inverter, it achieves higher dc-link voltage utilization since its maximum attainable voltage gain is doubled. Theoretical findings of the proposed topology are validated by both the simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a neutral-point voltage balancing method for a three-level inverter that uses discontinuous pulse width modulation (DPWM). The performance of a three-level inverter system is affected by the neutral-point voltage unbalancing. Therefore, the voltages of series connected dc-link capacitors should be equal. Generally, the offset voltage is added to reference voltages in the conventional voltage balancing method. However, when using DPWM, the performance of conventional balancing method is limitary because turn-on and turn-off switching occurs at regular intervals. The proposed method is implemented by adjusting the discontinuous pulsewidth of positive and negative cycle. The proposed method maintains low switching losses and achieves the effective voltage balancing, without additional hardware and complex calculations. Simulation and experimental results confirm the feasibility and effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This article presents a novel cascaded multilevel inverter as an alternative to the cascaded H-bridge (CHB). By adopting two H-bridges integrated with two inductors and two power switches, the proposed topology is able to generate a five-level voltage with merely a single dc source. Voltage-boosting capability is guaranteed despite its single-stage operation. A corresponding modulation technique is also established to charge the boost inductors with a constant duty-cycle while simultaneously generating a five-level ac voltage. Therefore, the proposed topology outperforms the CHB in reducing the isolated dc source count, enhancing the voltage gain, and lowering the dc source voltage magnitude. In addition, the modularity is preserved, where the proposed topology can be extended by cascading multiple modules. The operation and feasibility of the proposed cascaded multilevel inverter is analyzed and validated through simulation and experimental results. [ABSTRACT FROM AUTHOR]

The switched-capacitor-based cascaded multilevel inverters (CMI) have been emerging due to their voltage boosting capability. Unfortunately, they suffer from impulse charging current and nonuniform operation. This article presents a topology termed as dual-T-type five-level CMI to resolve these problems without compromising the desirable voltage boosting characteristic. The main idea is to integrate a half bridge and an inductor to soft charge a capacitor that is connected in series with the dc source. The capacitor enables the voltage gain boosted to two, while the control of eight power switches that constitutes a dual-T structure enables five voltage levels generation. In addition, uniform operation is achieved for cascaded extensions. The operating principle of the proposed topology is analyzed and elaborated. For validation, simulation, and experimental results of a prototype are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a new family of multilevel inverter topology that is able to generate seven voltage levels by utilizing one or two floating capacitors and 10 power switches. This novel boost switched-capacitor seven-level inverter possesses voltage boosting capability with an achievable maximum voltage level 1.5 times the input direct current (dc) voltage. The generation of higher output voltage does not incur high-voltage stress on any power switch in this topology, as the peak inverse voltages of all power switches do not exceed the input source voltage. In addition, capacitor voltage balancing is not essential since the floating capacitors are effectively balanced during the charging and discharging processes. Furthermore, the proposed topology eliminates the need for multiple isolated dc sources, and a single dc source is sufficient in both its single-phase and three-phase topologies. The operating principle and steady-state analysis of the proposed topology are elaborated. Experimental results from a single-phase prototype are then presented to verify the validity of the proposed topology. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is regarded as a promising topology in high-voltage direct current systems. However, the MMC consists of numerous submodules (SMs) and switching devices, which lead to a considerable switching loss, and increased cost and size of the heat sink. To mitigate these issues, this paper presents a novel modulation method composed of fundamental frequency modulation (FFM) and multicarrier-based sinusoidal pulsewidth modulation schemes. The main purpose of this modulation method is the reduction of switching loss while maintaining good harmonic performance. However, the FFM scheme leads to the unbalanced capacitor voltage of each SM in the MMC. Accordingly, this paper additionally proposes the rotation method and selective voltage balancing control for SMs to ensure effective performance of the method. Simulation and experimental results verify the effectiveness and performance of the proposed modulation scheme through switching loss and spectral analyses. [ABSTRACT FROM AUTHOR]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

In this paper, a novel scheme for the estimation of the equivalent series resistance (ESR) of the dc-link electrolytic capacitor in three-phase ac/dc pulsewidth-modulation converters is proposed for condition monitoring. First, a controlled ac current component is injected into the input. Then, it induces ac voltage ripples on the dc output. By manipulating these ac voltage and current components with digital filters, the value of the ESR can be calculated, where the recursive least squares algorithm is used for reliable estimation results. In addition, the value of the ESR is corrected by considering the temperature effect, for which a simple temperature-sensing circuit has been designed. The simulation and experimental results show that the estimation error of the ESR is within a reasonable range, thereby enabling the determination of the appropriate time for the replacement of the capacitor. [ABSTRACT FROM PUBLISHER]

This paper proposes a generalized scheme of new soft-switching interleaved boost converters that is suitable for high step-up and high-power applications. The proposed converter is configured with proper numbers of series and parallel connected basic cells in order to fulfill the required output voltage and power levels, respectively. This leads to flexibility in device selection resulting in high component availability and easy thermal distribution. Design examples of determining the optimum circuit configuration for given output voltage and power level are presented. Experimental results from a 1.5-kW prototype are provided to validate the proposed concept. [ABSTRACT FROM AUTHOR]

This paper proposes a new method to reduce the ripple current of the DC-link capacitor in a two-level voltage source inverter (VSI), with a discontinuous pulse-width modulation (DPWM). In real applications, a capacitor block is very bulky, due to the parallel connection of several capacitors that share the value of the ripple current. Hence, it contributes significantly to the volume and weight of the whole system. Conventional DPWM is used to minimize the amount of switching for the power transistors, therefore, reducing stress and power loss. This leads to increased efficiency and reliability of the system. Nevertheless, the reduction of the DC link ripple current is still not optimal. Therefore, the proposed method introduces a PWM phase-shift technique to provide further reduction of the DC-link ripple current in a DPWM-based VSI. The efficacy of the proposed method is confirmed by simulation and experimental results. [ABSTRACT FROM AUTHOR]