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Phase-change memory (PCM), recently developed as the storage-class memory in a computer system, is a new non-volatile memory technology. In addition, the applications of PCM in a non-von Neumann computing, such as neuromorphic computing and in-memory computing, are being investigated. Although PCM-based devices have been extensively studied, several concerns regarding the electrical, thermal, and structural dynamics of phase-change devices remain. In this article, aiming at PCM devices, a comprehensive review of PCM materials is provided, including the primary PCM device mechanics that underpin read and write operations, physics-based modeling initiatives and experimental characterization of the many features examined in nanoscale PCM devices. Finally, this review will propose a prognosis on a few unsolved challenges and highlight research areas of further investigation. We certify that the submitted manuscript is truly original, unpublished, and not being considered for publication elsewhere. [ABSTRACT FROM AUTHOR]

PCM (phase-change memory) is a memory innovation that has gained prominence as a capacity-class memory for computer systems. It is made up of a tiny functional amount of phase-change material that is located in the middle of two electrodes. In PCM, data is kept by utilizing the difference in electrical resistance between a crystalline phase, which has a high resistance, and its amorphous phase, which has a low resistance. Using electrical pulses, the phase-change material would be shifted from a high to the low conductive region and conversely. However, the device's material science concerned with PCM has been generally studied, and questions remain regarding their electrical, warm, and fundamental aspects since its publication in the 1960s. One major downside of PCM is its low heat conductivity, which causes delays in the energy charging/discharging procedure and hardware efficiency. As a result of this, one of the primary focuses of PCM studies has been the improvement of PCM's heat conductivity through the utilization of nanotechnology and nanomaterials. Nanotechnology has been developing ultrasmall nanoparticles to improve traditional PCMs' thermophysical characteristics. These nanomaterials, such as metal, metal oxide, and carbon, will significantly boost PCM's thermal properties, including supercooling, viscosity, and heat capacity. An overview of PCM devices is presented in this article, which underlies perusing and composition activities. Consequently, we offered novel PCM devices and materials. Therefore, the total study is qualitative, and no machine learning approach is used. Because of this, we cannot say that the data is quantitative. Our work includes both test representations of the specific features observed in nanoscale PCM devices and material science demonstrations. In the end, we provide a point of view on some remaining open inquiries and possible future exploration directions. [ABSTRACT FROM AUTHOR]

Non-volatile memories based on phase-change materials have gained ground for applications in analog in-memory computing. Nonetheless, non-idealities inherent to the material result in device resistance variations that impair the achievable numerical precision. Projected-type phase-change memory devices reduce these non-idealities. In a projected phase-change memory, the phase-change storage mechanism is decoupled from the information retrieval process by using projection of the phase-change material's phase configuration onto a projection liner. It has been suggested that the interface resistance between the phase-change material and the projection liner is an important parameter that dictates the efficacy of the projection. In this work, we establish a metrology framework to assess and understand the relevant structural properties of the interfaces in thin films contained in projected memory devices. Using X-ray reflectivity, X-ray diffraction and transmission electron microscopy, we investigate the quality of the interfaces and the layers' properties. Using demonstrator examples of Sb and Sb2Te3 phase-change materials, new deposition routes as well as stack designs are proposed to enhance the phase-change material to a projection-liner interface and the robustness of material stacks in the devices. [ABSTRACT FROM AUTHOR]

In this paper, the flexible phase change behavior of Ge 2 Sb 2 Te 5 /Mg 35 Sb 65 superlattice-like memory based on PEEK substrate is investigated in detail. The flexible memory has good thermal stability (T c ∼270.4 °C), resistance to bending (more than 2 ×104 bending times), low resistance drift (less than 25% of the Ge 2 Sb 2 Te 5 film), stable amorphous to crystalline resistance ratio (∼2 orders of magnitude) and ultra-fast information access speed (∼5 ns). Bending refines the grain of the film and widens the band gap. This study provides a potential option for flexible information storage electronics. • Ge 2 Sb 2 Te 5 /Mg 35 Sb 65 superlattice-like films on PEEK substrates possess good thermal stability and mechanical bending durability. • After several bending cycles, the FPCM can even complete the ultrafast phase transition within 5 ns. [ABSTRACT FROM AUTHOR]

Memory devices, such as the phase change memory (PCM), have recently shown significant breakthroughs in terms of compactness, 3-D stacking capability, and speed up for deep learning neural accelerators. However, PCM is affected by the conductance drift, which prevents a precise definition of the synaptic weights in artificial neural networks. Here, we propose an efficient system-level methodology to develop drift-resilient multilayer perceptron (MLP) networks. The procedure guarantees high testing accuracy under conductance drift of the devices and enables the use of only positive weights. We validate the methodology using MNIST, rand-MNIST, and Fashion-MNIST datasets, thus offering a roadmap for the implementation of integrated nonvolatile memory-based neural networks. We finally analyze the proposed architecture in terms of throughput and energy efficiency. This work highlights the relevance of robust PCM-based design of neural networks for improving the computational capability and optimizing energetic efficiency. [ABSTRACT FROM AUTHOR]

As a promising alternative to dynamic RAM, phase change memory (PCM) suffers from limited write endurance. Therefore, many research proposals on PCM security or reliability have focussed on the possible threat of wear‐out attacks from malicious applications. However, it is also found that the non‐volatile nature and the programming behaviour of PCM bring other security challenges to the memory system. The authors examine the potential risk of information leakage and theft in memory management for PCM‐based cloud server or multitenant systems. By observing the influence of process variation (PV) on PCM cell programming, they propose a fast and efficient in‐memory data obfuscation mechanism to defend against memory attacks or information leakage during page reallocation mandated by OS. With the capabilities of in‐memory data randomisation, the proposed SecuRAM avoids the long write latency of PCM cells to erase the content, and achieves higher data initialisation efficiency than conventional software solutions. Second, the proposed SecuRAM also provides a novel solution of fast in‐memory hardware fingerprinting and random number generation, which are common and essential security functions in encryption or access authentication to protect confidential memory data from attackers. Two novel techniques are proposed to generate signatures and random numbers: the first is based on partial programming, which works in the same way as bulk data randomisation; the second is loop‐counting, which is an overhead‐free method by reusing the cell programming mechanism in iterate‐write PCM devices. Through evaluation, SecuRAM shows a much better performance and energy‐efficiency than conventional measures for PCM memory. [ABSTRACT FROM AUTHOR]

A new simultaneous acquisition software for Precession Electron Diffraction (PED) and Energy Dispersive X-ray Spectroscopy (EDX) mapping has been developed. This approach has been used to study the RESET operation in Ge-rich Ge-Sb-Te (Ge-rich GST) non-volatile Phase-Change Memory (PCM). Such an operation consists in the local amorphization of the device's active volume, which defines the memory state. Using PED patterns indexing, we were able to segment the amorphous area, and access its composition through EDX quantification. Moreover, both the spatial distribution and the chemical composition of the two crystalline phases overlapped in the chalcogenide layer were retrieved by using the spectral unmixing approach and PED patterns indexing. It evidences that Ge and Ge 2 Sb 1 Te 2 (GST-212) crystals are separated in the studied devices. Despite this, we show that Ge-enrichment is preserved in the active volume of a functional device, which is crucial to guarantee the RESET state stability at high temperature. We also link the origin of the failure of the RESET operation observed in a dysfunctional device to the larger Ge-depleted area. [ABSTRACT FROM AUTHOR]

Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) devices have been popularly used as synapses in crossbar array based analog Neural Network (NN) circuit to achieve more energy and time efficient data classification compared to conventional computers. Here we demonstrate the advantages of recently proposed spin orbit torque driven Domain Wall (DW) device as synapse compared to the RRAM and PCM devices with respect to on-chip learning (training in hardware) in such NN. Synaptic characteristic of DW synapse, obtained by us from micromagnetic modeling, turns out to be much more linear and symmetric (between positive and negative update) than that of RRAM and PCM synapse. This makes design of peripheral analog circuits for on-chip learning much easier in DW synapse based NN compared to that for RRAM and PCM synapses. We next incorporate the DW synapse as a Verilog-A model in the crossbar array based NN circuit we design on SPICE circuit simulator. Successful on-chip learning is demonstrated through SPICE simulations on the popular Fisher's Iris dataset. Time and energy required for learning turn out to be orders of magnitude lower for DW synapse based NN circuit compared to that for RRAM and PCM synapse based NN circuits. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is a non-volatile memory device with favorable characteristics such as persistence, byte-addressability, and lower latency when compared to flash memory. However, it comprises memory cells that have limited lifetime and higher access latency than DRAM. The row buffer size of a PCM is preferred to be larger than 128B to fill the latency gap between two memories and to reduce the metadata overhead incurred by wear leveling. As the cache line size in a general-purpose processor is 64B, a read-modify-write (RMW) module is required to be placed between the processor and the PCM, which in turn induces a performance degradation. To reduce such an overhead and enhance the reliability of a device, this paper presents a new RMW architecture. The proposed model introduces a DRAM cache in the RMW module, which minimizes redundant read operations for write operations by pre-fetching the entire transaction unit instead of merely caching the 64B requested data. Furthermore, a typeless merge operation is performed with the proposed cache by gathering multiple commands accessing consecutive addresses, irrespective of whether they are READ or WRITE. Simulation results indicate that the proposed method enhances the speed by 3.2 times and the reliability by 49 percent as compared to the baseline model. [ABSTRACT FROM AUTHOR]

A major challenge for the widespread adoption of phase change memory (PCM) as main memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation (i.e., an operation that writes “1”) is 2–5 times longer than the latency of a RESET operation (i.e., an operation that writes “0”). For this reason, the average write latency of a PCM system is limited by the high-latency SET operations. This paper presents a novel PCM architecture called DyPhase, which uses partial-SET operations instead of the conventional SET operations to introduce a symmetry in write latency, thereby increasing write performance and throughput. However, use of partial-SET decreases data retention time. As a remedy to this problem, DyPhase employs novel distributed refresh operations in PCM that leverage the available power budget to periodically rewrite the stored data with minimal performance overhead. Unfortunately, the use of periodic refresh operations increases the write rate of the memory, which in turn accelerates memory degradation and decreases its lifetime. DyPhase overcomes this shortcoming by utilizing a proactive in-situ self-annealing (PISA) technique that periodically heals degraded memory cells, resulting in decelerated degradation and increased memory lifetime. Experiments with PARSEC benchmarks indicate that our DyPhase architecture-based hybrid dynamic random access memory (DRAM)–PCM memory system, when enabled with PISA, yields orders of magnitude higher lifetime, 8.3% less CPI, and 44.3% less EDP on average over other hybrid DRAM–PCM memory systems that utilize PCM architectures from prior works. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) and cloud computing are two important technologies in our life. They are integrated together to support each other. However, with the rapid development of IoT, the disk-based storage systems in clouds fail to process and analyze data timely from IoT devices. In order to improve the storage capabilities of traditional disk-based storage systems, we present a light-weight log-based hybrid storage system, which comprises of the phase change memory (PCM), flash memory-based SSD and disks. These devices are merged as a single block device with a continuous linear-address space. We also design and implement a log-based hybrid file system called HFS for the block device. By combining the semantic characteristics of data with distinct performance characteristics of devices, HFS optimizes the file system layout and overcomes the shortcomings of traditional log-structured systems. We implement HFS in the Linux kernel and compare it with modern file systems such as Ext4 and F2FS. Evaluation results show the efficiency of the proposed light-weight log-based hybrid storage system. [ABSTRACT FROM AUTHOR]

The high current density required by magnetic tunneling junction (MTJ) switching driven by the spin transfer torque (STT) effect leads to large power consumption and severe reliability issues, hindering the timetable for STT magnetic random access memory to mass market. By utilizing the voltage-controlled magnetic anisotropy (VCMA) effect, the MTJ can be switched by the voltage effect and is postulated to achieve ultralow power (fJ). However, the VCMA coefficient measured in experiments cannot meet the requirement for MTJ with dimensions below 100 nm. And an external in-plane magnetic field usually is demanded for precessional VCMA switching. Here, in this paper, a novel approach for the amplification of the VCMA effect, which borrows ideas from negative capacitance, is proposed. The feasibility of the proposal is proved by physical simulation and in-depth analysis. Since the amplified VCMA effect, the external magnetic field can be eliminated. A three-terminal novel MTJ memory cell is designed with which both low power and high speed can be achieved. [ABSTRACT FROM AUTHOR]

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance. [ABSTRACT FROM AUTHOR]

Multi-Level Cell Phase Change Memory (MLC PCM) is a promising candidate technology for DRAM replacement in main memory of modern computers. Despite of its high density and low power advantages, this technology seriously suffers from slow read and write operations. While prior works extensively studied the problem of slow write, this paper targets high read latency problem in MLC PCM and introduces an architecture mechanism to overcome it. To this end, we rely on the fact that reading different bits from an MLC cell takes different latencies, i.e., for a 2-bit MLC, reading its Most-Significant Bit (MSB) is fast, while reading its Least-Significant Bits (LSBs) is slower. We then propose Half-Line PCM (HL-PCM), a novel memory architecture that leverages this non-uniformity in reading MLC PCM’s content to send a requested memory block to the processor in different cycles–it sends half of a memory block to the processor ahead of the other half. If the processor requested a word belonging to the first half, it can resume its execution on receiving the first half, while the other half has not sent yet and scheduled to be received by the memory controller later. HL-PCM is easy and simple to implement, i.e., it needs minor modifications at memory controller, the search/evict policies at last level cache, as well as data layout in main memory. Our experimental results show that the proposed design improves the average memory access latency by 33–43 percent and program’s execution time by 23 percent, on average, while incurring negligible overhead at memory controller and PCM DIMM, in a 16-core chip multiprocessor (CMP) running memory-intensive benchmarks. [ABSTRACT FROM PUBLISHER]

In this paper, we describe and evaluate three possible architectures for using 3D-DRAMs and PCMs in the processor memory hierarchy. We explore: (i) using 3D-DRAM as main memory with PCM as backing store; (ii) using 3D-DRAM as the Last Level Cache and PCM as the main memory; and (iii) using both 3D-DRAM and PCM as main memory. In each of these configurations, since the proposed memories are significantly faster than today’s off-chip 2D DRAMs for main memories and magnetic hard drives for secondary storage, we introduce hardware assistance to speedup virtual to physical address translation. We use Simics, a full system simulator, and benchmarks from both SPEC and OLTP suites to evaluate our designs. We use CACTI for obtaining energy and latency values for our configurations. We measure energy consumed and execution performance for the selected benchmarks. Our studies lead to the following conclusions. The best performance is obtained when 3D-DRAMs are used as last level caches (LLC) and PCM as the main memory. However, this organization performs poorly in terms of energy consumed. Our 3D-DRAM together with PCM as main memory is the best choice in terms of energy consumed. In terms of write-backs, 3D-DRAM as LLC causes fewer writes to PCM than the other organization. These experiments can be extended to explore specific memory organizations, capacities of 3D-DRAM needed as LLC or main memory and how the hybrid PCM/DRAM memory should be used for specific application contexts. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is an emerging technology for faster nonvolatile memory where a small volume of phase-change material is switched between amorphous and crystalline states to provide distinct logic levels. A major difficulty with these devices is the high-power requirement for set and reset operations. In this brief, we computationally analyze a vacuum-insulated self-aligned Ge2Sb2Te5 nanowire (NW) PCM device and propose a way to control the placement and orientation of the NWs. The analysis is performed using 2-D rotationally symmetric finite-element simulations with temperature-dependent material parameters and accounting for thermoelectric effects. Simulation results predict a $\sim 10\times $ reduction in current required for reset operation and minimal thermal crosstalk when compared with a similarly sized conventional mushroom cell due to effective suppression of lateral heat loss. The operation of the vacuum-insulated NW devices is also almost independent of current polarity (unlike that of the mushroom cell), which can be advantageous for more flexible array programming schemes. These devices can be used to build densely packed PCM with lower power consumption and less thermal crosstalk. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is a new solid-state memory technology that promises disruptive changes in the way servers and enterprise storage systems are built. Multilevel-cell (MLC) storage is highly desirable for increasing capacity and thus lowering cost-per-bit in memory technologies. In PCM, MLC storage is hampered by noise and resistance drift. In this paper, the issue of reliability in MLC PCM is addressed. A statistical model is developed that captures the main impairments in MLC PCM cell-arrays. A signal processing and coding framework is then introduced that provides robustness to drift and noise, improving reliability and prolonging data retention. Several examples of codes are provided and practical detection schemes are described. [ABSTRACT FROM AUTHOR]

Multi-level memory cells are used in non-volatile memories to increase the storage density. Using multi-level cells, however, imposes lower read and write speeds, limiting their usability with high-performing applications. In this work we study the tradeoff between storage density and write/read speeds using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give a detailed analytical treatment of their information rate and speed, provide encoding/decoding algorithms, and compare them with more basic access schemes and upper bounds. Using performance coding enables accessing the memory with variable access speeds, thus creating heterogenous storage devices serving a variety of applications with improved efficiency. [ABSTRACT FROM PUBLISHER]

Phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy of future computer systems. However, PCM has two critical weaknesses to substitute DRAM memory in its entirety. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 6–10 times slower than that of DRAM. To cope with this situation, hybrid memory architectures that use a small amount of DRAM together with PCM have been suggested. In this paper, we present a new memory management technique for hybrid PCM and DRAM memory architecture that efficiently hides the slow write performance of PCM. Specifically, we aim to estimate future write references accurately and then absorb frequent memory writes into DRAM. To do this, we analyze the characteristics of memory write references and find two noticeable phenomena. First, using write history alone performs better than using both read and write history in estimating future write references. Second, the frequency characteristic is a better estimator than temporal locality in predicting future memory writes. Based on these two observations, we present a new page replacement algorithm called CLOCK-DWF (CLOCK with Dirty bits and Write Frequency) that significantly reduces the number of write operations that occur on PCM and also increases the lifespan of PCM memory. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) is a promising alternative of DRAM. Nonetheless, it has a well-known problem that is the limited number of writes to storage cells. Thus, wear-leveling, which makes the writes uniform, is crucial to boost PCM’s lifetime. This paper proposes multi-way wear leveling (MWWL) to increase both endurance and security of PCM. MWWL can efficiently distribute writes to physical addresses uniformly from a multiple of ways while incurring little write overhead and almost no extra hardware overhead. More important, MWWL is a fundamental scheme that can be applied to existing leveling algorithms. As a case study, we extended a state-of-the-art technique, Security Refresh, to its multi-way version, Multi-Way Security Refresh (MWSR). The experimental results show that MWSR can achieve the same or better lifetime than that of the original two-level Security Refresh but with much less write overhead (from 11.7% down to 1.5%). [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is the best candidate for the storage device of next-generation mobile consumer electronics. PCM has the potential to replace NAND flash memory, due to its non-volatility, in-place programmability, and low power consumption. Even though the lifetime of PCM is longer than that of flash memory, wear leveling is still required to cope with the non-uniformity of storage workload or malicious attack. In this paper, a novel wear-leveling algorithm for PCM storage is proposed, where more physical pages are allocated to frequently updated logical pages, to balance the wear counts of PCM cells. In comparison with the previous techniques, the proposed algorithm improved the lifetime of PCM by at maximum 14 times and on average 8 times. [ABSTRACT FROM AUTHOR]

The bond constraint theory (BCT) dealing with the rigidity caused by bond constraints and the long-range potential fluctuations (LRPF) arising from the defects and heterogeneities in the disordered semiconductors are important for understanding the atomic and electronic properties of amorphous semiconductors. Here, they are applied to the already commercialized GeSbTe (GST) chalcogenide glasses used in the rewritable phase change memory (PCM) devices. The main concern at present is to improve their ability to withstand a large number of phase change cycles, by choosing the right composition. The two considerations (BCT and LRPF) are briefly described and tested on the most commonly used GeSbTe and the nearby compositions. While these considerations provide significant insight into their atomic and electronic structures, the ansatz linking them with the durability of the PCM devices need to be justified by more work. [ABSTRACT FROM AUTHOR]

Recent advance in per-cell bit density and semiconductor technology for NAND flash memories have led to significant cost reduction in non-volatile storage implementation. However, the reliability of data stored in flash memory has dramatically decreased, requiring an efficient mechanism to detect and correct bit errors during read and write operations of the data. For this purpose, when user data are often written into a flash page, an Error Correction Code (ECC) for the data is generated and stored in the spare area of the page. ECCs tend to become longer to correct more bit errors, sometimes beyond what is affordable by the spare area. In order to cope with this problem, there have been many attempts to keep ECCs in the data area, as opposed to the spare area of the flash memory. However, an additional mapping mechanism is required to locate ECCs for a given data page, and the program time and cycle are increased due to reading/storing the ECCs. In this paper, we present a novel ECC management mechanism with an assist from PCM for NAND flash storage systems. This technique uses PCM as a temporal storage to store ECCs for the data in log blocks. Later, the pages in log blocks are merged into data blocks with their ECCs kept in the PCM. Our experimental results show that the overhead from ECC management has been improved by 57% and 69% over previous attempts in BAST and FAST mapping schemes, respectively. [ABSTRACT FROM PUBLISHER]

Flash memories are currently the most widely used type of nonvolatile memories. A flash memory consists of floating-gate cells as its storage elements, where the charge level stored in a cell is used to represent data. Compared to magnetic recording and optical recording, flash memories have the unique property that the cells are programmed using an iterative procedure that monotonically shifts each cell's charge level upward toward its target value. In this paper, we model the cell as a monotonic storage channel, and explore its capacity and optimal programming. We present two optimal programming algorithms based on a few different noise models and optimization objectives. [ABSTRACT FROM AUTHOR]

Abstract: Crystallization temperatures of the Sb2Te films increase remarkably from 139.4°C to 223.0°C as the N2 flow rates increasing from 0sccm to 1.5sccm. Electrical conduction activation energies for amorphous and crystalline states increase by doping nitrogen. A small amount of nitrogen atoms can locate at interstitial sites in the hexagonal structure, generating a strain field, and improving the thermal stability of amorphous state. The best 10-years lifetime at temperature up to 141°C is found in Sb2TeN1 films. Doping excessively high nitrogen in Sb2Te film will form nitride and make Te separate out. As a result, the activation energy for crystallization decreases instead, accompanying with the deterioration of thermal stability. The power consumption of PCRAM test cell based on Sb2TeN1 film is ten times lower than that of PCRAM device using Ge2Sb2Te5 films. [Copyright &y& Elsevier]

A phase-change (PC) memory model that keeps track of the detailed cooling profile in the RESET process is described in this brief. By physically calculating the final crystal fraction resulting from the thermal dynamic of the PC material during the RESET process, the final resistance of the memory cell can be more accurately determined. The proposed model has been implemented in Verilog-A language and verified by experimental data. [ABSTRACT FROM AUTHOR]

A key issue in nonvolatile storage is long-term data retention. This aspect is even more important in innovative storage technologies such as phase-change memory (PCM), which promises better performance and easier scalability with respect to traditional Flash memory and potential for multilevel storage. In this respect, we experimentally investigated the stability of intermediate states obtained by means of partial-SET programming. To this end, we analyzed the effects of the width and the amplitude of the programming pulses on the degradation of intermediate programmed resistance levels over time in PCM cells. Our study was carried out by considering the average behavior of an array of PCM cells, showing that data-retention properties degrade as the programming thermal stress increases. [ABSTRACT FROM AUTHOR]

The transient simulation of threshold switching in phase-change memory (PCM) devices is essential for the prediction and optimization of cell behavior depending on the circuit parameters and for the understanding of the ultimate limit of operation speed. This paper presents a simulation study of threshold switching in PCM devices aimed at investigating the role of delay and switching times in cell behavior. The analytical Poole–Frenkel model for conduction and the energy gain model for threshold switching are used to evaluate the transient effects. The current and field transients at the basis of the switching phenomenon are shown and discussed with the aid of the numerical model. The impact of cell parasitics, in particular the parallel capacitance, is finally addressed. [ABSTRACT FROM PUBLISHER]

In-memory analytics—which probes data stored in RAM rather than on disk, as is traditionally the case—is becoming popular because it speeds up the analysis process, even as data volumes explode. [ABSTRACT FROM PUBLISHER]

Phase-change electrical probe memory has recently attained considerable attention owing to its profound potential for next-generation mass and archival storage devices. To encourage more talented researchers to enter this field and thereby advance this technology, this paper first introduces approaches to induce the phase transformation of chalcogenide alloy by probe tip, considered as the root of phase-change electrical probe memory. Subsequently the design rule of an optimized architecture of phase-change electrical probe memory is proposed based on a previously developed electrothermal and phase kinetic model, followed by a summary of the state-of-the-art phase-change electrical probe memory and an outlook for its future prospects. [ABSTRACT FROM AUTHOR]

Free-p—fine-grained remapping with error checking and correcting (ECC) and embedded pointers—remaps worn-out nonvolatile RAM (NVRAM) blocks at a fine granularity without requiring large dedicated storage and protects NVRAM against both hard and soft errors. Furthermore, Free-p can be implemented purely in the memory controller, avoiding custom NVRAM devices. [ABSTRACT FROM PUBLISHER]

As dynamic RAM scaling approaches its physical limit, phase-change memory is the most mature and well-studied option for potential DRAM replacement. However, malicious wear-out attacks can exploit PCM's limited write endurance. To address this, a low-cost wear-leveling scheme can dynamically randomize the data addresses across the entire address space and obfuscate their actual locations from users and system software. [ABSTRACT FROM PUBLISHER]