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Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes. However, it is important to note that T-gates come at a considerable computational cost. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We articulate the proposed circuits employing Clifford+T gates, facilitating error correction code implementation. Additionally, we minimise T-gate usage, thereby reducing computational costs and fortifying circuit robustness against errors and environmental disturbances-essential for mitigating the effects of internal and external noise. Our methodology employs a bottom-up examination of comparator circuits, initiating with a detailed study of their gates. Subsequently, we systematically dissect the functions of these gates, thereby advancing towards a comprehensive understanding of the circuit's overall functionality. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance. [ABSTRACT FROM AUTHOR]

Background: In April 2018, the UK government implemented a levy on soft drinks importers and manufacturers, tiered according to the amount of sugar in drinks. The stated aim was to encourage manufacturers to reduce sugar and portion sizes. Previous evidence suggests that the policy has been successful in reducing sugar in drinks in the short-term since implementation, but their sustained effects have not been explored. This study aimed to assess the impact of the soft drink industry levy (SDIL) on sugar levels, price, portion size and use of non-sugar sweeteners in the medium-term. Methods and findings: Product data from 30 November 2017 to 14 March 2020 from one major UK retail supermarket were analysed (112,452 observations, 126 weekly time points). We used interrupted time series analysis, to assess the impact of the soft-drink industry levy (SDIL) on levy-eligible soft drinks, with exempt drinks (i.e. 100% fruit juices, milks, flavoured milks) acting as a comparator series. At the point of implementation of the SDIL (April 2018) there was a step change in the proportion of eligible drinks with sugar content below the SDIL levy threshold (5g per 100ml) (+0.08, 95%CI: +0.04, +0.12), with a similar sized decrease in the proportion in the highest levy category (> = 8g sugar per 100ml) (-0.06, 95%CI: -0.10, -0.03). Between April 2018 and March 2020, the proportion of eligible drinks below the SDIL levy threshold continued to gradually increase (p = 0.003), while those in the highest levy category decreased (p = 0.007). There was a step change in price of eligible drinks in the higher levy category at the point of implementation of +£0.049 (95%CI: +£0.034, +£0.065) per 100mL (for comparison, the levy is set at £0.024 per 100mL for this group). Trends in price for the high levy category were not altered by the SDIL. In the no levy category, there was a step change in price at the implementation (+£0.012 per 100mL, 95%CI: +£0.008, +£0.023), followed by a second step change in October 2018 (-£0.018p per 100mL, 95%CI: -£0.033, -£0.001p). The volume of products in the higher levy group decreased at the time of the implementation (-305mL on average including multipacks, 95%CI: -511, -99). The change in trend for the product volume of drinks in the higher levy group between April 2018 and March 2020 was in the increasing direction (+704mL per year, 95%CI: -95, 1504), but it did not meet our threshold for statistical significance (p = 0.084). There were no changes observed in the volume of lower levy drinks or no levy drinks. There was a step change in the proportion of drinks with non-sugar sweeteners at the implementation of the SDIL (+0.04, 95%CI: +0.02, +0.06). Conclusion: These results suggest that the SDIL was successful in [1] producing reductions in sugar levels that were maintained over the medium term up to March 2020 and [2] a reduction in product volume for higher tier drinks that may be diminishing over time. Our results also show that the SDIL was associated with a maintained price differential between high and low sugar drinks. [ABSTRACT FROM AUTHOR]

This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital). [ABSTRACT FROM AUTHOR]

External comparator (EC) studies are increasingly being used to generate evidence that supports the evaluation of emerging pharmacological treatments for regulatory and health technology assessment (HTA) purposes. However, the reliability of evidence generated from EC studies can vary. In this paper, we outline how an existing framework for causal inference, the target trial emulation (TTE) framework, can be appropriately applied to improve the design and analysis of EC studies. Applying the TTE framework involves specifying the protocol of an ideal target trial which would answer the causal question of interest, then emulating its key elements under real-world (RW) settings. We describe each component of the original TTE framework and explain how it can be applied to EC studies, supplemented with practical recommendations. We also highlight special considerations and limitations in applying the TTE framework to EC studies. We describe how the TTE framework can be applied to improve the clarity, transparency, and reliability of evidence generated from EC studies. [ABSTRACT FROM AUTHOR]

This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

For the calibration of linear scales, comparators are generally used. Comparators are devices that enable the movement of an evaluation apparatus over a calibrated scale along a linear base with high precision. The construction of a comparator includes a movable carriage that carries the device for the evaluation of the position of the given edge of the line scale relative to the beginning of the scale. In principle, it involves a camera capturing the scale of the measurer, where the position of the camera's projection center is measured using an interferometer. This article addresses the development of a comparator assembled from low-cost components, as well as the description of systematic influences related to the movement of individual parts of the system, such as the inclination and rotation of the camera and directional and height deviations during the carriage's movement. This article also includes an evaluation of the edge of the given scale with subpixel accuracy, addressing distortion elimination and excluding the influences of impurities or imperfections on the scale. The proposed solution was applied to linear-scale measurers, such as leveling rods with coded and conventional scales and measuring tapes. The entire process of measurement and evaluation was automated. [ABSTRACT FROM AUTHOR]

The estimand framework as defined by the ICH E9(R1) addendum aims to clearly define "the treatment effect reflecting the clinical question posed by the trial objective". It intends to achieve this goal of a clear definition by specifying the 5 estimand attributes: treatment conditions, population, endpoints, handling of intercurrent events (IEs), and population-level summary. However, hybrid clinical/observational research like External Comparators (ECs) leads to new reflections on existing attributes and to considerations for additional ones. Specifically, treatment conditions and exposure may be more difficult to handle in the EC, and especially Standard of Care (SoC) treatment needs detailed attention. The external population typically cannot be based on the classical Intention-to-treat population and constitutes also an approximation only. Endpoints may not be comparable across cohorts, and IEs may be more different than in an RCT setting, such that the hypothetical treatment policy according to the ICH E9(R1) addendum may become of greater interest especially for long-term endpoints. Finally, the necessary assumptions for some population-level summaries (e.g., the proportional hazards assumption) can become more fragile when joining data from different sources due to induced heterogeneity. Finally, it is shown that the baseline definition and the marginal estimator are candidates for additional estimand attributes in case the estimand framework is revised to account for observational study needs. [ABSTRACT FROM AUTHOR]

Though there is only one term for the gold standard of Randomized Controlled Trials the terminology used for controlled research involving external data is diverse. Common terms include External Comparator/Control Arm study, Externally Controlled Trial, Synthetic Control study and Historical Control study. The term Externally Controlled Trial was recently selected by the U.S. Food and Drug Administration (FDA) and is in line with the use case of a pivotal trial. It entails pre-specification of the external dataset and its analysis in the trial protocol, which produces the highest amount of transparency, which is an important aspect for maximum credibility. If this pre-specification did not occur, we advocate the term External Comparator Cohort study (or short External Comparator study), which is derived by scrutinizing the paired terms study/trial, control/comparator and arm/cohort. Furthermore, we propose an overall framework of nomenclature, which is generally applicable for research projects involving external data. Only a precise and consistent use of terminology will most effectively safeguard from unintended implications, inaccurate perceptions, and misguided mindsets. [ABSTRACT FROM AUTHOR]

Background: Pragmatic trials evaluating complex health interventions often compare them to usual care. This comparator should resemble care as provided in everyday practice. However, usual care can differ for the same condition, between patients and practitioners, across clinical sites and over time. Heterogeneity within a usual care arm can raise methodological and ethical issues. To address these it may be necessary to standardise what usual care entails, although doing so may compromise a trial's external validity. Currently, there is no guidance detailing how researchers should decide the content of their usual care comparators. We conducted a methodology review to summarise current thinking about what should inform this decision. Methods: MEDLINE, Embase, CINAHL and PsycINFO were searched from inception to January 2022. Articles and book chapters that discussed how to identify or develop usual care comparators were included. Experts in the field were also contacted. Reference lists and forward citation searches of included articles were screened. Data were analysed using a narrative synthesis approach. Results: One thousand nine hundred thirty records were identified, 1611 titles and abstracts screened, 112 full texts screened, and 16 articles included in the review. Results indicated that the content of a usual care comparator should be informed by the aims of the trial, existing care practices, clinical guidelines, and characteristics of the target population. Its content should also be driven by the trial's requirements to protect participants, inform practice, and be methodologically robust, efficient, feasible and acceptable to stakeholders. When deciding the content of usual care, researchers will need to gather information about these drivers, balance tensions that might occur when responding to different trial objectives, and decide how usual care will be described and monitored in the trial. Discussion: When deciding the content of a usual care arm, researchers need to understand the context in which a trial will be implemented and what the trial needs to achieve to address its aim and remain ethical. This is a complex decision-making process and trade-offs might need to be made. It also requires research and engagement with stakeholders, and therefore time and funding during the trial's design phase. Trial registration: PROSPERO CRD42022307324. [ABSTRACT FROM AUTHOR]

Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a digital circuit designer. Most of the times, the designer sacrifices power consumption and chip area to decrease delay for a given technology node. To overcome this problem, we propose the ternary threshold logic gate. We have implemented the proposed gate by combining the threshold logic with the ternary logic. Then, we have constructed basic building blocks of a ternary ALU (as ternary logic gates, comparator, and arithmetic circuits) using the proposed ternary threshold logic gate. We have compared these building blocks and implemented with the proposed gate, with the ones implemented using different technologies. Via simulations, we have shown that the proposed gate may be utilized to decrease delay, power consumption, and chip area of ternary circuits. Thus, the proposed ternary threshold logic gate can be used to decrease delay, power consumption, and chip area of ternary circuits. [ABSTRACT FROM AUTHOR]

This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design. [ABSTRACT FROM AUTHOR]

Background: Well‐designed randomized trials provide high‐quality clinical evidence but are not always feasible or ethical. In their absence, the electronic medical record (EMR) presents a platform to conduct comparative effectiveness research, central to the emerging academic learning health system (aLHS) model. A barrier to realizing this vision is the lack of a process to efficiently generate a reference comparison group for each patient. Objective: To test a multi‐step process for the selection of comparators in the EMR. Materials and Methods: We conducted a mixed‐methods study within a large aLHS in North Carolina. We (1) created a list of 35 candidate variables; (2) surveyed 270 researchers to assess the importance of candidate variables; and (3) built consensus rankings around survey‐identified variables (ie, importance scores >7) across two panels of 7–8 clinical research experts. Prioritized algorithm inputs were collected from the EMR and applied using a greedy matching technique. Feasibility was measured as the percentage of patients with 100 matched comparators and performance was measured via computational time and Euclidean distance. Results: Nine variables were selected: age, sex, race, ethnicity, body mass index, insurance status, smoking status, Charlson Comorbidity Index, and neighborhood percentage in poverty. The final process successfully generated 100 matched comparators for each of 1.8 million candidate patients, executed in less than 100 min for the majority of strata, and had average Euclidean distance 0.043. Conclusion: EMR‐derived matching is feasible to implement across a diverse patient population and can provide a reproducible, efficient source of comparator data for observational studies, with additional testing in clinical research applications needed. [ABSTRACT FROM AUTHOR]

BACKGROUND: Hospital at Home (H@H) programs--which seek to deliver acute care within a patient's home--have become more prevalent over time. However, existing literature exhibits heterogeneity in program structure, evaluation design, and target population size, making it difficult to draw generalizable conclusions to inform future H@H program design. OBJECTIVE: The objective of this work was to develop a quality improvement evaluation strategy for a H@H program--the Kaiser Permanente Advanced Care at Home (KPACAH) program in Northern California--leveraging electronic health record data, chart review, and patient surveys to compare KPACAH patients with inpatients in traditional hospital settings. METHODS: The authors developed a 3-step recruitment workflow that used electronic health record filtering tools to generate a daily list of potential comparators, a manual chart review of potentially eligible comparator patients to assess individual clinical and social criteria, and a phone interview with patients to affirm eligibility and interest from potential comparator patients. RESULTS: This workflow successfully identified and enrolled a population of 446 comparator patients in a 5-month period who exhibited similar demographics, reasons for hospitalization, comorbidity burden, and utilization measures to patients enrolled in the KPACAH program. CONCLUSION: These initial findings provide promise for a workflow that can facilitate the identification of similar inpatients hospitalized at traditional brick and mortar facilities to enhance outcomes evaluations for the H@H programs, as well as to identify the potential volume of enrollees as the program expands. [ABSTRACT FROM AUTHOR]

Filters are used to remove the different types of noises including salt and pepper, Gaussian, and random noises from image. Therefore, the VLSI oriented hardware implementation of filters plays the crucial role in real time applications. However, the conventional hardware-based filters are failed to reduce the look-up-table (LUT)s, path delays, and power consumption. Therefore, this work is focused on implementation of Gammatone Median Filter (GMF) using Data Comparator (DC) logic. Initially, the multiplexer selection logic-based data comparator is used to identify the high and low values from two numbers. Then, data comparator is repeated for multiple numbers of times for nine pixels combinations, which identifies the median value from nine pixels. The subjective and objective evaluation shows that the proposed GMF-DC resulted in superior performance in terms reduced noise, hardware metrics like LUTs, delay, and power consumption as compared to state of art approaches. [ABSTRACT FROM AUTHOR]

Researchers using the ascent of human scale (AOH) to study dehumanization typically include filler groups in addition to the main comparator groups, to hide the true intent of the study. However, there is little work examining the impact of filler group choice on dehumanization ratings between groups of interest. Across two studies (including one pre-registered study) we manipulated the salience of a target out-group (i.e., the extent to which the group stood out) by embedding it within lists of other groups. By comparing AOH ratings across three conditions in which the target out-group was either high salience, medium salience, or low salience, we were able to determine the effects of target out-group salience on dehumanization. In study 1, we included participants' in-group (Canadian) in the list, and in study 2, we did not include participants in-group in the list. Results from study 1 showed that group salience had no impact on AOH ratings for the out-group when the participant in-group was included in the list. However, in study 2, when participant in-group was removed from the list, ratings for the out-group in the high salience condition were significantly lower than both the medium and low salience conditions. Implications for both theoretical and methodological issues in investigations using the AOH scale are discussed. [ABSTRACT FROM AUTHOR]

Background: In the course of the SARS-CoV-2 pandemic, multiple vaccines were developed. Little was known about reactogenicity and safety in comparison to established vaccines, e.g. influenza, pneumococcus, or herpes zoster. Therefore, the present study aimed to compare self-reported side effects in persons vaccinated against SARS-CoV-2 with the incidence of side effects in persons receiving one of the established vaccines. Methods: A longitudinal observational study was conducted over a total of 124 days using web-based surveys. Persons receiving either a vaccination against SARS-CoV-2 or one of the established vaccines (comparator group) were included. In the first questionnaire (short-term survey), 2 weeks after vaccination, mainly local and systemic complaints were evaluated. The long-term survey (42 days after vaccination) and follow-up survey (124 weeks after vaccination) focused on medical consultations for any reason. Multivariate analyses were conducted to determine the influence of the vaccine type (SARS-CoV-2 vs. comparator) and demographic factors. Results: In total, data from 16,636 participants were included. Self-reported reactogenicity was lowest in the comparator group (53.2%) and highest in the ChAdOx1 group (85.3%). Local reactions were reported most frequently after mRNA-1273 (73.9%) and systemic reactions mainly after vector-based vaccines (79.8%). Almost all SARS-CoV-2 vaccines showed increased odds of reporting local or systemic reactions. Approximately equal proportions of participants reported medical consultations. None in the comparator group suspected a link to vaccination, while this was true for just over one in 10 in the mRNA-1273 group. The multivariate analysis showed that people with SARS-CoV-2 vaccination were not more likely to report medical consultations; patients who had received a regimen with at least one ChAdOx1 were even less likely to report medical consultations. Younger age, female gender and higher comorbidity were mostly associated with higher odds of medical consultations. Conclusion: The rate of adverse reactions after established vaccinations was roughly comparable to previous studies. Two weeks after vaccination, participants in the SARS-CoV-2 vaccination group reported more local and systemic local reactions than participants in the comparator group. In the further course, however, there were no higher odds of medical consultations in either of the two groups. Thus, altogether, we assume comparable safety. Trial registration: DRKS-ID DRKS00025881 and DRKS-ID DRKS00025373. [ABSTRACT FROM AUTHOR]

Acute pharyngitis can cause sore throat. This multicentre, active-controlled, randomised, open-label, and parallel-group study, conducted according to the German Medical Devices Act, compared the effectiveness and tolerability of ERS09 mouth and throat spray with a well-established device for the treatment of sore throat caused by acute pharyngitis and dry cough. Patients were randomised 1:1 into ERS09/comparator groups (EMSER® Sore Throat Spray) for 7 ± 2 days. Patients and investigators reported effectiveness (change in total symptom score [TSS]) and safety endpoints (incidence of adverse events [AEs]; adverse device effects [ADEs]). A total of 186 patients were included (ERS09: n = 92; comparator: n = 94). The baseline-adjusted mean TSS over 7 days was −90.14 and −74.91 in the ERS09 and comparator groups, respectively (p < 0.05). The majority of patients reached a 50% reduction in symptoms by day 6 (ERS09 = 78.85; comparator = 75.8%). Most patients reported a soothing effect within five minutes (ERS09 = 82%; comparator = 71%). Improvements in individual symptoms were similar with no significant differences between groups; more patients in the ERS09 group reported an improvement in pharyngeal redness/swelling. Three AEs unrelated to medication, one ADE following ERS09, and no serious AE/ADE were reported. ERS09 was as well tolerated and effective as the established device, showing greater improvement in the management of some symptoms and greater patient preference. [ABSTRACT FROM AUTHOR]

The rapid progress in the field of fluorescent probes and fluorescent sensing material extended this research area toward more complex molecular logic gates capable of carrying out a variety of sensing functions simultaneously. These molecules are able to calculate a composite result in which the analysis is not performed by a man but by the molecular device itself. Since the first report by de Silva of AND molecular logic gate, all possible logic gates have been achieved at the molecular level, and currently, utilization of more complicated molecular logic circuits is a major task in this field. Comparison between two digits is the simplest logic operation, which could be realized with the simplest logic circuit. That is why the right understanding of the applied principles during the implementation of molecular digital comparators could play a critical role in obtaining logic circuits that are more complicated. Herein, all possible ways for the construction of comparators on the molecular level were discussed, and recent achievements connected with these devices were presented. [ABSTRACT FROM AUTHOR]

Pharmacovigilance studies based on spontaneous reporting systems use disproportionality analysis methods to identify drug‐event combinations with higher‐than‐expected reporting. Enhanced reporting is deemed as a proxy for a detected signal and is used to generate drug safety hypotheses, which can then be tested in pharmacoepidemiologic studies or randomized controlled trials. Higher‐than‐expected reporting means that the reporting rate of a drug‐event combination of interest is disproportionately higher than the rate in a specific comparator or reference set. Currently, it is unclear which comparator is the most appropriate for use in pharmacovigilance. Moreover, it is also unclear how the selection of a comparator may affect the directionality of the various reporting and other biases. This paper reviews commonly used comparators chosen for signal detection studies (active comparator, class‐exclusion comparator, and full data reference set). We give an overview of the advantages and disadvantages of each method based on examples from the literature. We also touch upon the challenges related to the derivation of general recommendations for the selection of comparators when mining spontaneous reports for pharmacovigilance. [ABSTRACT FROM AUTHOR]

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs. [ABSTRACT FROM AUTHOR]

An energy-efficient, low-noise, and high-speed dynamic comparator is proposed in this work. The comparator uses two pre-amplifiers to have a two-stage operation for reduced kickback noise. It also incorporates the adaptive current reuse (ACR) technique for reduced latency and high-speed operation. The proposed comparator is designed and simulated in a 65-nm UMC CMOS process using a 1.2-V power supply. The performance of the design is verified using post-layout simulation and also through Monte Carlo simulations. The resultant offset standard deviation of 8 mV is observed, which is 3 times less compared to the conventional design. The maximum operating frequency of the comparator is 1 GHz. The worst-case energy consumption is 67 fJ with an average latency of 70 ps. The kickback noise of 5.5 mV is observed for the entire working range, which is almost 10 times less compared to the conventional dynamic comparator at 500 MHz clock frequency. [ABSTRACT FROM AUTHOR]

This paper proposes solutions for zero-value-cross detection (ZVCD) in a single-phase mains-powered motor used for high-torque tightening. Four different applications are presented: resistor-polarized digital input, a resistor-polarized optocoupler, comparators steering up the optocoupler, and n-MOSFETs polarizing the optocoupler. The performance of each solution is evaluated in terms of complexity, dimensions, power dissipation, and response time. The n-MOSFET-based solution is found to be the most suitable, providing a simple design, low power dissipation, and almost instantaneous response. This solution meets the project's requirements for accurate and fast zero-crossing detection. [ABSTRACT FROM AUTHOR]

Background: Novel precision medicine therapeutics target increasingly granular, genomically-defined populations. Rare sub-groups make it challenging to study within a clinical trial or single real-world data (RWD) source; therefore, pooling from disparate sources of RWD may be required for feasibility. Heterogeneity assessment for pooled data is particularly complex when contrasting a pooled real-world comparator cohort (rwCC) with a single-arm clinical trial (SAT), because the individual comparisons are not independent as all compare a rwCC to the same SAT. Our objective was to develop a methodological framework for pooling RWD focused on the rwCC use case, and simulate novel approaches of heterogeneity assessment, especially for small datasets. Methods: We present a framework with the following steps: pre-specification, assessment of dataset eligibility, and outcome analyses (including assessment of outcome heterogeneity). We then simulated heterogeneity assessments for a binary response outcome in a SAT compared to two rwCCs, using standard methods for meta-analysis, and an Adjusted Cochran's Q test, and directly comparing the individual participant data (IPD) from the rwCCs. Results: We found identical power to detect a true difference for the adjusted Cochran's Q test and the IPD method, with both approaches superior to a standard Cochran's Q test. When assessing the impact of heterogeneity in the null scenario of no difference between the SAT and rwCCs, a lack of statistical power led to Type 1 error inflation. Similarly, in the alternative scenario of a true difference between SAT and rwCCs, we found substantial Type 2 error, with underpowered heterogeneity testing leading to underestimation of the treatment effect. Conclusions: We developed a methodological framework for pooling RWD sources in the context of designing a rwCC for a SAT. When testing for heterogeneity during this process, the adjusted Cochran's Q test matches the statistical power of IPD heterogeneity testing. Limitations of quantitative heterogeneity testing in protecting against Type 1 or Type 2 error indicate these tests are best used descriptively, and after careful selection of datasets based on clinical/data considerations. We hope these findings will facilitate the rigorous pooling of RWD to unlock insights to benefit oncology patients. [ABSTRACT FROM AUTHOR]

Introduction: A post hoc analysis of the PIONEER 1–5 and 8 trials assessed the clinically relevant composite endpoints of HbA1c (glycated haemoglobin) reduction ≥ 1% and body weight loss of ≥ 5% or ≥ 10% with orally administered semaglutide versus comparators. Methods: In the PIONEER trials, people with type 2 diabetes were randomised to orally administered semaglutide versus placebo (PIONEER 1, 4, 5 and 8), empagliflozin (PIONEER 2), sitagliptin (PIONEER 3) and liraglutide (PIONEER 4) for 26–78 weeks. This analysis assessed the proportion of people achieving an HbA1c reduction of ≥ 1% and body weight loss of ≥ 5% at week 26 and at end of treatment, and the proportion of people achieving an HbA1c reduction of ≥ 1% and body weight loss of ≥ 10% at end of treatment. Results: Overall, 3506 people in PIONEER 1–5 and 8 were included. At week 26 and at end of treatment, odds of achieving the composite endpoint of an HbA1c reduction of ≥ 1% and body weight loss of ≥ 5% were significantly greater with orally administered semaglutide 14 mg than with placebo (PIONEER 1, 4, 5 and 8; all p < 0.0001), empagliflozin 25 mg (PIONEER 2, p < 0.0001), sitagliptin 100 mg (PIONEER 3, p < 0.0001) and liraglutide 1.8 mg (PIONEER 4, p < 0.0001). Odds of achieving the composite endpoint of HbA1c reduction of ≥ 1% and body weight loss of ≥ 10% at end of treatment were also significantly greater with orally administered semaglutide versus comparators. Conclusion: In PIONEER 1–5 and 8, odds of achieving clinically relevant reductions in both HbA1c and body weight were significantly greater with orally administered semaglutide versus comparators. [ABSTRACT FROM AUTHOR]

In this paper, a modification is proposed in the conventional finite control set model predictive controller (FCS-MPC) applied in the three-phase voltage source inverter's (VSI's) output current control with resistive-inductive (RL) load. It comprises the introduction of the novel type of hysteresis-based comparator in the cost function evaluation implemented with a single-step prediction horizon, which represents an improvement when compared to existing solutions. In this way, effective reduction of the VSI output voltage high switching frequency is achieved, by implementing a simplified predictive current control algorithm. Also, an effective disturbance estimator algorithm is proposed, which enables the operation of a hysteresis FCS-MPC with RL load and with unmeasurable external disturbances. Simulation and experimental tests are used in the paper to prove the effectiveness of the proposed solution, showing the extent of the impact that the chosen cost evaluation comparator hysteresis value has on the resulting average power converter switching frequency, for the model predictive control current controller operating with the zero steady-state error. [ABSTRACT FROM AUTHOR]

This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases. [ABSTRACT FROM AUTHOR]

Three meta-analyses have demonstrated the clinical potential of open-label placebos (OLPs). However, there is a need to synthesize the existing evidence through more complex analyses that would make it possible to answer questions beyond mere efficacy. Such analyses would serve to improve the understanding of why and under what circumstances OLPs work (e.g., depending on induced expectations or across different control groups). To answer these questions, we conducted the first network meta-analyses in the field of OLPs. Our analyses revealed that OLPs could be beneficial in comparison to no treatment in nonclinical (12 trials; 1015 participants) and clinical populations (25 trials; 2006 participants). Positive treatment expectations were found to be important for OLPs to work. Also, OLP effects can vary depending on the comparator used. While the kind of administration route had no substantial impact on the OLP effects, effects were found to be larger in clinical populations than in nonclinical populations. These results suggest that the expectation, comparator, administration route, and population should be considered when designing and interpreting OLP studies. [ABSTRACT FROM AUTHOR]

The intrinsic high parallelism and entanglement characteristics of quantum computing have made quantum image processing techniques a focus of great interest. One of the most widely used techniques in image processing is segmentation, which in one of their most basic forms can be carried out using thresholding algorithms. In this paper, a fault-tolerant quantum dual-threshold algorithm has been proposed. This algorithm has been built using only Clifford+T gates for compatibility with error detection and correction codes. Because fault-tolerant implementation of T gates has a much higher cost than other quantum gates, our focus has been on reducing the number of these gates. This has allowed adding noise tolerance, computational cost reduction, and fault tolerance to the state-of-the-art dual-threshold segmentation circuits. Since the dual-threshold image segmentation involves the comparison operation, as part of this work we have implemented two full comparator circuits. These circuits optimize the metrics T-count and T-depth with respect to the best circuit comparators currently available in the literature. [ABSTRACT FROM AUTHOR]

In this paper, a nanosecond voltage comparator with PECL logic for a photon-counting radiation imaging system is presented. To realize a high-speed comparison of four gamma detector channels in a limited board space, quad comparators MAX9602 with PECL logic are chosen. Each of the four channels is coupled with a PECL to CMOS converter ICS508, which exports CMOS logic data for later use in an FPGA. Simulated findings for cobalt-60 with intensities ranging from 30 Ci to 300 Ci show little count loss caused by using a comparator and indicate ideal propagation delays at all source intensities. While in the laboratory test using a PCB-level system, signals with pulse width less than 3 ns might be dropped, and dispersion of propagation delay occurs. Despite these, the performance is still satisfactory and can meet the requirements of practical applications, as demonstrated by an improved result of 0.9% in the contrast indicator model. Further studies to optimize the circuit design can be conducted to gain improvement. [ABSTRACT FROM AUTHOR]

In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

This paper introduces a design for a charge pump DC-DC boost regulator with an integrated low-voltage control circuit. With a charge pump and feedback circuits implemented in 0.35 µm CMOS technology, the proposed DC-DC boost regulator offers an efficient device solution for low-power applications. The proposed design employs an error amplifier, oscillator, and comparator in the control circuit which is designed with a supply voltage of 1.8–3.5 V and 2 MHz frequency. Stability is obtained via a pole-zero compensation in the feedback circuit. The charge pump regulator with four pump stages and the whole regulator circuit are analyzed using the Cadence simulation tool. Measurements of the fabricated 0.35 µm CMOS regulator show that the transient time of the error amplifier is controlled within 1.0 µsec and the output voltage is accurately controlled from 7.8 V to 9.4 V with 27–38 mV ripple and 4.5 mA maximum current. [ABSTRACT FROM AUTHOR]

Background: Previous studies investigating potential cardiovascular adverse events of acid-suppressing drugs are susceptible to protopathic bias and confounding. We aimed to investigate the association between short-term risk of myocardial infarction (MI) and proton pump inhibitors (PPIs) using a self-controlled case series (SCCS) with an active comparator.Methods: We conducted a SCCS using a population-wide database from Hong Kong from 2003-2014. Adult with ≥1 outpatient oral PPI prescription or H2 receptor antagonist (H2RA) and MI during the observation period were included. We used both simple ratio and effect modifier approaches to SCCS with active comparators to obtain comparator adjusted estimates.Results: A total of 2802 and 1889 people with MI who had exposure to PPIs and H2RA were included respectively. We observed a higher risk of MI during days 1-14 following the start of PPI prescription (Incidence rate ratio (IRR): 2.30, 95% confidence interval (CI): 1.76-3.00) versus baseline. Similarly, we observed a higher risk of MI during days 1-14 following the start of H2RA prescription (IRR: 2.46, 95%CI: 1.92-3.16) versus baseline. In the novel SCCS analyses, comparator adjusted estimates were 0.93 (95%CI: 0.57-1.30) and 0.83 (95%CI: 0.58-1.20) during days 1-14 in simple ratio and effect modifier approach, respectively.Conclusions: We observed no difference in risk of MI associated with PPIs compared with baseline using H2RA as the active comparator. The elevated risk of MI associated with PPIs is likely due to protopathic bias. More studies are required to explore the feasibility of using active comparators in SCCS to address protopathic bias in addition to confounding. [ABSTRACT FROM AUTHOR]

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal. [ABSTRACT FROM AUTHOR]

A self-supplied circuit that is able to significantly increase the power delivered to a bridge rectifier by a Resonant Piezoelectric Vibration Energy Harvester (RPVEH) is presented and discussed. The proposed circuit, called the Energy Harvester Power Optimizer (EHPO), is implemented by means of a switch-mode converter that emulates a negative capacitance. Unlike switch-mode impedance emulators, based on sophisticated tracking algorithms requiring lossy microcontrollers, EHPO exploits a very light control circuit based on a hysteresis comparator. The EHPO is self-supplied since it does not need an external supply, but it draws the energy for its operation directly from the RPVEH. Moreover, it is developed without the assumption of purely sinusoidal vibrations. Experimental results show that the EHPO can significantly increase the power delivered to a rectifier, both in the case of sinusoidal vibrations (percent gain of the net extracted power up to about 190%) and non-sinusoidal vibrations (percent gain of the net extracted power up to about 245%), regardless of the shape of the forcing acceleration and regardless of the RPVEH resonance frequency. [ABSTRACT FROM AUTHOR]

A new water-soluble poly(propylene imine) dendrimer (PPI) modified with 4-sulfo-1,8-naphthalimid units (SNID) and its related structure monomer analog (SNIM) has been prepared by a simple synthesis. The aqueous solution of the monomer exhibited aggregation-induced emission (AIE) at 395 nm, while the dendrimer emitted at 470 nm due to an excimer formation beside the AIE at 395 nm. Fluorescence emission of the aqueous solution of either SNIM or SNID was significantly affected by traces of different miscible organic solvents, and the limits of detection were found to be less than 0.05% (v/v). Moreover, SNID exhibited the function to execute molecular size-based logic gates where it mimics XNOR and INHIBIT logic gates using water and ethanol as inputs and the AIE/excimer emissions as outputs. Hence, the concomitant execution of both XNOR and INHIBIT enables SNID to mimic digital comparators. [ABSTRACT FROM AUTHOR]

As a result of increased interest in space applications, radiation-aware circuit design has become a major concern to guarantee the safe operation of electronic systems operating under extreme space conditions. As the first step, several ad-hoc simulation approaches have been developed in analog and digital domains to estimate the functional behavior of circuits exposed to high radiation. However, most of these tools are application specific and stand-alone (not integrated into the simulation tools). Also, several commercial CAD solutions exist; however, access to these tools is limited due to security measures. To this end, we have developed a well-equipped, SPICE-integrated, and free-to-access simulation tool, RadiSPICE, capable of running statistical radiation simulations and performing extended temperature and sensitivity analyses. By using RadiSPICE, one can readily predict the functional behavior of circuits after long-term or short-term radiation effects. Moreover, the sensitivity analysis reveals vulnerabilities of the design against radiation and provides valuable design hints to the designer to make circuits radiation-hardened. To demonstrate the proposed tool, we have performed several experiments on two analog building blocks with different topologies (bandgap reference and comparator circuits) using RadiSPICE and discussed the robustness of the designs in detail. • This article presents RadiSPICE, a SPICE-integrated, free-access simulation tool. • The tool is intended for radiation-aware circuit design, for space applications. • Statistical simulations for long- and short-term radiation effects are covered. • The sensitivity analysis tool provides radiation-aware circuit design insight. • The circuit functionality after long- and short-term effects is demonstrated. • Two analog blocks are simulated and investigated for robustness in detail. [ABSTRACT FROM AUTHOR]

In this Letter, a new low‐voltage and low‐power current‐mode winner‐take‐all (WTA) circuit is proposed. The proposed circuit is able to operate with a low supply voltage requirement while exhibiting a high accuracy. Moreover, the sensitivity of the circuit to the process variations and mismatches is improved. The proposed WTA circuit is designed and simulated in a 65‐nm technology with a supply voltage of VDD = 0.9 V. The post‐layout simulation results show that the power consumption of the proposed circuit is about 72 μW with the input dynamic range of 40 μA. [ABSTRACT FROM AUTHOR]

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive-approximation register (SAR) analogue-to-digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high-resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor-resistor (C-R) hybrid digital-to-analogue converters (DACs). The prototype ADC implemented in a 28-nm CMOS process demonstrates measured differential and integral non-linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal-to-noise-and-distortion ratio (SNDR) and spuriousfree dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm² and consumes 3.98 mW at a 1.1-V supply voltage. [ABSTRACT FROM AUTHOR]

An artful complex algorithm to achieve high-efficiency high-precision multiobjective synchronous modeling and optimal solving of an analog IC is proposed. The complete approach combines response surface methodology (RSM) with an improved support vector regression (SVR) machine, which shows obvious superiority in nonlinear modeling and global solution by reduced training datasets. Targeting an analog comparator circuit as the experimental object, 33 sets of optimal design parameters are solved first in the RSM preprocessing stage, and these high-quality sample data can be subsequently input to the SVR machine for model training. In the second SVR solving stage, a differential evolution (DE) algorithm is adopted to further auto-optimize the modeling factors of the SVR machine to improve the accuracy of the nonlinear model. Finally, an SVR model of the comparator circuit can be obtained to accurately describe the response relationships of performance metrics and the corresponding design parameters that are expected by designers. With the comparator design based on TSMC 65 nm/1.2 V standard CMOS technology, we compare the SVR model-based prediction value with the Cadence-based simulation result by design test-bench and observe error lower than 3%. This work proved that the proposed complex RSM-DE-SVR algorithm is significantly practical and effective to benefit the aided optimization design of analog ICs. [ABSTRACT FROM AUTHOR]

Isavuconazole is the only US FDA-approved antifungal for treating invasive mucormycosis. We evaluated isavuconazole activity against a global collection of Mucorales isolates. Fifty-two isolates were collected during 2017–2020 from hospitals located in the USA, Europe, and the Asia-Pacific. Isolates were identified by MALDI-TOF MS and/or DNA sequencing and susceptibility tested by the broth microdilution method following CLSI guidelines. Isavuconazole (MIC50/90, 2/>8 mg/L) inhibited 59.6% and 71.2% of all Mucorales isolates at ≤2 mg/L and ≤4 mg/L, respectively. Among comparators, amphotericin B (MIC50/90, 0.5/1 mg/L) displayed the highest activity, followed by posaconazole (MIC50/90, 0.5/8 mg/L). Voriconazole (MIC50/90, >8/>8 mg/L) and the echinocandins (MIC50/90, >4/>4 mg/L) had limited activity against Mucorales isolates. Isavuconazole activity varied by species and this agent inhibited at ≤4 mg/L 85.2%, 72.7%, and 25% of Rhizopus spp. (n = 27; MIC50/90, 1/>8 mg/L), Lichtheimia spp. (n = 11; MIC50/90, 4/8 mg/L), and Mucor spp. (n = 8; MIC50, >8 mg/L) isolates, respectively. Posaconazole MIC50/90 values against Rhizopus, Lichtheimia, and Mucor species were 0.5/8 mg/L, 0.5/1 mg/L, and 2/- mg/L, respectively; amphotericin B MIC50/90 values were 1/1 mg/L, 0.5/1 mg/L, and 0.5/- mg/L, respectively. As susceptibility profiles varied among Mucorales genera, species identification and antifungal susceptibility testing are advised whenever possible to manage and monitor mucormycosis. [ABSTRACT FROM AUTHOR]

In this paper, the common-mode voltage (CMV) elimination is focused on five-phase induction motor (F-PIM) drive which is controlled by a direct torque control method. Since the motor is fed by inverter, the CMV is generated in the drive. The CMV allows common-mode current (CMC) to circulate in the bearing parts of the drive. The CMC may eventually damage the complete drive, if it is not controlled. Therefore, the proposed DTC strategy targets the elimination of the CMV. Since the F-PIM is fed by three-level five-phase inverter (T-LF-PI), there are 243 voltage vectors (VVs) available for the DTC operation. These VVs are distributed at different locations in d-q stator plane in the form of main and intermediate VVs. The 41 intermediate VVs are selected, due to their ability of eliminating the CMV, through seven-level torque and two-level flux comparators. By implementing a seven-level torque comparator (S-LTC) the torque ripple is reduced. For validating the proposed DTC method, simulation and experimental results are provided. [ABSTRACT FROM AUTHOR]

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications. [ABSTRACT FROM AUTHOR]

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 m m 2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step. • Designing a modified ADC with an ultra low supply voltage (0.2 V) for biosignals acquisition. • Designing a novel 0.2 V, ultra low power dynamic comparator. • The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. • 46% reduction of occupied area using custom capacitor design. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel technique for passively autoranging a photonic current transducer (PCT) that incorporates a current transformer (CT), piezoelectric transducer (PZT) and fiber Bragg grating (FBG). Due to the usage of single-mode fiber and FBG, multiple PCTs can be interconnected and distributed over a long distance, for example along a power network, greatly reducing the cost of sensor deployment and offering other unique advantages. The autoranging technique relies on the usage of multiple, serially connected CT burden resistors and associated static MOSFET switches to realize instantaneous shortening of the resistors in response to increasing measured current. This functionality is realized passively, utilizing a modular, μW-power comparator circuit that powers itself from the electrical energy supplied by the CT within a small fraction of the 50/60 Hz cycle. The resultant instantaneous changes in sensor gain will be ultimately detected by the central FBG interrogator through real-time analysis of the optical signals and will be used to apply appropriate gain scaling for each sensor. The technique will facilitate the usage of a single PCT to cover an extended dynamic range of the measurement that is required to realize a combined metering- and protection-class current sensor. This paper is limited to the description of the design process, construction, and testing of a prototype passive autoranging circuitry for integration with the PCT. The two-stage circuitry that is based on two burden resistors, 1 Ω and 10 Ω, is used to prove the concept and demonstrate the practically achievable circuit characteristics. It is shown that the circuit correctly reacts to input current threshold breaches of approximately 2 A and 20 A within a 3 ms reaction time. The circuit produces distinct voltage dips across burden resistors that will be used for signal scaling by the FBG interrogator. [ABSTRACT FROM AUTHOR]

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it. [ABSTRACT FROM AUTHOR]

In a conventional current-mode dc–dc buck converter, two sensed inductor current signals are processed in three separate comparators to regulate the converter under various load conditions. These independent sensing currents and comparators not only consume large quiescent current and silicon areas but also cannot guarantee the accuracy of the current limit threshold. This article proposes a current-mode dc–dc buck converter with an accurate current limit using a multiplex pulsewidth modulation (PWM) comparator. Through a multiplex PWM comparator, only one sensing current and one comparator are required to process the inductor current information and complete the regulation of the converter under various load conditions. The response speed of overcurrent protection is also increased without consuming more power and silicon area. Moreover, by generating the zero temperature coefficient (ZTC) sensing current and adding ZTC reference current with slope compensation information, the accuracy of the current limit threshold is greatly improved under various temperatures in a wide input voltage range. The proposed buck converter with a multiplex PWM comparator was fabricated using a standard 1P3M 0.18 μm BCD (BiCMOS/DMOS) process and the experimental results show that the proposed scheme functions properly in the 5-A load range, and the current limit threshold also varies only 8.1% in the temperature range from −40 to 125 °C with the input voltage up to 60 V. [ABSTRACT FROM AUTHOR]

Background: Ceftobiprole is a fifth-generation cephalosporin which has been reported to have broad antibacterial spectrum when tested against bacteria collected from other countries except China. This study evaluated the in vitro activity of ceftobiprole in comparison with other comparators against clinically significant isolates collected across from China. Results: Susceptibility testing of ceftobiprole and comparators against 1163 clinically isolated Gram-positive and Gram-negative bacteria was performed with broth micro dilution method following the CLSI guidelines. All 110 S. aureus were susceptible to ceftobiprole with MIC50/90 of 1/2 mg/L for MRSA and 0.5/1 mg/L for MSSA. For Coagulase-negative staphylococci (CNS), MIC50/90 of ceftobiprole for MRCNS and MSCNS was 1/2 mg/L and 0.25/0.5 mg/L. Ceftobiprole demonstrated good potency against E. faecalis (MIC50/90 of 0.5/1 mg/L) but limited activity against E. faecium (MIC50/90 of > 32/ > 32 mg/L). Ceftobiprole demonstrated potent activity against all 39 β-hemolytic Streptococcus spp. with MIC50/90 ≤ 0.015/ ≤ 0.015–2 mg/L and 110 of PSSP with 98.2% susceptibility. Ceftobiprole inhibited all isolates of H. influenzae and M. catarrhalis at ≤ 1 mg/L. 91.8% and 98.2% of the ESBL-negative E. coli and K. pneumoniae were susceptible to ceftobiprole, but most of the ESBL-positive or carbapenem-resistant strains were also resistant to ceftobiprole. Ceftobiprole inhibited 84.2% of carbapenem-susceptible P. aeruginosa and 94.1% of carbapenem-susceptible A. baumannii at ≤ 8 mg/L, but only 52.6% of carbapenem-resistant P. aeruginosa and 5.3% of carbapenem-resistant A. baumannii. Conclusion: Ceftobiprole demonstrated good in vitro activity against a broad range of clinically relevant contemporary Gram-positive and Gram-negative bacterial isolates. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) are based on the nanoscale and used as an alternative for Complementary Metal Oxide (CMOS) semiconductor technology. The main feature that attracts researchers in the VLSI domain of QCA is the ultra-dense structures with less power consumption and fewer transistors count. This paper presents a low energy dissipation 1-bit magnitude comparator using modified MV32 gates with minimum area. The simulation results of the proposed design have a value of 2.05 meV as total energy dissipation and 0.198 meV as average energy dissipation per cycle. Being at the nanoscale, the possibility of defects must be explored and analyzed. Therefore, the single missing cell analysis for the MV32 gate is carried out and presented in this paper. The hardware description language model is developed to analyze the faults caused by the single missing cell defects in the MV32 gate. At last, the proposed comparator is analyzed under the single missing cell defect to prove its fault tolerance. [ABSTRACT FROM AUTHOR]