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With decreasing dimensions and increasing complexity, semiconductor devices are getting more difficult to fabricate. In particular the allowed deposition temperature becomes lower. Amorphous materials, which do not require annealing steps, are therefore becoming more interesting. First principles modelling of amorphous materials is, however, way more complex than modelling crystalline ones. Especially to screen for new materials, a fully ab initio approach is hence too expensive. We take on this challenge by employing a combination of high throughput first principles calculations and artificial intelligence (AI). We construct 4500 atomistic models, each containing 200-atoms, to capture the properties of amorphous phases of primary, X-O, and binary, X-Y-O, metal oxides. For these models, we calculate the relevant properties for a transistor channel. Expanding this exercise to more complex metal oxides would lead to a prohibitively large number of options. We solve this problem by training support vector regression models based on the data generated for the primary and binary oxides to predict the properties of ternary and more complex oxides. By combining the trained models, we construct an objective function that, at its minimum, points to the optimal composition in terms of electronic performances and material stability. After screening a series of objective functions, we identify the Zn-Mg-Al-O metal oxide (Zn and Mg around 40-50 at%, Al below 10 at%) as being the most interesting improvement to the current industry standard a-IGZO for the development of a high charge carrier mobility layer of a thin film transistor compatible with low deposition temperature requirements. It is predicted to combine an improvement in terms of electron mobility and chemical stability with respect to a-IGZO. This method, combining first principles calculated data with AI, is however not restricted to finding new materials for the active layer in a thin film transistor. From a general perspective, this approach can be used for any alloy or compound discovery problem, in which the pivotal material properties can be calculated for, in the order of a thousand, relevant one- and two-element materials.

Using the deterministic version of our hot-carrier degradation (HCD) model, we perform a statistical analysis of the impact of random dopants (RDs) on the HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime, the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HCD), with exponential- and step-like shapes. First, we analyze how these localized DPs affect the transistor I-V and model the complex relation between DP and FET degradation by considering the degraded FET as a series circuit of an undegraded transistor (the source side) and a degraded one (the drain side). We also compare how the same DP causes different degradation for changes in the device structure. Second, we use the DP simulations to qualitatively understand the DP dependence on stress voltages in measured FETs and assess how uniquely a DP can be extracted from degraded I-V metrics. The results are of interest for HCD modeling.

In this study, high-performance few-layered ReS2 field-effect transistors (FETs), fabricated with hexagonal boron nitride (h-BN) as top/bottom dual gate dielectrics, are presented. The performance of h-BN dual gated ReS2 FET having a trade-off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h-BN dielectric has almost no defects and provides a physical distance between the traps in the SiO2 and the carriers in the ReS2 channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h-BN dual-gated ReS2 with a high mobility of 46.1 cm2 V−1 s−1, a high current on/off ratio of ≈106, a subthreshold swing of 2.7 V dec−1, and a low effective interface trap density (Nt,eff) of 7.85 × 1010 cm−2 eV−1 at a small operating voltage (2 channel through Y-function method as a function of constant top gate bias.

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single-and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: ( $i$ ) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-R bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond-breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with confined architectures, such as fin and nanowire (NW) FETs. Although the view on whether SH accelerates or inhibits HCD in n-channel devices is controversial, it is commonly accepted that in p-channel FETs HCD becomes more pronounced due to SH. Therefore, we develop a framework for modeling coupled HCD and SH and validate it against experimental data acquired in p-channel Si NWFETs. This framework incorporates a carrier transport solver linked to a solver for the lattice heat flow equation; the latter solver allows one to evaluate a non-uniform lattice temperature distribution in the device. Carrier energy distribution functions obtained considering coordinate-dependent lattice temperature are used to calculate the rates of the multiple- and single-carrier processes of Si H bond dissociation. In addition to perturbation of carrier transport by SH, elevated lattice temperature results in enhancement of the thermal contribution to the bond rupture rate and shortens vibrational lifetime of the Si H bond, thereby reducing the multiple-carrier process rate. All these three aspects are captured by our framework, importance of each of them is analyzed, and our approach was shown to accurately reproduce experimental data.

Simulations of hot-carrier degradation of nanowire field-effect transistors are reported. The simulations rely on the carrier energy distribution function, obtained by solving the Boltzmann transport equation. To model the contribution of impact ionization, the hydrodynamic scheme is employed. A range of pertinent physical mechanisms is invoked and discussed to adequately reproduce HCD measurements in the full ( $V_{\mathrm{g}}, V_{\mathrm{d}}$ ) bias space. Impact ionization is discussed as an important ingredient of HCD at low gate, high drain voltages.

High-performance integrated tin monoxide bottom-gate staggered p-channel thin-film transistors (TFTs) are realized and reported. The active layer has been formed by thermal vacuum evaporation and rapid thermal annealing under a continuous nitrogen flow, resulting in field-effect mobilities up to 1.6 cm2/( $\textsf {V}\cdot \textsf {s}$ ) and contact resistances of around $148~\Omega \cdot \textsf {cm}$ . The integration of these TFTs in elementary building blocks for digital circuit applications such as inverters and ring-oscillators is demonstrated, resulting in stage delays down to 300 ns. Furthermore, a unipolar p-type-only 8-bit radio frequency identification code generator is realized, achieving 12.2 kb/s and comprising 294 tin monoxide TFTs.

Hot-carrier degradation (HCD) is again becoming a growing VLSI reliability problem. This work reports hot-carrier simulations for Si nanowire field-effect transistors (NW FETs) based on the carrier energy distribution function (DF) and compares the results to measured data. The importance of impact ionization for HCD simulations is discussed. A 1-to-1 relation between the extent of interface defects generated by hot-carriers in the channel and the degradation of several FET parameters is observed.

In this work, we report on amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with medium frequency physical vapor deposited (mf-PVD) etch-stop-layer (ESL). TFT with mf-PVD ESL show comparable characteristics such as fieldeffect mobility (μFE), sub-threshold slope (SS−1) and current ratio (ION/OFF) to the conventional plasma enhanced chemical vapor deposition (PECVD) ESL based TFT, however significant differences were observed in gate bias-stress stabilities. The TFTs with mf-PVD ESL showed lower threshold-voltage (VTH) shifts compared to TFTs with PECVD ESL when stressed under a gate field of +/−1 MV/cm for duration of 104 seconds in dark and light conditions. We associate the better bias-stress stability of the mf-PVD ESL based TFT to better passivating properties and the low hydrogen content of the mf-PVD layer compared to PECVD layer.

We present an ultrahigh frequency energy harvester based on low temperature processed a-IGZO (amorphous indium-gallium-zinc oxide) semiconductor on a glass substrate. The harvester is composed of a dipole antenna, matching network, and a double half-wave rectifier and is capable of delivering more than 1 Vdc at a distance of 2 m from the transmitter antenna. In the proposed wireless system, this sensitivity corresponds to 2.75-m distance harvesting at 4-W (36 dBm) emitted power from a base station, which is within EPC regulations. The main element of the rectifier is the high-performance a-IGZO Schottky diode on glass, with a rectification ratio of 107 at ±1 V, a low threshold voltage of 0.6 V and a cutoff frequency of 3 GHz at 0 V bias.

We present vertical Schottky diodes based on amorphous IGZO with an unprecedented cutoff frequency of 1.8 GHz at 0 V bias. These diodes have a rectification ratio of up to 108 at ±1 V and a current density of 800 A/cm2 at +1 V. The diodes' high performance is achieved by understanding and modeling of the two contacts, a Schottky contact using Pd at the bottom and an ohmic contact formed at the top. In particular, the choice of the latter top contact combined with an optimized IGZO layer thickness proves to be crucial: we show how the semiconductor layer thickness and the nature of the top metal modify the doping concentration profile of the IGZO film, which we fully measure and characterize, and how that affects the performance and optimization of the diodes. We measure our diodes in rectifiers, which operate up to 1.1 GHz. Finally, we show that these rectifiers can be fully modeled in SPICE using diode parameters extracted from electrical measurements.

In this study, the authors report high-quality amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) fabricated using a new back-channel-etch (BCE) process flow on Polyethylene Naphthalate (PEN) foil. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165oC in order to ensure good overlay accuracy (< 1µm) on foil. The presented process flow differs from to previously reported by defining the Mo S/D contacts by dry etch prior to a-IGZO patterning. The TFTs show good electrical performance, including field-effect mobilities in the range of 15.0cm2/(V.s), sub-threshold slopes of 0.3V/decade and off-currents

AbstractFor the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.

It is shown in this paper that the finite resistance of the accumulation channel in amorphous In–Ga–Zn–O thin-film transistors (a-IGZO TFTs) is the main cause of the frequency dispersion of the capacitance–voltage curves in these devices. A transmission line model, accounting for the distributed nature of channel resistance, is used to explain this. Multi-frequency analysis techniques for trap density distribution use a lumped series resistance model and attribute dispersion solely to the charging and discharging of trap states. As the resistance–capacitance (RC) time constant values of the IGZO TFTs are in the range of 10–100 µs, a distributed RC network is better suited for the measured frequency range (1 kHz–1 MHz). cop. 2014 The Korean Information Display Society.

In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS. ispartof: pages:302-304 ispartof: 44th European Solid-State Device Conference - ESSDERC pages:302-304 ispartof: 44th European Solid-State Device Conference - ESSDERC location:Venice Italy date:9 Jan 2014 status: published

We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible substrates. The OFeFETs are connected serially, similar to the NAND architecture of flash memory, which offers the highest memory density of transistor memories. We demonstrate a reliable addressing scheme in this architecture, without the need for select or access transistors. As proof of principle, a 1 × 4 NAND-like string is fabricated and characterized. Retention up to one month and endurance up to 2500 cycles are shown. Read and write disturb measurements show that the memory array can potentially be scaled up to 8 kbits.

The first direct measurement is reported of the bulk density of deep states in amorphous IGZO (indium-gallium-zinc oxide) semiconductor by means of deep-level transient spectroscopy (DLTS). The device under test is a Schottky diode of amorphous IGZO semiconductor on a palladium (Pd) Schottky-barrier electrode and with a molybdenum (Mo) Ohmic contact at the top. The DLTS technique allows to independently measure the energy and spatial distribution of subgap states in the IGZO thin film. The subgap trap concentration has a double exponential distribution as a function energy, with a value of ∼1019 cm−3 eV−1 at the conduction band edge and a value of ∼1017 cm−3 eV−1 at an energy of 0.55 eV below the conduction band. Such spectral distribution, however, is not uniform through the semiconductor film. The spatial distribution of subgap states correlates well with the background doping density distribution in the semiconductor, which increases towards the Ohmic Mo contact, suggesting that these two properties share the same physical origin. ispartof: Applied Physics Letters vol:104 issue:8 status: published

High-performance Schottky diodes based on amorphous IGZO (Indium-Gallium-Zinc Oxide) semiconductor were fabricated and fully characterized. S-parameter measurements and subsequent analysis prove that these diodes have a cut-off frequency over 900MHz at 0V bias, making these diodes a promising choice for UHF applications, such as energy-harvesters for passive RFID tags on foil. Moreover, when used in a single stage rectifier, the diodes provide DC voltages higher than 1.2V at 900MHz, which is enough supply for circuitry on foil based on current metal-oxides technologies (1,2). © 2012 IEEE. ispartof: Proc. of IEDM 2012 ispartof: IEDM location:San Francisco, USA date:10 Dec - 12 Dec 2012 status: published

The ambition of printing item-level RFID tags is one of the driving forces behind printed electronics research. Organic RFID tags have been shown, initially using p-type organic semiconductors [1-4]. The introduction of n-type organic semiconductors with reasonable performance made organic CMOS conceivable [5] and organic CMOS RFID tags were shown [6]. However, all currently reported organic RFID tags are based on a tag-talks-first principle: as soon as the tag gets powered from the RF field, its code is transmitted at a data rate determined by an internal ring oscillator. Practical RFID systems will need to be able to read multiple RFID tags within the reach of the reader antenna. Existing anti-collision protocols implemented in organic RFID tags [2,4] are limited to about maximum 4 tags and come at the cost of a slow reading time. In this paper, we for the first time realize a reader-talks-first low-temperature thin-film transistor (TFT) RFID circuit. We use a complementary hybrid organic/oxide technology. As organic transistors with reasonable channel lengths ( >2 um) have a cut-off frequency below 13.56MHz, the base carrier frequency of HF communication, present technologies on foil do not yet allow to extract the circuit clock as a fraction of the base carrier. We solve this by introducing an original uplink (reader-to-tag) scheme, in which a slow clock (compatible with our transistors' speed) is transmitted as amplitude-modulation on the base carrier while data is encoded on this clock by pulse width modulation (PWM). ispartof: pages:312-313 ispartof: 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) vol:55 pages:312-313 ispartof: ISSCC location:San Francisco, USA date:19 Feb - 23 Feb 2012 status: published

We present a statistical analysis of the cumulative impact of random traps (RTs) and dopants (RDs) on hot-carrier degradation (HCD) in n-channel FinFETs. Calculations are performed at three combinations of high stress voltages and for conditions close to the operating regime. We generate 200 different configurations of devices with RDs and subsequently solve the Boltzmann transport equation to obtain the continuous interface trap concentration ${N} _{\text {it}}$ . These deterministic densities ${N} _{\text {it}}$ for each individual configuration are randomized and converted to 200 different configurations of RTs, yielding a total amount of 40,000 samples in our study. The analysis shows that at high stress voltages (with both RTs and RDs taken into account) probability densities of linear drain currents and device lifetimes are close to a bi-modal normal distribution, while in the operating regime such a trend is not visible.

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm2 per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm2/V s with Von close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at Vdd as low as 2.5 V and the inverter stage delay at Vdd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors. © 2014 Published by Elsevier B.V.