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This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 μ W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

Introduction: Though, having right set of behavioural skills is always been a priority of all organizations, nevertheless, today's organizations are investing too much on behavioural skill training to safeguard their brand value, bring-up the work culture, maintaining reputation, etc. Behavioural skills plays a vital role in personal development and well-being at student level also. This paper identifies and analyzes the fourteen behavioural skills which are vital in the personal and professional excellence development of a student. Methods: Exhaustive literature review is done and expert opinions are taken to determine the behavioural skills. Interpretive Structural Modelling is performed to analyze and prioritize these skills into strategic, operational and performance outcomes. Results: Behavioral skills are not only depicted in ones' actions but also determines thought process and attitude of a person. Result of this research shows that time management, emotional intelligence, self-development, resilience, multitasking, and open mindedness of an individual are the key behavioural skills that trigger most behaviours and eventually influences the effectiveness of management of personal and professional life. Discussion: Every job requires specific skills to perform. There are certain skills that must be possessed by every student irrespective of the discipline. It include behavioural skills like human values, resilience, multitasking, communication, etc. Research on behavioral skills and its importance are available in literature. However, the literature is lacking in explaining the interplay of these skills in driving personal and professional journey of an individual. Such skills may not be mentioned in the recruitment advertisements but are vital to perform well. [ABSTRACT FROM AUTHOR]

The paper demonstrates an efficient process flow for the Hardware Testing of an ASIC (Application Specific Integrated Circuit). The procedure is implied on Comparator, ADC (Analog-to-Digital) and Present Cipher Crypto ASIC. This involves the testing functionality of an Analog, Digital and Mixed Signal design ASIC. The results obtained during functional testing are verified through simulations on Cadence, in case of comparator and ADC ASIC, and vivado in case of Crypto ASIC. The method gives high accuracy and requires less power even at high frequency. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6 GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18- μ m CMOS technology with supply voltage of 1.8 V. The output clocks with cycle-to-cycle jitter of 2.13 ps at 1.6 GHz. The phase noise of VCO is − 137 dBc/Hz at an offset of 100 MHz and total power consumed by the proposed PLL is 2.63 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6 GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180 nm CMOS process with supply voltage of 1.8 V. The phase noise of VCO is − 1 3 7 dBc/Hz at an offset frequency of 100 MHz. The reference clock of 25 MHz synthesizes the output clock of 1.6 GHz with rms jitter of 0.642 ps. [ABSTRACT FROM AUTHOR]

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180 nm CMOS technology with 1.8 V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43 dB, 25.2 dB and 30.1 dB, respectively at 33.20 MHz input frequency and 200 MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14 mW. The calculated value of DNL and INL is < 0. 4 LSB and < 0. 5 LSB respectively. [ABSTRACT FROM AUTHOR]

This study describes the highly‐digital 4‐bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time‐to‐market and is scalable with technology. The comparators used in the ADC consist of complementary metal–oxide–semiconductor (CMOS)‐based inverter and NAND‐NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal‐to‐noise and distortion ratio, signal‐to‐noise ratio and spurious‐free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non‐linearity (DNL) of this ADC is ± 0.25 LSB and integral non‐linearity (INL) is + 0.6 LSB. [ABSTRACT FROM AUTHOR]

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply. [ABSTRACT FROM AUTHOR]