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Presents information on a study which provided an algorithm to generate, for each n>0, a universal series-parallel (SP) function for implementing all SP functions with n inputs or less in technology mapping. Use of a Field-Programmable Gate Array (FPGA) in technology mapping; Formulation of a problem; Construction of universal trees.

We used data obtained from customer contact employees in the People's Republic of China to test a moderated mediation model of the processes through which core self-evaluations (CSE) influence voice behavior. Specifically, we examined personal control and approach/avoidance motivation as psychological pathways and procedural justice perceptions as a moderator of the CSE-voice behavior relationship. As predicted, our results revealed that CSE related to employee voice behavior indirectly through personal control and approach motivation but not avoidance motivation. Furthermore, and consistent with our prediction, results showed that procedural justice perceptions moderated the mediated influence of both personal control and approach motivation on the CSE-voice behavior relationship such that this relationship is stronger when procedural justice perceptions are high but not low. We discuss the implications of these findings in terms of explanatory frameworks for understanding the documented effects of CSE on employee work outcomes. [ABSTRACT FROM AUTHOR]

Electron-beam maskless lithography is being actively explored by the semiconductor industry for chip production in the sub-22 nm regime. Character projection allows in one e-beam shot the printing of complex pattern rather than merely a single rectangle or triangle as in variable-shaped beam projection. However, those circuit patterns that do not match any character on the stencil still have to be written by variable-shaped beam projection. We investigate a new problem of character and stencil co-optimization with blank space sharing between characters so as to minimize the total number of shots required for printing a circuit. We exploit the fact that the blank spaces on the sides of a character can be adjusted by moving the pattern to be printed within its projection region to facilitate blank space sharing so as to pack more characters into the stencil. Even though the co-optimization problem is shown to be NP-complete, we are able to design an elegant approximation algorithm, CASCO. Experiments confirm that the solutions by CASCO are nearly optimal. Compared to the published state-of-the-art, CASCO reduces the shot count by 1.59 times, while it is also orders of magnitude faster. [ABSTRACT FROM PUBLISHER]

This study examined psychological mechanisms that underpin the relationships between perceived organizational family support (POFS) and a family-supportive supervisor (FSS) on employee work behaviors. Based on data from employed parents and their supervisors (N = 230) in 12 South Korean organizations, structural equation modeling results revealed three salient findings: (1) POFS and FSS are indirectly related to contextual performance through control over work time, (2) FSS is indirectly related to both contextual performance and work withdrawal through organization-based self-esteem (OBSE), and (3) control over work time is indirectly related to the two work outcomes through OBSE. The authors interpret these findings as indicating support for the focus on informal workplace family support and the need for research to examine the psychological resources they engender if we are to understand why these forms of support have their demonstrated outcomes. [ABSTRACT FROM PUBLISHER]

The article reflects on a study which investigates the reliability and validity of selfadministered Chinese Shortness of Breath Questionnaire (SOBQ) with pictorial enhancement(C-SOBQ), an instrument for assessing the impact of dyspnoea on daily activities of patients with different lung diseases. The study focuses on the patients suffering from chronic obstructive pulmonary disease (COPD) to check the reliability of the instrument to enhance the clinical application of the instrument.

Wire bonding is currently the most popular method for connecting signals between dies in system-in-package (SiP) design. Pad assignment, which assigns inter-die signals to die pads so as to facilitate wire bonding, is an important physical design problem for SiP design because the quality of a pad assignment solution affects both the cost and the performance of an SiP design. In this paper, we study a pad assignment problem, which prohibits the generation of illegal crossings and aims to minimize the total signal wirelength, for die-stacking SiP design. We first consider the two-die cases and die-stacks with a bridging die, and present a minimum-cost flow-based approach to optimally solve them in polynomial time. We then describe an approach, which uses a modified left-edge algorithm and an integer linear programming technique, for pyramid die-stacks with no bridging die. Finally, we discuss extensions of the two approaches to handle additional design constraints. Encouraging experimental results are shown to support our approaches. [ABSTRACT FROM AUTHOR]

In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT) algorithm called fast lookup table estimation (FLUTE). FLUTE is based on a precomputed lookup table to make RSMT construction very fast and very accurate for low-degree' nets. For high-degree nets, a net-breaking technique is proposed to reduce the net size until the table can be used. A scheme is also presented to allow users to control the tradeoff between accuracy and runtime. FLUTE is optimal for low-degree nets (up to degree 9 in our current implementation) and is still very accurate for nets up to degree 100. Therefore, it is particularly suitable for very large scale integration applications in which most nets have a degree of 30 or less. We show experimentally that, over 18 industrial circuits in the ISPD98 benchmark suite, FLUTE with default accuracy is more accurate than the Batched 1-Steiner heuristic and is almost as fast as a very efficient implementation of Prim's rectilinear minimum spanning tree algorithm. [ABSTRACT FROM AUTHOR]

In this paper, we study the retiming problem of sequential circuits with net topology optimization. Both interconnect and gate delay are considered in retiming. Most previous retiming algorithms have assumed ideal conditions for the nonlogical portions of data paths, which are not sufficiently accurate to be used in high-performance circuits today. In our modeling, we assume that the delay of a wire is directly proportional to its length. This assumption is reasonable since the quadratic component of a wire delay is significantly smaller than its linear component when the more accurate Elmore delay model is used. A simple experiment was conducted to illustrate the validity of this assumption. We present two approaches to solve the retiming problem, both of which have polynomial time complexity. The first one can compute the optimal clock period, while the second one is an improvement over the first one in terms of practical applicability. The second approach gives solutions that are very close to the optimal (0.06% more than the optimal on average) but in a much shorter runtime. The optimally retimed circuit will then be realized physically by placing the registers and finding the net topologies. In contrast to many previous works [Proc. IEEE mt. Conf. Comput.-Aided Des., p. 136, 1998], [IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., 22(7) Jul. 2003] that performed simple calculations to determine the register positions, our approach can preserve the optimal clock period that is obtained by the retiming step and utilize as few registers as possible. Minimization of register number saves both area and power in register and clock loading. Our topology optimization step is shown to be optimal for nets with four or fewer pins, and this type of nets constitutes over 90% of the nets in a sequential circuit on average. Using the ISCAS89 benchmark, we tested our algorithm with a 0.35-μsm complementary metal-oxide-semiconductor standard cell library. Silicon Ensemble was used to layout the design with a row utilization of 50%. Experimental results showed that our algorithm could find the best sharing of registers for a net in most of the cases, i.e., using the minimum number of registers while preserving the target clock period that is obtained by the retiming step, within a minute run on an Intel Pentium IV 1.5 GHz PC with 512 MB RAM. [ABSTRACT FROM AUTHOR]

To achieve timing closure in a placed design, buffer insertion and driver sizing are two of the most effective transforms that can be applied. Since the driver-sizing solution and the buffer-insertion solution affect each other, sub optimal solutions may result if these techniques are applied sequentially instead of simultaneously. We show how to simply extend van Ginneken's buffer-insertion algorithm to simultaneously incorporate driver sizing and introduce the idea of a delay penalty to encapsulate the effect of driver sizing on the previous stage. The delay penalty can be pre computed efficiently via dynamic programming. Experimental results show that using driver sizing with a delay-penalty function obtains designs with superior timing and area characteristics. [ABSTRACT FROM AUTHOR]

Many previous works on floorplanning with non rectangular modules [1]-[12] assume that the modules are predesignated to have particular non rectangular shapes, e.g., L-shaped, T-shaped, etc. However, this is not common in practice because rectangular shapes are more preferable in many designing steps. Those non rectangular shapes are actually generated during floor planning in order to further optimize the solution. In this paper, we study this problem of changing the shapes and dimensions of the flexible modules to fill up the unused area of a preliminary floor plan, while keeping the relative positions between the modules unchanged. This feature will also be useful in fixing small incremental changes during engineering change order modifications. We formulate the problem as a mathematical program. The formulation is such that the dimensions of all of the rectangular and, nonrectangular modules can be computed by closed-form equations in O(m) time in each corresponding Lagrangian relaxation sub problem (LRS) where m is the total number of edges in the constraint graphs. As a result, the total time for the whole shaping and sizing process is O(k × m), where k is the number of iterations on the LRS. Experimental results show that the amount of area reused is 3.7% on average, while the total wirelength can be reduced by 0.43% on average because of the more compacted result packing. [ABSTRACT FROM AUTHOR]

A floorplan can be defined as a rectangular dissection of the floorplan region. Simple and tight asymptotic bounds on the number of floorplans for different dissection structures help us to evaluate the size of the solution space of different floorplan representation. They are also interesting theoretically. However, only loose bounds exist in the literature. In this paper, we derive tighter asymptotic bounds on the number of slicing, mosaic and general floorplans. Consider the floorplanning of n blocks. For slicing floorplan, we prove that the exact number is Multiple line equation(s) cannot be represented by ASCII text and the tight bound is Θ(n!2[sup 2.543n]/n[sup 1.5]) [9]. For mosaic floorplan, we prove that the fight bound is Θ(n!2[sup 3n]/n[sup 4]). For general floorplan, we prove a tighter lower bound of Ω(n[sub 2][sup 3n]/n[sup 4]) and a fighter upper bound of O(n!2[sup 5n]/n[sup 4.5]). [ABSTRACT FROM AUTHOR]