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In this brief, we study jitter behavior in an event-driven self-sampled model of an All-Digital Phase-Locked Loop. We provide its steady-state analysis using simulations of a discrete-time model. We show that digital jitter, a function of two control parameters of the model, can be mapped onto a on-dimensional manifold and approximated via a simple function. The latter can be used to perform jitter optimisation under constraints for the control parameters. The verification is done through FPGA measurements and shows excellent agreement with the analytic approximation.

In this paper, we study networks of coupled oscillators applied to the distributed synthesis of clock signals for large systems-on-chip. The oscillators are implemented as interconnected all-digital phase-locked loops (ADPLLs), which are asynchronous control systems. We address the issue of modelling, synchronization and stability of both a single ADPLL and interconnected ADPLLs. We prove that the stability domain is universal for large Cartesian networks, and it related to the domain for a single ADPLL. We show that within the stability domain the network synchronises to the reference signal both in frequency and phase. A hardware verification of Cartesian networks is presented, and it is consistent with our theoretical findings. The proposed design may be useful for multiples engineering and physics applications, including clock generation, distributed computations, beamforming, and other applications, where the control over time synchronicity is crucially important for the system performance.

This letter presents a single-electron injection device for position-based charge qubit structures implemented in 22-nm fully depleted silicon-on-insulator CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5-nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small $0.7\times 0.4\,\,\mu \text{m}^{2}$ elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2-GHz clock frequency. With this apparatus, we demonstrate a single-electron injection into a quantum dot.

This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies $3.5\times 45\,\,\mu \text{m}^{2}$ and consumes 0.27mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1mW (including its output driver) with an area of $40\times 25\,\,\mu \text{m}^{2}$ . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 $\mu \text{V}$ -rms is estimated through mathematical analysis while the ≤ 0.225mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.

International audience; The immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications. This paper presents a design of such an oscillator with a high frequency resolution and small area in 28 nm technology. In order to reduce the dependence of the oscillator frequency on its voltage supply, differential amplifiers are used as inverters (delay cells) and a bias circuit with a stable voltage output is employed to bias the oscillator. From post-layout simulations, this DCO achieves a dynamic range from 1.13 to 1.54 GHz with the use of differential delay cells, the variation of the output frequency is less than 4.5% over all the frequency range, for VDD variation of 10%. The frequency control has 9.2 bits, giving an average frequency step of 722 kHz. This DCO achieves a phase noise of-74 dBc/Hz@1MHz or an jitter equivalence of 2.3 ps. The maximal power consumption of this DCO at maximum frequency is 840 µW, which is a low figure comparing to the state-of-the-art implementation with typical power of sub-milliwatts for the similar frequency range. Index Terms-All-Digital Phase Locked Loop (ADPLL), Digitally controlled oscillator (DCO), differential inverter ring

The construction of quantum computer simulators requires advanced software which can capture the most significant characteristics of the quantum behavior and quantum states of qubits in such systems. Additionally, one needs to provide valid models for the description of the interface between classical circuitry and quantum core hardware. In this study, we model electron transport in semiconductor qubits based on an advanced CMOS technology. Starting from 3D simulations, we demonstrate an order reduction and the steps necessary to obtain ordinary differential equations on probability amplitudes in a multi-particle system. We compare numerical and semi-analytical techniques concluding this paper by examining two case studies: the electron transfer through multiple quantum dots and the construction of a Hadamard gate simulated using a numerical method to solve the time-dependent Schrodinger equation and the tight-binding formalism for a time-dependent Hamiltonian.

In this paper, we propose an optimization method for the construction of two-qubit and two-qudit quantum gates based on semiconductor position-based charge qubits. To describe the evolution of various quantum states, we use a Hubbard based model and Lindblad formalism. The suggested optimization algorithm uses the time evolution of entanglement entropy and mutual information for the determination of the system parameters to achieve high fidelity gates.

This work is aimed at the development of a path-based approach to Statistical Static Timing Analysis. Timing Analysis is an absolutely essential step in the verification of Very Large Scale Integration (VLSI) designs. We propose a novel analytical methodology for the fast calculations of VLSI delay. The problem is stated in such a way that becomes equivalent to finding the maximum of a large set of correlated random variables (RVs). For this purpose, a corresponding extension of extreme value theory of weakly-correlated RVs is developed. Results of simulations showing a comparison of our approach with Monte Carlo simulations are presented. Possible applications, extensions of our methodology and future steps are discussed.

In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.

In this paper, we introduce a statistical approach for studying a special class of nonlinear dynamical systems such as ADPLLs and ADPLL networks, where the process driving the adjustment of the DCO frequency can be seen as ∑Δ modulation. We showed that, by applying the Frobenius-Perron operator to the governing equation, it is possible to find the invariant probability density which is valid for dynamically changing input of ∑Δ modulator. By using this, we show that the average behaviour of the corresponding complex system can be dramatically simplified and studied analytically.

In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.

International audience; In this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.

In this paper we consider a network of phase oscillators. We develop the equations that model the time evolution of the phase of each oscillator in the network. The oscillator represents a modified Kuramoto oscillator and in this study we discuss how these modifications are obtained. In the context of this study, we use this network to model a network of PLLs for distributed clock applications. We analyse analytically and numerically the synchronisation modes of this system for different types of the coupling function. We show that depending on the properties of the coupling function, the network displays either multiple coexisting synchronisation modes or only a single synchronisation mode. While in the context of clock generation, multiple synchronisation modes coexisting in the system at the same parameters are a parasitic phenomenon. However in the context of other application such as associative memory models, mode-locking can be seen a useful phenomenon. The results provide a deeper understanding of globally synchronised clock networks with applications in microprocessor design.