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This brief proposes a 102-Gb/s eight-level pulse amplitude modulation (PAM-8) wireline receiver frontend system with high linearity. The receiver adopts a strategy wherein the differential signal undergoes division in the analog domain before equalization. The bias shifters control the common-mode voltage of the input signal to provide distinct dynamic regions for multiple equalizer pathways. The bias shifter circuits employing passive devices ensure both power saving and full linearity. The proposed PAM-8 receiver frontend operates at 102 Gb/s with an efficiency of 1.61 pJ/b and a linear input range of 1.4-Vppd in 28-nm CMOS.

This paper presents a high-speed single-ended 4-level pulse amplitude modulation (PAM-4) transceiver for next-generation memory interfaces, achieving a data rate of 32Gb/s. The proposed asymmetrically terminated PAM-4 driver is optimized for pseudo open drain (POD) channel configurations and improves signal-to-noise ratio (SNR) with a larger output swing. The dynamic logic-based high-speed 4-to-1 serializer enhances the transmitter output’s jitter characteristic by avoiding high-frequency components in the selection signals. The 4-tap feed-forward equalizer (FFE) with two operation modes and one sliding tap flexibly compensates for inter-symbol interference (ISI) of the channel. In the receiver frontend, a continuous-time linear equalizer (CTLE), which utilizes a trans-admittance stage (TAS) and a trans-impedance amplifier (TIA) with an inductive load, provides high-frequency boosting and robust single-to-differential conversion performance through the design techniques of current source gain-boosting and capacitive compensation. The low kickback noise comparators mitigate clock feedthrough and noise coupling during multi-phase PAM-4 sampling and embed the 1-tap PAM-4 decision feedback equalizer (DFE) operation by directly feeding back the previous sampling phase’s outputs. The transceiver prototype fabricated in 28-nm CMOS technology occupies 0.126 mm2. At 32 Gb/s, a bit error rate of under $10^{-12}$ was achieved with a 6.25% eye margin and an energy efficiency of 3.37 pJ/bit while equalizing the 6.87-dB channel loss at 8 GHz.

This brief solves the challenge of loop latency in the digital filter of conventional digital phase-locked loops (DPLLs), which hinders timely updates of phase frequency detector error information. To address this latency problem, we introduce a direct path for jitter correction, utilizing a pulse generator with an adaptive pulse width controller (PWC). The impact of PWC-based phase correction is analyzed to optimize the proportional gain in DPLLs. The DPLL, designed with adaptive gain control and realized in 40-nm CMOS technology, significantly enhances its performance metrics. Operating from a 100-MHz reference clock to produce a 3.2-GHz output, the prototype achieves a power consumption of 6.36 mW. Remarkably, the measurements indicate a 25% improvement in integrated jitter, reduced from 1231 to 942 fs, while maintaining comparable reference spur performance relative to conventional DPLL designs.

A low-dropout (LDO) regulator controlled by an inverter-based amplifier is proposed to accomplish the latest processor power requirements. The proposed inverter-based amplifier provides a high DC gain in low-voltage operation. Furthermore, an auxiliary non-inverting amplifier is adopted to regulate the wider output voltage and enhance power supply rejection ratio (PSRR) performance. The proposed LDO regulator has been implemented in a 28-nm CMOS process and provides an output range of 0.2–1.05 V from the input range of 0.4–1.1 V. With the input voltage of 1 V, the settling time is within 71.8 ns for 50-mV overshoot and 63 ns for 47-mV undershoot. With the low input voltage of 600 mV, the settling time is within 269 ns for 81-mV overshoot and 182 ns for 84-mV undershoot. The measured values of PSRR are 44.3 dB and 25.0 dB at 100 kHz and 10 MHz at 1-V input voltage, respectively. The PSRR with 600-mV input voltage shows 30 dB up to 600 kHz.

This brief presents a 100-Gb/s eight-level pulse amplitude modulation (PAM-8) transmitter (TX) for next-generation wireline communication systems. The high-swing hybrid driver combines the cascode current-mode logic (CML) and tailless CML techniques for higher bandwidth, output resistance, and wide feed-forward equalizer (FFE) tap control range. The transmitter employs a reconfigurable 3-tap FFE for adaptive channel equalization. The design achieves a 100-Gb/s data rate with worst-case eye-opening values of 52 mV with FFE and 1.5-V peak-to-peak differential (Vppd) output swing without FFE. The transmitter test chip is fabricated in a 40-nm CMOS technology and the measured energy efficiency is 4.42 pJ/bit.

This brief describes a channel-loss-tolerant 35-Gb/s PAM-4 transmitter with feed-forward equalization (FFE) for high-speed wireline interfaces. The proposed transmitter adopts 7B4Q full transition avoidance (FTA) coding in combination with the 2-tap FFE to improve the worst-case horizontal eye-opening in the presence of inter-symbol interference (ISI). The input and output bit widths (7-bit input and 8-bit (4Q) output) and the encoder structure are selected to achieve a high data-rate with a synthesizable encoder hardware. Additionally, an area-efficient gm-boosting voltage-mode driver is used to enhance the transition slope. The transmitter test chip was fabricated in a 28-nm CMOS process and occupied 0.18 mm2. The design achieved 35-Gb/s with a 0.95x wider horizontal eye-opening by adopting the FTA coding for a 5.2-dB loss channel.

In this brief, a four-level pulse amplitude modulation (PAM-4) receiver for single-ended memory interfaces is presented. The frontend signaling path is optimized to maximize the receiver’s bandwidth in combination with a T-coil that mitigates the loading effect of the electrostatic discharge (ESD) protection cell. The following continuous-time linear equalizer (CTLE) employs an inverter-based TAS-transimpedance (TIA) stage in a subtraction configuration to compensate for the channel loss. The dual-path T-coil is optimally designed for the CTLE core based on the characteristics of the low and high-frequency signaling paths of the subtractive equalizer to maximize the bandwidth of the high-frequency path. The complementary transconductances with current biasing achieve high gain, wide linearity, and high power supply rejection ratio (PSRR). The output common-mode of the CTLE is balanced across the entire input range by adopting an auxiliary TAS and suppressing the gain mismatch. The proposed single-ended PAM-4 receiver is fabricated in a 40-nm CMOS technology and occupies 0.014 mm2. The design operates at 28-Gb/s with a $10^{-12}$ bit error rate (BER) and consumes 21.51 mW, which corresponds to 0.77-pJ/bit energy efficiency.

A noise-immune spatial-delta coding (SDC) scheme is proposed for single-ended multi-lane links. The SDC technique allows differential sensing of single-ended PAM2 signals for high signal integrity while still achieving the same pin efficiency as the 8b9b data bus (DBI) scheme, providing high compatibility with conventional DDR interfaces. The SDC encoding/decoding functions are implemented with simple XOR gates to minimize power and latency overhead. Continuous-time linear equalizers in the receiver compensate for distortions in incoming pseudo-differential signals with high tolerance on dynamic common-mode switching associated with the SDC operation. An 8b9b SDC transceiver prototype array composed of nine data channels and a differential clock channel has been fabricated in 28-nm CMOS technology for demonstration. The transceiver array achieves a 77.44 Gb/s aggregate data rate with 9 wires at 9.68 Gbaud/s. The bit error rate is measured to be less than 1e-12 while consuming 4.9 pJ/b from a 1.25-V supply.