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In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO 2 coupled with Al 2 O 3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10 -10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.

The time-dependent variability of nanoscaled Si0.45 Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as 1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology.

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.

In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting soft breakdown (SBD) and post-SBD wear-out (WO) parameters from measuring the time to hard breakdown (t HBD) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model that includes SBD and WO.

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

Este trabajo presenta el desarrollo de un modelo termo-eléctrico de elementos finitos (EF) con el fin de analizar los mecanismos de falla responsables de la degradación física causada por alta densidad de corriente en contactos de cobre de 90 nm empleados en dispositivos FinFET. De hecho en [1], esta degradación física fue interpretada como consecuencia principal del efecto Joule, sin embargo el modelo empleado alcanzó temperaturas demasiado bajas comparadas con el daño observado. Con el propósito de confirmar esta hipótesis, el modelo de EF de estado estable desarrollado en este trabajo calcula el incremento y la distribución de temperatura causada por alta densidad de corriente eléctrica fluyendo a través de un contacto de cobre, tomando en cuenta interfaces eléctricas y térmicas no idealizadas. Además, un análisis de sensibilidad fue realizado como un medio para identificar parámetros críticos de falla. La respuesta del modelo ante la variación independiente de la resistividad eléctrica de los materiales estudiados, y las conductancias eléctricas y térmicas entre el contacto de cobre y su barrera de difusión fue obtenida. La disminución de la conductancia eléctrica de dicha interfaz desencadenó temperaturas de estado estable superiores a los puntos de fusión del cobre y los silicatos del contacto y, en consecuencia, permite explicar la degradación física observada.