28 results on '"Wang, Erwei"'
Search Results
2. Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks
- Author
-
Joksas, Dovydas, Wang, Erwei, Barmpatsalos, Nikolaos, Ng, Wing H., Kenyon, Anthony J., Constantinides, George A., and Mehonic, Adnan
- Subjects
Computer Science - Emerging Technologies - Abstract
Recent years have seen a rapid rise of artificial neural networks being employed in a number of cognitive tasks. The ever-increasing computing requirements of these structures have contributed to a desire for novel technologies and paradigms, including memristor-based hardware accelerators. Solutions based on memristive crossbars and analog data processing promise to improve the overall energy efficiency. However, memristor nonidealities can lead to the degradation of neural network accuracy, while the attempts to mitigate these negative effects often introduce design trade-offs, such as those between power and reliability. In this work, we design nonideality-aware training of memristor-based neural networks capable of dealing with the most common device nonidealities. We demonstrate the feasibility of using high-resistance devices that exhibit high $I$-$V$ nonlinearity -- by analyzing experimental data and employing nonideality-aware training, we estimate that the energy efficiency of memristive vector-matrix multipliers is improved by three orders of magnitude ($0.715\ \mathrm{TOPs}^{-1}\mathrm{W}^{-1}$ to $381\ \mathrm{TOPs}^{-1}\mathrm{W}^{-1}$) while maintaining similar accuracy. We show that associating the parameters of neural networks with individual memristors allows to bias these devices towards less conductive states through regularization of the corresponding optimization problem, while modifying the validation procedure leads to more reliable estimates of performance. We demonstrate the universality and robustness of our approach when dealing with a wide range of nonidealities., Comment: 32 pages, 20 figures, 4 tables
- Published
- 2021
- Full Text
- View/download PDF
3. Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference
- Author
-
Wang, Erwei, Davis, James J., Stavrou, Georgios-Ilias, Cheung, Peter Y. K., Constantinides, George A., and Abdelfattah, Mohamed S.
- Subjects
Computer Science - Machine Learning ,Computer Science - Hardware Architecture - Abstract
FPGA-specific DNN architectures using the native LUTs as independently trainable inference operators have been shown to achieve favorable area-accuracy and energy-accuracy tradeoffs. The first work in this area, LUTNet, exhibited state-of-the-art performance for standard DNN benchmarks. In this paper, we propose the learned optimization of such LUT-based topologies, resulting in higher-efficiency designs than via the direct use of off-the-shelf, hand-designed networks. Existing implementations of this class of architecture require the manual specification of the number of inputs per LUT, K. Choosing appropriate K a priori is challenging, and doing so at even high granularity, e.g. per layer, is a time-consuming and error-prone process that leaves FPGAs' spatial flexibility underexploited. Furthermore, prior works see LUT inputs connected randomly, which does not guarantee a good choice of network topology. To address these issues, we propose logic shrinkage, a fine-grained netlist pruning methodology enabling K to be automatically learned for every LUT in a neural network targeted for FPGA inference. By removing LUT inputs determined to be of low importance, our method increases the efficiency of the resultant accelerators. Our GPU-friendly solution to LUT input removal is capable of processing large topologies during their training with negligible slowdown. With logic shrinkage, we better the area and energy efficiency of the best-performing LUTNet implementation of the CNV network classifying CIFAR-10 by 1.54x and 1.31x, respectively, while matching its accuracy. This implementation also reaches 2.71x the area efficiency of an equally accurate, heavily pruned BNN. On ImageNet with the Bi-Real Net architecture, employment of logic shrinkage results in a post-synthesis area reduction of 2.67x vs LUTNet, allowing for implementation that was previously impossible on today's largest FPGAs., Comment: Accepted manuscript uploaded 04/12/21. DOA 22/11/21
- Published
- 2021
- Full Text
- View/download PDF
4. Accelerating Recurrent Neural Networks for Gravitational Wave Experiments
- Author
-
Que, Zhiqiang, Wang, Erwei, Marikar, Umar, Moreno, Eric, Ngadiuba, Jennifer, Javed, Hamza, Borzyszkowski, Bartłomiej, Aarrestad, Thea, Loncar, Vladimir, Summers, Sioni, Pierini, Maurizio, Cheung, Peter Y, and Luk, Wayne
- Subjects
Computer Science - Machine Learning ,Computer Science - Hardware Architecture ,Physics - Instrumentation and Detectors - Abstract
This paper presents novel reconfigurable architectures for reducing the latency of recurrent neural networks (RNNs) that are used for detecting gravitational waves. Gravitational interferometers such as the LIGO detectors capture cosmic events such as black hole mergers which happen at unknown times and of varying durations, producing time-series data. We have developed a new architecture capable of accelerating RNN inference for analyzing time-series data from LIGO detectors. This architecture is based on optimizing the initiation intervals (II) in a multi-layer LSTM (Long Short-Term Memory) network, by identifying appropriate reuse factors for each layer. A customizable template for this architecture has been designed, which enables the generation of low-latency FPGA designs with efficient resource utilization using high-level synthesis tools. The proposed approach has been evaluated based on two LSTM models, targeting a ZYNQ 7045 FPGA and a U250 FPGA. Experimental results show that with balanced II, the number of DSPs can be reduced up to 42% while achieving the same IIs. When compared to other FPGA-based LSTM designs, our design can achieve about 4.92 to 12.4 times lower latency., Comment: Accepted at the 2021 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
- Published
- 2021
- Full Text
- View/download PDF
5. Enabling Binary Neural Network Training on the Edge
- Author
-
Wang, Erwei, Davis, James J., Moro, Daniele, Zielinski, Piotr, Lim, Jia Jie, Coelho, Claudionor, Chatterjee, Satrajit, Cheung, Peter Y. K., and Constantinides, George A.
- Subjects
Computer Science - Machine Learning ,Computer Science - Hardware Architecture - Abstract
The ever-growing computational demands of increasingly complex machine learning models frequently necessitate the use of powerful cloud-based infrastructure for their training. Binary neural networks are known to be promising candidates for on-device inference due to their extreme compute and memory savings over higher-precision alternatives. However, their existing training methods require the concurrent storage of high-precision activations for all layers, generally making learning on memory-constrained devices infeasible. In this article, we demonstrate that the backward propagation operations needed for binary neural network training are strongly robust to quantization, thereby making on-the-edge learning with modern models a practical proposition. We introduce a low-cost binary neural network training strategy exhibiting sizable memory footprint reductions while inducing little to no accuracy loss vs Courbariaux & Bengio's standard approach. These decreases are primarily enabled through the retention of activations exclusively in binary format. Against the latter algorithm, our drop-in replacement sees memory requirement reductions of 3--5$\times$, while reaching similar test accuracy in comparable time, across a range of small-scale models trained to classify popular datasets. We also demonstrate from-scratch ImageNet training of binarized ResNet-18, achieving a 3.78$\times$ memory reduction. Our work is open-source, and includes the Raspberry Pi-targeted prototype we used to verify our modeled memory decreases and capture the associated energy drops. Such savings will allow for unnecessary cloud offloading to be avoided, reducing latency, increasing energy efficiency, and safeguarding end-user privacy.
- Published
- 2021
6. Rethinking binary neural network design for FPGA implementation
- Author
-
Wang, Erwei and Cheung, Peter
- Abstract
Research has shown that deep neural networks contain significant redundancy, and that high classification accuracy can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates during inference. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inefficiency has also been spotted in BNN training: high-precision gradients and intermediate activations become redundant because we only care about weights' signs. My PhD focusses around increasing the efficiency of BNN inference and training on FPGAs. For inference, I propose expanding BNN's inference operator to utilize LUTs' full expressiveness. I also found various redundancies in the standard BNN training method, and proposed improvements to reduce them. With the promising improvements in area, energy and memory efficiency demonstrated in my works, my research makes BNN a more promising architecture for resource-constrained AI deployment. To make BNNs embrace the full capabilities of the LUT, I propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. I demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy, when implemented on a single fully-unrolled layer. Against the state-of-the-art binarised neural network implementation, I achieve twice the area efficiency for several standard network models when inferencing popular datasets. I also demonstrate that even greater energy efficiency improvements are obtainable. Although implementing just one network layer using the unrolled LUTNet architecture leads to significant area efficiency gains for a given modern DNN, their complexity makes whole-network unrolled LUTNet implementation infeasible. Given a fixed-sized FPGA, tiling allows us to trade off throughput and efficiency for additional accuracy by enabling our architecture to be used to implement a greater proportion--including all--of the target network. Therefore, I extend LUTNet's training program to natively support network tiling, allowing inference nodes to be shared between operations both within and across channels. In this new architecture, each physical K-LUT can inference as one of many (K-P):1 logical LUTs, selected by P runtime selection bits streaming from BRAMs. This tiled architecture, (K, P)-LUTNet, facilitates whole-network LUTNet deployment on current-generation FPGAs. I comprehensively explore the tiling factor space offered by this tiling-friendly architecture, finding that (K, P)-LUTNet can achieve up to 1.28x in area savings and 1.57x in energy efficiency gains against the BNN baseline. With logic expansion, there is a significant increase in network complexity leading to greater expressiveness, but at the cost of longer training time. Hence, manually fine tuning K for each individual LUT is infeasible. Also, the LUT inputs are randomly connected which do not guarantee a good choice of network topology. Therefore, in addition to logic expansion, I propose logic shrinkage which allows the network to learn its choice of K and input connections for each LUT via fine-grained activation pruning. Saliency of each LUT input is evaluated and low-importance connections removed, thereby improving the efficiency of the resultant LUTNet netlist. With logic shrinkage, I achieve 1.54x the area efficiency and 1.31x the energy efficiency over LUTNet for CNV network classifying CIFAR-10. The above works focus on BNN's redundancies in inference. I also spotted redundancies in the training process of BNN, which serve as starting points for LUTNet. The ever-growing computational demands of increasingly complex machine learning models frequently necessitate the use of powerful cloud-based infrastructure for their training. I introduce a low-cost binary neural network training strategy exhibiting sizable memory footprint reductions and energy savings vs Courbariaux & Bengio's standard approach. Against the latter, my method reduces coincident memory requirement and energy consumption by a factor of 2-6x, while reaching similar test accuracy in comparable time, across a range of small-scale models trained to classify popular datasets. I also showcase ImageNet training of ResNetE-18, achieving a 3.12x memory reduction over the aforementioned standard. Such savings will allow for unnecessary cloud offloading to be avoided, reducing latency, increasing energy efficiency and safeguarding privacy.
- Published
- 2021
- Full Text
- View/download PDF
7. LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference
- Author
-
Wang, Erwei, Davis, James J., Cheung, Peter Y. K., and Constantinides, George A.
- Subjects
Computer Science - Machine Learning ,Computer Science - Computer Vision and Pattern Recognition ,Electrical Engineering and Systems Science - Signal Processing ,Statistics - Machine Learning - Abstract
Research has shown that deep neural networks contain significant redundancy, and thus that high classification accuracy can be achieved even when weights and activations are quantized down to binary values. Network binarization on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We describe the realization of both unrolled and tiled LUTNet architectures, with the latter facilitating smaller, less power-hungry deployment over the former while sacrificing area and energy efficiency along with throughput. For both varieties, we demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarized neural network implementation, we achieve up to twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable., Comment: arXiv admin note: substantial text overlap with arXiv:1904.00938. Accepted manuscript uploaded 02/03/20. DOA 01/03/20
- Published
- 2019
8. Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs
- Author
-
Zhao, Yiren, Gao, Xitong, Guo, Xuan, Liu, Junyi, Wang, Erwei, Mullins, Robert, Cheung, Peter Y. K., Constantinides, George, and Xu, Cheng-Zhong
- Subjects
Electrical Engineering and Systems Science - Signal Processing ,Computer Science - Hardware Architecture ,Computer Science - Machine Learning - Abstract
Modern deep Convolutional Neural Networks (CNNs) are computationally demanding, yet real applications often require high throughput and low latency. To help tackle these problems, we propose Tomato, a framework designed to automate the process of generating efficient CNN accelerators. The generated design is pipelined and each convolution layer uses different arithmetics at various precisions. Using Tomato, we showcase state-of-the-art multi-precision multi-arithmetic networks, including MobileNet-V1, running on FPGAs. To our knowledge, this is the first multi-precision multi-arithmetic auto-generation framework for CNNs. In software, Tomato fine-tunes pretrained networks to use a mixture of short powers-of-2 and fixed-point weights with a minimal loss in classification accuracy. The fine-tuned parameters are combined with the templated hardware designs to automatically produce efficient inference circuits in FPGAs. We demonstrate how our approach significantly reduces model sizes and computation complexities, and permits us to pack a complete ImageNet network onto a single FPGA without accessing off-chip memories for the first time. Furthermore, we show how Tomato produces implementations of networks with various sizes running on single or multiple FPGAs. To the best of our knowledge, our automatically generated accelerators outperform closest FPGA-based competitors by at least 2-4x for lantency and throughput; the generated accelerator runs ImageNet classification at a rate of more than 3000 frames per second., Comment: To be published in International Conference on Field Programmable Technology 2019
- Published
- 2019
9. The pressure-induced structural transformation of La2S3
- Author
-
Yao, Binbin, Xu, Yongsheng, Wang, ErWei, Fan, Yinbo, and Lou, Benzhuo
- Published
- 2023
- Full Text
- View/download PDF
10. Measurement and Influencing Factors of the Second Digital Divide among University Students in Guangdong
- Author
-
Li Yumin, He Menglin, Zhang Zhen, and Wang Erwei
- Subjects
Social Sciences - Abstract
This study proposes a second digital divide measurement for university students in Guangdong, encompassing internet usage proficiency and internet-enabled learning levels. Drawing on information literacy theory, the dimensions of information awareness, acquisition, storage, retrieval, utilization, and ethical/security considerations are individually assessed. A total of 1038 valid responses were collected through a questionnaire survey, and data analysis was conducted using descriptive statistics and variance analysis. The internet usage and enabled learning levels of university students in Guangdong are found to be moderately above average. The second-level digital divide among university students in Guangdong is complex, resulting from the interactive effects of personal factors, growth environment, and university environment. Personal characteristics (gender, grade), growth environment (average living expenses, parental education, family location, growth location, family learning environment), and campus learning environment have a significant impact on both the level of internet usage and internet-enabled learning. Conversely, personal characteristics (disciplinary category), and school location exhibit no significant impact on internet-enabled learning levels.
- Published
- 2024
- Full Text
- View/download PDF
11. LUTNet: Rethinking Inference in FPGA Soft Logic
- Author
-
Wang, Erwei, Davis, James J., Cheung, Peter Y. K., and Constantinides, George A.
- Subjects
Computer Science - Machine Learning ,Statistics - Machine Learning - Abstract
Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable., Comment: Accepted manuscript uploaded 01/04/19. DOA 03/03/19
- Published
- 2019
12. Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going
- Author
-
Wang, Erwei, Davis, James J., Zhao, Ruizhe, Ng, Ho-Cheung, Niu, Xinyu, Luk, Wayne, Cheung, Peter Y. K., and Constantinides, George A.
- Subjects
Computer Science - Computer Vision and Pattern Recognition - Abstract
Deep neural networks have proven to be particularly effective in visual and audio recognition tasks. Existing models tend to be computationally expensive and memory intensive, however, and so methods for hardware-oriented approximation have become a hot topic. Research has shown that custom hardware-based neural network accelerators can surpass their general-purpose processor equivalents in terms of both throughput and energy efficiency. Application-tailored accelerators, when co-designed with approximation-based network training methods, transform large, dense and computationally expensive networks into small, sparse and hardware-efficient alternatives, increasing the feasibility of network deployment. In this article, we provide a comprehensive evaluation of approximation methods for high-performance network inference along with in-depth discussion of their effectiveness for custom hardware implementation. We also include proposals for future research based on a thorough analysis of current trends. This article represents the first survey providing detailed comparisons of custom hardware accelerators featuring approximation for both convolutional and recurrent neural networks, through which we hope to inspire exciting new developments in the field., Comment: Accepted manuscript uploaded 21/01/19. DOA 15/01/19
- Published
- 2019
- Full Text
- View/download PDF
13. Electrochemical Deposition and Etching of Quasi-Two-Dimensional Periodic Membrane Structure
- Author
-
Yao, Binbin, primary, Xu, Yongsheng, additional, Lou, Benzhuo, additional, Fan, Yinbo, additional, and Wang, Erwei, additional
- Published
- 2024
- Full Text
- View/download PDF
14. Hotel recommendation algorithms based on online reviews and probabilistic linguistic term sets
- Author
-
Cui, Chunsheng, Wei, Meng, Che, Libin, Wu, Shouwen, and Wang, Erwei
- Published
- 2022
- Full Text
- View/download PDF
15. Identification of molecular markers and candidate regions associated with grain number per spike in Pubing3228 using SLAF-BSA
- Author
-
Wang, Jiansheng, primary, Wang, Erwei, additional, Cheng, Shiping, additional, and Ma, Aichu, additional
- Published
- 2024
- Full Text
- View/download PDF
16. Advances in materials used for minimally invasive treatment of vertebral compression fractures
- Author
-
Sui, Pengfei, primary, Yu, Tong, additional, Sun, Shouye, additional, Chao, Bo, additional, Qin, Cheng, additional, Wang, Jingwei, additional, Wang, Erwei, additional, and Zheng, Changjun, additional
- Published
- 2023
- Full Text
- View/download PDF
17. Low-Voltage Distribution Network Loss-Reduction Method Based on Load-Timing Characteristics and Adjustment Capabilities.
- Author
-
Huangfu, Cheng, Wang, Erwei, Yi, Ting, and Qin, Liang
- Subjects
- *
SMART homes , *IMPACT loads , *FUZZY algorithms , *SUSTAINABLE design , *ENERGY consumption - Abstract
The primary contributors to elevated line losses in low-voltage distribution networks are three-phase load imbalances and variations in load peak–valley differentials. The conventional manual phase sequence adjustment fails to capitalize on the temporal characteristics of the load, and the proliferation of smart homes has opened up new scheduling possibilities for managing the load. Consequently, this paper introduces a loss-reduction method for low-voltage distribution networks that leverages load-timing characteristics and adjustment capabilities. This method combines dynamic and static methods to reduce energy consumption from different time scales. To commence, this paper introduced a hierarchical fuzzy C-means algorithm (H-FCM), taking into account the distance and similarity of load curves. Subsequently, a phase sequence adjustment method, grounded in load-timing characteristics, was developed. The typical user load curve, derived from the classification of user loads, serves as the foundation for constructing a long-term commutation model, therefore mitigating the impact of load fluctuations on artificial commutation. Following this, this paper addressed the interruptible and transferable characteristics of various smart homes. This paper proposed a multi-objective transferable load (TL) optimal timing task adjustment model and a peak-shaving control strategy specifically designed for maximum sustainable power reduction of temperature-controlled loads (TCL). These strategies aim to achieve real-time load adjustment, correct static commutation errors, and reduce peak-to-valley differences. Finally, a simulation verification model was established in MATLAB (R2022a). The results show that the proposed method mainly solves the problems of three-phase imbalance and large load peak–valley difference in low-voltage distribution networks and reduces the line loss of low-voltage distribution networks through manual commutation and load adjustment. [ABSTRACT FROM AUTHOR]
- Published
- 2024
- Full Text
- View/download PDF
18. Research on a Hotel Collaborative Filtering Recommendation Algorithm Based on the Probabilistic Language Term Set
- Author
-
Wang, Erwei, primary, Chen, Yingyin, additional, and Li, Yumin, additional
- Published
- 2023
- Full Text
- View/download PDF
19. Nonideality‐Aware Training for Accurate and Robust Low‐Power Memristive Neural Networks
- Author
-
Joksas, Dovydas, primary, Wang, Erwei, additional, Barmpatsalos, Nikolaos, additional, Ng, Wing H., additional, Kenyon, Anthony J., additional, Constantinides, George A., additional, and Mehonic, Adnan, additional
- Published
- 2022
- Full Text
- View/download PDF
20. Research on High Quality Development Evaluation of Pearl River Delta Urban Agglomeration
- Author
-
Wang Erwei and Liao Aihong
- Subjects
Pearl river delta ,Urban agglomeration ,Environmental science ,Water resource management ,Quality development - Published
- 2021
21. Research on the Construction of Local Government Think Tank System Based on Bidding Data Analysis
- Author
-
Wang Erwei and Chen Yingyin
- Subjects
Finance ,business.industry ,Local government ,Business ,Bidding - Published
- 2021
22. Research on Measurement and Influence Factors of Total Factor Productivity in Zhuhai
- Author
-
Qi Yanxin, Liao Aihong, and Wang Erwei
- Subjects
Toxicology ,Environmental science ,Total factor productivity - Published
- 2021
23. Differentiated Impact of Politics- and Science-Oriented Education on Pro-Environmental Behavior: A Case Study of Chinese University Students
- Author
-
Wang, Ran, primary, Jia, Tiantian, additional, Qi, Rui, additional, Cheng, Jinhua, additional, Zhang, Kang, additional, Wang, Erwei, additional, and Wang, Xi, additional
- Published
- 2021
- Full Text
- View/download PDF
24. LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference
- Author
-
Wang, Erwei, primary, Davis, James J., additional, Cheung, Peter Y. K., additional, and Constantinides, George A., additional
- Published
- 2020
- Full Text
- View/download PDF
25. Effects of thickness on switching current for (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O 3 antiferroelectric films under thermo‐electric coupled field
- Author
-
Xiujian Chou, An Kun, Wang Erwei, Chenyang Xue, Jian He, and Wendong Zhang
- Subjects
010302 applied physics ,Materials science ,Field (physics) ,Biomedical Engineering ,Bioengineering ,Lanthanum compounds ,02 engineering and technology ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,01 natural sciences ,Homogeneous ,0103 physical sciences ,Thermoelectric effect ,Ferroelectric thin films ,Antiferroelectricity ,General Materials Science ,Current (fluid) ,Composite material ,0210 nano-technology ,Current density - Abstract
Homogeneous and compact antiferroelectric (AFE) (Pb, La)(Zr, Ti)O3 thick films in large area with different thicknesses were successfully fabricated by the sol–gel processing on Pt(111)/Ti/SiO2/Si(100) substrates. The characteristics of switching current of samples with different thicknesses under thermo-electric coupled field were investigated in detail. The experimental result shows that the peak of switching current density increased with the increase of temperature in three samples. Moreover, it is found that the thickness of the films has a big effect on the current density. Therefore, the peak of switching current density increased with increasing in the thickness at the same temperatures. The maximum switching current density of film with the thickness of 2254 nm is 4.35 × 10−5A/cm2. These results are quite important and necessary for design and preparation of the AFE materials applied on high sensitivity and intelligent micro-sensors and micro-actuators.
- Published
- 2016
26. Deep Neural Network Approximation for Custom Hardware
- Author
-
Wang, Erwei, primary, Davis, James J., additional, Zhao, Ruizhe, additional, Ng, Ho-Cheung, additional, Niu, Xinyu, additional, Luk, Wayne, additional, Cheung, Peter Y. K., additional, and Constantinides, George A., additional
- Published
- 2019
- Full Text
- View/download PDF
27. Deep Neural Network Approximation for Custom Hardware: Where We’ve Been,Where We’re Going.
- Author
-
WANG, ERWEI, DAVIS, JAMES J., ZHAO, RUIZHE, NG, HO-CHEUNG, NIU, XINYU, LUK, WAYNE, CHEUNG, PETER Y. K., and CONSTANTINIDES, GEORGE A.
- Abstract
Deep neural networks have proven to be particularly effective in visual and audio recognition tasks. Existing models tend to be computationally expensive and memory intensive, however, and so methods for hardware-oriented approximation have become a hot topic. Research has shown that custom hardware-based neural network accelerators can surpass their general-purpose processor equivalents in terms of both throughput and energy efficiency. Application-tailored accelerators, when co-designed with approximation-based network training methods, transform large, dense, and computationally expensive networks into small, sparse, and hardware-efficient alternatives, increasing the feasibility of network deployment. In this article, we provide a comprehensive evaluation of approximation methods for high-performance network inference along with in-depth discussion of their effectiveness for custom hardware implementation. We also include proposals for future research based on a thorough analysis of current trends. This article represents the first survey providing detailed comparisons of custom hardware accelerators featuring approximation for both convolutional and recurrent neural networks, through which we hope to inspire exciting new developments in the field. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
28. Effects of thickness on switching current for (Pb 0.97 La 0.02 )(Zr 0.95 Ti 0.05 )O 3 antiferroelectric films under thermo‐electric coupled field
- Author
-
An, Kun, primary, Wang, Erwei, additional, He, Jian, additional, Chou, Xiujian, additional, Xue, Chenyang, additional, and Zhang, Wendong, additional
- Published
- 2016
- Full Text
- View/download PDF
Catalog
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.