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Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a 50µm of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

Through Silicon Via (TSV) technology is the shortest interconnection technology which is compared with conventional wire bonding interconnection technology. Recently, this technology has been also noticed for the miniaturization of electronic devices, multi-functional and high performance. The short interconnection length of TSV achieve can implement a high density and power efficiency. Among the TSV technology, TSV filling process is important technology because the cost of TSV technology is depended on the filling process time and reliability. Various filling methods have been developed like as Cu electroplating method, molten solder insert method and Ti/W deposition method. In this paper, various TSV filling methods were introduced and each filling materials were discussed.

Carbon nanotubes (CNTs) that incorporated Sn–3.5Ag solder balls were fabricated by a surface impact mixing (SIM) process. The SIM process consisted of a ball milling process that provided enough impact energy for CNT embedding on the solder surface and at the same time, maintained the size and shape of the solder balls. As the SIM time increased, the density of the embedded CNTs on the solder surface increased and the entire solder surface was covered with CNTs after 24 h of the SIM process. The shear strength of the CNT-embedded Sn-3.5Ag solder balls increased by 10% after the 24 h-SIM process. The thickness of the intermetallic compound (IMC) layer between the solder and Ni decreased when CNTs were included in the Sn–3.5Ag solder. As aging time increased, the IMC thickness difference between CNT-embedded and non-CNT samples remarkably increased as well.

따라서 빠른 충진 시간을 갖는 충진 기술이 필요하며 빠른 충진 시간은 곧 생산성 증가로 연결되어 공정 비용을 낮추는 효과가 있다. 본 연구의 용융 솔더 충진 방법은 수초 이내의 짧은 시간내에 결함 없는 비아 충진이 가능한 방법이다. 웨이퍼 양단의 압력차를 이용하여 용융 솔더를 충진하는 방법으로 TSV 직경의 변화가 있더라도 압력만을 제어하여 빠른 충진이 가능하다는 장점을 가지고 있다. 또한 본 연구의 또 다른 이슈로 낮은 열팽창계수를 가지는 충진소재를 연구하였다. 기존의 TSV내에 충진된 Cu는 Si과의 열팽창계수 차이에 따라 Cu와 Si 간의 계면에 높은 Stress가 발생하게 된다. 이러한 Stress는 Cu의 Pop-up현상 및 Crack, Void 발생 등의 문제와 Si내의 Stress는 device의 성능저하를 일으키는 원인이 된다

이러한 장점은 지금까지 개발되어 온 3D 적층기술 중에서 TSV가 차세대 전자산업의 다양한 요구를 충족할 수 있는 기술로 부각되는 이유이다. 그러나 TSV의 높은 종횡비와 초미세 직경 등 구조적인 문제로 도전성 물질의 충진에는 높은 제조 공정비용이 소요되고 이는 상업화에 대한 가장 큰 저해 요소이다. TSV의 제조공정은 비아(via)형성, 절연층 및 확산방지층 형성, 비아 충진(via filling), 칩 접합(bonding)으로 나눌 수 있는데 각 세부공정 중 비아 충진 공정은 전체 TSV 제조 공정 중 약 40%이상의 가장 높은 비용을 차지하고 있다

SiC-mixed Sn–58Bi composite solder bumps were successfully fabricated via an electroplating process. For the composite solder bump fabrication, ultrasonically dispersed SiC nanoparticles were added to the plating solutions. DSC analysis indicated that the melting temperature of SiC-mixed Sn–58Bi solders was the same as that of the non-mixed Sn–58Bi. Shear strengths of Sn–58Bi+SiC solder bumps were 6% higher than that of non-mixed solder bumps. The thicknesses of intermetallic compound were almost the same for both Sn–58Bi and Sn–58Bi+SiC samples. The Sn–58Bi+SiC composite solder bumps had finer lamellar structures than non-mixed Sn–58Bi. From the fracture surface analysis, fracture occurred at solder bump matrix, not at joint interface. Therefore, the addition of the SiC nanoparticles in the Sn–58Bi solders decreased the grain sizes, which increased the shear strengths.

The motion estimator employs a pair of processing cores that calculate the motion vector concurrently. By controlling the data flow in a systolic fashion using internal shift registers of the processing cores, the local memory (SRAM) is discarded to reduce the time overhead for accessing the local memory and utilise lower-cost fabrication tcchnology.