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Device architectures and dimensions are now at an unimaginable level not thought possible even 10 years ago. The continued downscaling, following the so-called Moore's law, has motivated the development and use of extreme ultraviolet (EUV) lithography scanners with specialized photoresists. Since the quality and precision of the transferred circuit pattern is determined by the EUV induced chemical changes in the photoresist, having a deep understanding of these chemical changes is of pivotal importance. For this purpose, several spectroscopic and material characterization techniques have already been employed so far. Among them, photoemission can be essential as it not only allows direct probing of chemical bonds in a quantitative way but also provides useful information regarding the generation and distribution of primary and secondary electrons. However, since high energy photons are being employed for characterization of a photosensitive material, modification of the sample during the measurement is possible and this must be considered when investigating the chemical changes in the photoresist before and after exposure to EUV light.

Two-dimensional transition metal dichalcogenides (TMDs) for advanced logic transistor technologies are deposited by various modifications of the chemical vapor deposition (CVD) method using a wide variety of precursors. Being a major electrical performance limiter, the TMD crystal grain size strongly differs between the various CVD precursor chemistries from nano- to millimeter-sized crystals. However, it remains unclear how the CVD precursor chemistry affects the nucleation density and resulting TMD crystal grain size. This work postulates guiding principles to design a CVD process for highly crystalline TMD deposition using a quantitative analytical model benchmarked against literature. The TMD nucleation density reduces favorably under low supersaturation conditions, where the metal precursor sorption on the starting surface is reversible and the corresponding metal precursor desorption rate exceeds the overall deposition rate. Such reversible precursor adsorption guarantees efficient long-range gas-phase lateral diffusion of precursor species in addition to short-range surface diffusion, which vitally increases crystal grain size. As such, the proposed model explains the large spread in experimentally observed TMD nucleation densities and crystal grain sizes for state-of-the-art CVD chemistries. Ultimately, it empowers the reader to interpret and modulate precursor adsorption and diffusion reactions through designing CVD precursor chemistries compatible with temperature sensitive application schemes.

As semiconductor patterning dimensions shrink, more advanced Scanning Electron Microscopy (SEM) image-based defect inspection techniques are needed. Recently, many Machine Learning (ML)-based approaches have been proposed for defect localization and have shown impressive results. These methods often rely on feature extraction from a full SEM image and possibly a number of regions of interest. In this study, we propose a deep Reinforcement Learning (RL)-based approach to defect localization which iteratively extracts features from increasingly smaller regions of the input image. We compare the results of 18 agents trained with different feature extractors. We discuss the advantages and disadvantages of different feature extractors as well as the RL-based framework in general for semiconductor defect localization., Comment: 5 pages, 5 figures, 3 tables

A growing need exists for efficient and accurate methods for detecting defects in semiconductor materials and devices. These defects can have a detrimental impact on the efficiency of the manufacturing process, because they cause critical failures and wafer-yield limitations. As nodes and patterns get smaller, even high-resolution imaging techniques such as Scanning Electron Microscopy (SEM) produce noisy images due to operating close to sensitivity levels and due to varying physical properties of different underlayers or resist materials. This inherent noise is one of the main challenges for defect inspection. One promising approach is the use of machine learning algorithms, which can be trained to accurately classify and locate defects in semiconductor samples. Recently, convolutional neural networks have proved to be particularly useful in this regard. This systematic review provides a comprehensive overview of the state of automated semiconductor defect inspection on SEM images, including the most recent innovations and developments. 38 publications were selected on this topic, indexed in IEEE Xplore and SPIE databases. For each of these, the application, methodology, dataset, results, limitations and future work were summarized. A comprehensive overview and analysis of their methods is provided. Finally, promising avenues for future work in the field of SEM-based defect inspection are suggested., Comment: 16 pages, 12 figures, 3 tables

Continual shrinking of pattern dimensions in the semiconductor domain is making it increasingly difficult to inspect defects due to factors such as the presence of stochastic noise and the dynamic behavior of defect patterns and types. Conventional rule-based methods and non-parametric supervised machine learning algorithms like KNN mostly fail at the requirements of semiconductor defect inspection at these advanced nodes. Deep Learning (DL)-based methods have gained popularity in the semiconductor defect inspection domain because they have been proven robust towards these challenging scenarios. In this research work, we have presented an automated DL-based approach for efficient localization and classification of defects in SEM images. We have proposed SEMI-CenterNet (SEMI-CN), a customized CN architecture trained on SEM images of semiconductor wafer defects. The use of the proposed CN approach allows improved computational efficiency compared to previously studied DL models. SEMI-CN gets trained to output the center, class, size, and offset of a defect instance. This is different from the approach of most object detection models that use anchors for bounding box prediction. Previous methods predict redundant bounding boxes, most of which are discarded in postprocessing. CN mitigates this by only predicting boxes for likely defect center points. We train SEMI-CN on two datasets and benchmark two ResNet backbones for the framework. Initially, ResNet models pretrained on the COCO dataset undergo training using two datasets separately. Primarily, SEMI-CN shows significant improvement in inference time against previous research works. Finally, transfer learning (using weights of custom SEM dataset) is applied from ADI dataset to AEI dataset and vice-versa, which reduces the required training time for both backbones to reach the best mAP against conventional training method.

Shrinking pattern dimensions leads to an increased variety of defect types in semiconductor devices. This has spurred innovation in patterning approaches such as Directed self-assembly (DSA) for which no traditional, automatic defect inspection software exists. Machine Learning-based SEM image analysis has become an increasingly popular research topic for defect inspection with supervised ML models often showing the best performance. However, little research has been done on obtaining a dataset with high-quality labels for these supervised models. In this work, we propose a method for obtaining coherent and complete labels for a dataset of hexagonal contact hole DSA patterns while requiring minimal quality control effort from a DSA expert. We show that YOLOv8, a state-of-the-art neural network, achieves defect detection precisions of more than 0.9 mAP on our final dataset which best reflects DSA expert defect labeling expectations. We discuss the strengths and limitations of our proposed labeling approach and suggest directions for future work in data-centric ML-based defect inspection., Comment: 8 pages, 10 figures, accepted for the 38th EMLC Conference 2023

Innovative Electronic Design Automation (EDA) solutions are important to meet the design requirements for increasingly complex electronic devices. Verilog, a hardware description language, is widely used for the design and verification of digital circuits and is synthesized using specific EDA tools. However, writing code is a repetitive and time-intensive task. This paper proposes, primarily, a novel deep learning framework for training a Verilog autocompletion model and, secondarily, a Verilog dataset of files and snippets obtained from open-source repositories. The framework involves integrating models pretrained on general programming language data and finetuning them on a dataset curated to be similar to a target downstream task. This is validated by comparing different pretrained models trained on different subsets of the proposed Verilog dataset using multiple evaluation metrics. These experiments demonstrate that the proposed framework achieves better BLEU, ROUGE-L, and chrF scores by 9.5%, 6.7%, and 6.9%, respectively, compared to a model trained from scratch. Code and data are made available at: https://github.com/99EnriqueD/verilog_autocompletion ., Comment: Updated text to correct language errors and added a link to supplementary code and data (https://github.com/99EnriqueD/verilog_autocompletion). 6 pages, 3 figures, 4 tables. To be presented as a WIP poster at DAC 2023

We have studied the effect of chemical-mechanical polishing (CMP) on the ferroelectric, piezoelectric, and microwave dielectric properties of Ba-substituted PZT (BPZT), deposited by pulsed laser deposition. CMP allowed for the reduction of the root mean square surface roughness of 600 nm thick BPZT films from 12.1nm to 0.79 nm. Ammonium peroxide (SC-1) cleaning was effective to remove Si CMP residuals. Measurements of the ferroelectric hysteresis after CMP indicated that the ferroelectric properties of BPZT were only weakly affected by CMP, while the piezoelectric d33 coefficient and the microwave permittivity were reduced slightly by 10%. This can be attributed to the formation of a thin dead layer at the BPZT surface. Moreover, the intrinsic dielectric permittivity at microwave frequencies between 1 and 25 GHz was not influenced by CMP, whereas the dead layer series capacitance decreased by 10%. The results indicate that the CMP process can be used to smoothen the BPZT surface without affecting the film properties strongly., Comment: 13 pages of text, 4 tables and 7 figures. This project has received funding from the European Union's Horizon 2020 research and innovation program under grant agreement No. 801055 "Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics" - CHIRON

The field of object detection using Deep Learning (DL) is constantly evolving with many new techniques and models being proposed. YOLOv7 is a state-of-the-art object detector based on the YOLO family of models which have become popular for industrial applications. One such possible application domain can be semiconductor defect inspection. The performance of any machine learning model depends on its hyperparameters. Furthermore, combining predictions of one or more models in different ways can also affect performance. In this research, we experiment with YOLOv7, a recently proposed, state-of-the-art object detector, by training and evaluating models with different hyperparameters to investigate which ones improve performance in terms of detection precision for semiconductor line space pattern defects. The base YOLOv7 model with default hyperparameters and Non Maximum Suppression (NMS) prediction combining outperforms all RetinaNet models from previous work in terms of mean Average Precision (mAP). We find that vertically flipping images randomly during training yields a 3% improvement in the mean AP of all defect classes. Other hyperparameter values improved AP only for certain classes compared to the default model. Combining models that achieve the best AP for different defect classes was found to be an effective ensembling strategy. Combining predictions from ensembles using Weighted Box Fusion (WBF) prediction gave the best performance. The best ensemble with WBF improved on the mAP of the default model by 10%., Comment: 8 pages, 4 figures, 5 tables. To be published by SPIE in the proceedings of Metrology, Inspection, and Process Control XXXVII

The application of new materials in nanotechnology opens new perspectives and enables ground-breaking innovations. Two-dimensional van der Waals materials and more specific, 2D chalcogenides are a promising class of new materials awaiting their usage in the semiconductor industry. However, the integration of van der Waals materials relying on industry-compatible manufacturing processes is still a major challenge. This is currently restricting the application of these new materials to the research laboratories environment only. The large-area and single-crystalline growth of van der Waals materials is one of the most important requirements to meet the challenging demands implied by the semiconductor industry. This review contributes to a more generalized understanding on the integration of van der Waals materials - and in more specific 2D chalcogenides - through the growth process of epitaxy. This, can pursue further the aspiration of large-area, single-crystalline and defect-free epitaxial integration of (quasi) van der Waals homo- and heterostructures into the great world of the semiconductor industry.

Defect-free epitaxial growth of 2D materials is one of the holy grails for a successful integration of van der Waals (vdW) materials in the semiconductor industry. The large-area (quasi-)vdW epitaxy of layered 2D chalcogenides is consequently carefully being researched since these materials hold very promising properties for future nanoelectronic applications. The formation of defects such as stacking faults like 60o twins and consequently 60o grain boundaries is still of major concern for the defect-free epitaxial growth of 2D chalcogenides. Although growth strategies to overcome the occurrence of these defects are currently being considered, more fundamental understanding on the origin of these defects at the initial stages of the growth is highly essential. Therefore this work focuses on the understanding of 60o twin formation in (quasi-)vdW epitaxy of 2D chalcogenides relying on systematic molecular beam epitaxy (MBE) experiments supported by density functional theory (DFT) calculations. The MBE experiments reveal the striking difference in 60o twin formation between WSe2 and Bi2Se3 in both quasi-vdW heteroepitaxy and vdW homoepitaxy, which from our DFT calculations links to the difference in interlayer vdW coupling strength. The stronger interlayer vdW coupling in Bi2Se3 compared to WSe2 results in a striking enhanced control on twin formation and hence shows significantly more promise for defect-free epitaxial integration. This interesting aspect of (quasi-)vdW epitaxy reveals that the strength of interlayer vdW coupling is key for functional 2D materials and opens perspectives for other vdW materials sharing strong interlayer interactions.