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In this article, a nine-level multilevel topology is proposed by stacking of low voltage basic inverter cells and then cascading with H-bridges. The dc-link is split into four equal halves by series-connected capacitors from a common dc-link. Three common coupling points (CCPs) are formed due to the stacking of four capacitors, which are connected across the dc-link. The CCP voltage balancing is ensured by drawing or injecting zero instantaneous currents from each of these points at any instant. A six-phase symmetrical IM is used to generate equal and opposite instantaneous phase currents by applying exactly equal and opposite phase voltages for two opposite phases from the six-phase inverter. Simultaneously, the capacitor voltage balancing of H-bridge inverter cells is also achieved by proper selection of redundancies from the available pole voltage redundancies. The concept is verified with a nine-level inverter laboratory prototype, which consists of a five-level stacked inverter, and followed by two low voltage cascaded H-bridge inverters in each phase. Detailed experimental results of steady-state and transient conditions are included to validate the proposed scheme. [ABSTRACT FROM AUTHOR]

In this work, a ten-level inverter scheme is presented to extend the linear modulation range (LMR) by using a unique space vector pulsewidth modulation (SVPWM) technique, such that no lower order harmonics (such as 5th, 7th, 11th, and 13th, etc.) are present in the phase voltage as compared to six-step mode operation. The proposed scheme can increase the peak phase fundamental voltage of the inverter from 0.577 to $0.637 V_{dc}$ (maximum possible peak phase fundamental voltage of a conventional hexagonal space vector structure (SVS) voltage source inverters while operating in six-step mode), irrespective of the load power factor (p.f), where $V_{dc}$ is the dc link voltage of the inverter. The ten-level inverter structure is formed using a two-level inverter and an H-bridge (HB) in cascade from one end and a floating capacitor-based two-level inverter cascaded with an HB from the other end to drive an open-end winding induction motor (OEWIM). All the HB capacitor voltages are balanced by using space vector redundancy. The claim of balancing the capacitor voltages throughout the whole modulation range is verified experimentally in this article. Experimental results at different steady-state and transient conditions are shown to validate the proposed inverter scheme’s efficacy in increasing the LMR. [ABSTRACT FROM AUTHOR]

This article proposes a method of generating 24-sided polygonal voltage space vector structure composed of 24 real active vectors and a zero vector. Each active vector is a real vector in contrast to switched average vectors in literature. Generation of real 24-sided vectors minimizes switching losses and improves quality of phase voltage compared to switched averaged vectors technique. An important feature of the presented scheme is elimination of lower order harmonics up to 19th order from motor phase voltage throughout the modulation range that gives reduction in torque pulsation and near sinusoidal phase current. The proposed scheme extends the linear modulation range till 99.42 $\%$. Open-end winding induction motor is fed with primary and secondary inverters from either ends. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both the inverters are realized using a simple star-delta transformer combination. The proposed concepts are verified with laboratory prototype and the respective results during the steady-state, transient, and fault scenario are presented. The supporting loss analysis and harmonic performance of the proposed drive is performed with existing topologies. [ABSTRACT FROM AUTHOR]

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/f” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented. [ABSTRACT FROM AUTHOR]

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation. [ABSTRACT FROM AUTHOR]

A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected H-bridges. The H-bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five- or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the H -bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region. [ABSTRACT FROM PUBLISHER]

A voltage source inverter generating a polygonal voltage space vector structure (SVS) having 117- concentric 30-sided polygons of different radii are proposed. Modulation using a 30-sided SVS eliminates lower order harmonics till 25th order from motor phase voltage. The proposed scheme combines the advantages of a 30-sided SVS with that of a multilevel inverter. The topology consists of two cascaded five-level inverters feeding from either end of the open-end induction motor stator windings. One of the cascaded five-level inverter is connected to an active dc source and delivers the required active power for the scheme, while the other is capacitor fed and acts as a switched capacitive filter. In this article, nonaligned 30-sided polygons, i.e., regular 30-sided polygons that are not symmetric with respect to $\alpha$ and $\beta$ axis are also considered for inverter operation. The harmonic analysis of such nonaligned 30-sided polygons is investigated in this article. Nearest level switching is employed throughout the modulation range, enabling further reduction of switching loss in the system. Extensive hardware experimentations are carried out to validate the proposed scheme and the results are included in the article. [ABSTRACT FROM AUTHOR]

Multilevel converters have been under research and development for more than three decades and have found successful industrial application. However, this is still a technology under development, and many new contributions and new commercial topologies have been reported in the last few years. The aim of this paper is to group and review these recent contributions, in order to establish the current state of the art and trends of the technology, to provide readers with a comprehensive and insightful review of where multilevel converter technology stands and is heading. This paper first presents a brief overview of well-established multilevel converters strongly oriented to their current state in industrial applications to then center the discussion on the new converters that have made their way into the industry. In addition, new promising topologies are discussed. Recent advances made in modulation and control of multilevel converters are also addressed. A great part of this paper is devoted to show nontraditional applications powered by multilevel converters and how multilevel converters are becoming an enabling technology in many industrial sectors. Finally, some future trends and challenges in the further development of this technology are discussed to motivate future contributions that address open problems and explore new possibilities. [ABSTRACT FROM AUTHOR]

The open-loop control scheme presented in part I of this paper for a dual five-level-inverter-fed induction motor (IM) drive with two dc power supplies maintains dc-link capacitor voltage balancing and common-mode voltage (CMV) elimination throughout the operating range of the drive. The operating limitation of the proposed open-loop control scheme to take corrective action toward the existing unbalance in the dc-link-capacitor voltages is also pointed out in part I of this paper. As a solution to this, a simple closed-loop control scheme, which is based only on the switching-state redundancy, is proposed in this part of the paper. The proposed closed-loop control scheme not only prevents further unbalancing of capacitor voltages but also takes corrective actions to bring back the capacitor voltages in the balanced state. The proposed closed-loop scheme achieves dc-link capacitor voltage balancing and elimination of CMV together in the complete modulation range, including overmodulation of up to the 24-step operation. The proposed control scheme does not affect the output fundamental voltage generated by the inverter, as it effectively utilizes only the availability of redundant switching states of the inverter, and does not call for additional power circuit hardware. The scheme is presented with the simulation studies and experimentally verified with a 1.5-kW open-end winding IM drive. [ABSTRACT FROM AUTHOR]

A current error space phasor based simple hysteresis controller is proposed in this paper to control the switching frequency variation in two-level pulsewidth-modulation (PWM) inverter-fed induction motor (IM) drives. A parabolic boundary for the current error space phasor is suggested for the first time to obtain the switching frequency spectrum for output voltage with hysteresis controller similar to the constant switching frequency voltage-controlled space vector PWM-based IM drive. A novel concept of online variation of this parabolic boundary, which depends on the operating speed of motor, is presented. A generalized technique that determines the set of unique parabolic boundaries for a two-level inverter feeding any given induction motor is described. The sector change logic is self-adaptive and is capable of taking the drive up to the six-step mode if needed. Steady-state and transient performance of proposed controller is experimentally verified on a 3.7-kW IM drive in the entire speed range. Close resemblance of the simulation and experimental results is shown. [ABSTRACT FROM AUTHOR]

For a dual five-level inverter-fed induction motor (IM) drive, effects of dc-neutral currents on dc-link capacitor voltage fluctuations are analyzed in this paper. Operating limitations in achieving the dual task of common-mode voltage elimination and dc-link capacitor voltage balancing with a single dc power supply are further investigated for the proposed drive. In this paper, an open-loop control scheme, which uses only the availability of redundant switching states for the inverter control, is presented. Limitation of proposed open-loop control to take corrective action for any existing unbalance in capacitor voltages calls for a closed-loop control scheme, which is presented in Part II of this paper. [ABSTRACT FROM AUTHOR]

A dc link capacitor voltage balancing scheme along with common mode voltage elimination is proposed for an induction motor drive, with open-end winding structure. The motor is fed from both the ends with three-level inverters generating a five level output voltage space phasor structure. If switching combinations, with zero common mode voltage in the pole voltage, are used, then the resultant voltage space vector combinations are equivalent to that of a three-level inverter. The proposed inverter vector locations exhibit greater multiplicity in the inverter switching combinations which is suitably exploited to arrive at a capacitor voltage balancing scheme. This allows the use of a single dc link power supply for the combined inverter structure. The simultaneous task of common mode voltage elimination with dc link capacitor voltage balancing, using only the switching state redundancies, is experimentally verified on a 1.5-kW induction motor drive. [ABSTRACT FROM AUTHOR]

The simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance is achieved in a five-level inverter scheme for an induction motor drive throughout its operating range. A dual five-level inverter-fed open-end-winding induction motor structure is used for the proposed drive. Initially, the operating limitations of achieving this dual task for the five-level inverter configuration are investigated for a single DC power supply. Subsequently, a switching strategy for a five-level inverter topology with two DC power supplies is proposed to achieve the dual task over the entire speed range of the drive. The proposed drive offers a simple power-bus structure with more redundant switching combinations for inverter voltage vectors, and requires a lower voltage-blocking capacity of the power devices as compared with the conventional single five-level inverter-fed drive. As only the availability of redundant switching combinations for inverter voltage vectors is exploited, the dual task is achieved without disturbing the fundamental component of the inverter output voltage and the scheme does not need any extra control circuit hardware. Experimental verification of the proposed scheme is done on a 1.5 kW induction motor drive in the linear as well as overmodulation range. [ABSTRACT FROM AUTHOR]

A current-error space-vector-based PWM hysteresis controller is proposed for three-level voltage source inverter fed induction motor drive applications. A hexagonal boundary for the current-error space vector is formed by sensing the current-error space vector along three different axes, which are 120:) apart and are orthogonal to machine phase axes. Only the adjacent inverter voltage vectors forming a triangular sector, in which tip of the machine voltage vector lies, are switched to keep the current-error space vector within the hexagonal boundary. Selection amongst the three nearest voltage vectors is done by a simple region detection logic in all the sectors. Calculation of the machine voltage vector is not needed and information of the same is indirectly derived from the direction of current-error space vector. The controller uses a self-adaptive sector identification logic, which provides smooth transition between sectors (voltage levels), including over modulation region up to 12-step mode of operation. Inherent advantages of current hysteresis controller are retained with the added advantage of adjacent voltage vector selection for hysteresis PWM control. Simple look-up tables are only needed for sector and vector selection, based on the hysteresis controller output, for the proposed hysteresis PWM controller. Experimental verification is provided by implementing the proposed controller on a 1.5 kW open-end winding induction motor drive. The proposed controller can be extended for further levels of multi-level inverters for high-performance drives by constructing suitable look-up tables. [ABSTRACT FROM AUTHOR]

A dual two-level inverter fed open-end winding induction motor drive with a single DCpower supply is proposed. The proposed scheme produces voltage space vector locations identical to those of a conventional three-level inverter. In the conventional neutral-clamped three-level inverter, the series-connected DC link capacitors carry the load current, resulting in a fluctuating neutral point. Also, a three-level inverter requires bulky DC link capacitors. In the proposed scheme, the DC link capacitors carry currents of higher frequency and hence the neutral point fluctuations are reduced. A PWM switching strategy to suppress the zero sequence currents for all the voltage space phasor combinations is also proposed. This strategy is an improvisation of the one that uses a switched neutral to eliminate the triplen harmonic currents and results in an improved DC bus utilisation. [ABSTRACT FROM AUTHOR]

This article introduces a hybrid nine-level inverter topology with extended dc-bus utilization for operation at over modulation range without the presence of lower order harmonics (predominantly fifth and seventh) when compared to conventional two-level and multilevel inverter with hexagonal voltage space vector structure. The proposed inverter is a cascade of a five-level T-type unit and an H-bridge (HB) unit. An increase in the dc-bus utilization is possible by increasing the pole voltage levels to ± (Vdc/2 + Vdc/8) using the HB capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned pulsewidth modulation strategy allows us to increase the peak phase fundamental voltage from 0.577Vdc to 0.625Vdc in case of unity power factor (p.f) load and to 0.637Vdc for 0.82 p.f load with the proposed nine-level inverter. The limiting factor on increasing the dc bus utilization such as p.f, HB capacitor balancing are analysed broadly in this article. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype. [ABSTRACT FROM AUTHOR]

In this article, a method is proposed for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor drive. A five-level inverter with a single dc source is used for the proposed scheme. Using this method, linear pulsewidth modulation (PWM) operation of the inverter can be achieved till peak phase fundamental voltage of 0.637 Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed five-level inverter scheme is realized by cascading a two-level inverter with a capacitor fed H-bridge, feeding open-end induction motor drive from one end and a capacitor fed two-level inverter from the other end. The proposed scheme uses space vector redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal five-level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme [ABSTRACT FROM AUTHOR]

This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

A multilevel dodecagonal voltage space vector generation scheme for variable-speed drive applications with single-dc-link operation requires a large value of capacitance for cascaded H-bridge (CHB) filters, when operated at lower speeds. In existing schemes, the multilevel dodecagonal structure is obtained by cascading a flying capacitor inverter with a CHB. In this paper, a new scheme has been proposed to minimize the capacitance requirement for full speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimize the selection of vector redundancies among the CHBs in order to minimize the voltage ripple of the floating capacitors. The proposed algorithm considers instantaneous capacitor voltages and phase currents for optimal selection of vector redundancies. A mathematical model for capacitor voltage deviation is presented, and the effectiveness of the proposed algorithm is verified in both the simulation and the experiment. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a novel harmonic suppression scheme for two-level inverter fed three-terminal induction motor drives using switched capacitive filter. Capacitor fed H-bridges used as filters are cascaded to conventional two-level inverter to eliminate fifth- and seventh-order harmonics for the full modulation range including a six-step operation. For the first time, two-level dodecagonal voltage space vector is implemented with single dc supply for three-terminal induction motor drive. Enabling the switched capacitive filtering at low-voltage domain and shifting the high frequency switching to the switched capacitive filter is shown. A uniform pulse width modulation technique is shown which charges and maintains the capacitor voltages while eliminating the fifth- and seventh-order harmonics for the full speed range. [ABSTRACT FROM AUTHOR]

This paper presents a method for generating a multilevel dodecagonal voltage space vector structure using a single dc source for induction motor drives. Multilevel dodecagonal structure combines the advantages of both multilevel and dodecagonal structures, and hence, generates low dv/dt phase voltage along with the elimination of fifth- and seventh-order harmonics over the entire modulation range. This eliminates low-order harmonic currents and prevents the generation of sixth-order torque ripple in the motor. The topology used requires only one dc source making four-quadrant operation of the drive system simpler compared to previously proposed multilevel topologies generating dodecagonal space vector structures. The topology used consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge. The FC inverter operates at a lower switching frequency and the low-order harmonics are eliminated by the switching action of the cascaded H-bridge inverter. The capacitors in the cascaded H-bridge modules are maintained at a substantially smaller voltage compared to the dc-link voltage and are inherently balanced during the pulsewidth modulation operation. This results in low switching loss, in the FC inverter as well as in the cascaded H-bridge inverter. Experimental results are included to validate the operation of the topology and modulation scheme presented in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a new method of generating higher number of levels in the voltage waveform by stacking multilevel converters with lower voltage space vector structures. An important feature of this stacked structure is the use of low voltage devices while attaining higher number of levels. This will find extensive applications in electric vehicles since direct battery drive is possible. The voltages of all the capacitors in the structure can be controlled within a switching cycle using the switching state redundancies (pole voltage redundancies). This helps in reducing the capacitor size. Also, the capacitor voltages can be balanced irrespective of modulation index and load power factor. To verify the concept experimentally, a nine-level inverter is developed by stacking two five-level inverters and an induction motor is run using V/f control scheme. Both steady state and transient results are presented. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n \pm 1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM. [ABSTRACT FROM PUBLISHER]

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc. [ABSTRACT FROM AUTHOR]

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. [ABSTRACT FROM AUTHOR]

• Modified approach for repetitive control based on comb filters. • Introduced multiple normalization factors. • Multiple current harmonics compensation with simple design and implementation. • Stability of the main control loop is unaffected. • Introduced FIR filter for robustness improvement Power quality plays an important role in the operation of grid-connected inverters. The injected current should have a minimum harmonic content in order to comply with the local grid codes. This can be challenging due to the fact that the grid voltage can also be distorted. This paper presents the modified repetitive control method for three-phase grid-connected inverters by means of a digital comb filter application. The proposed method provides multiple harmonics compensation, simple implementation and design. It consists in complementing the Proportional-Resonant (PR) control with an appropriately tuned comb filter, which results in mitigation of the output current harmonics and reduced THD. Two types of comb filters have been proposed as a harmonic compensator, namely feedback and feedforward structures. The compensator included an additional FIR low-pass filter for increased robustness. Regardless of the structure chosen the solution is targeted at simplicity of analysis, design and implementation. Furthermore, the compensator based on the feedforward comb filter is casual, hence its implementation on the digital microprocessors is greatly facilitated. The proposed two-stage design of the control loop ensures the stability even in the case of additional poles being introduced by the feedback comb filter. Investigation on frequency variations impact is also included. The research was conducted by means of the following IT solutions: data workflow management environment, code design and generation (Matlab), and user interface design (ControlDesk). The experimental results have demonstrated the effectiveness of the proposed solution for a grid-connected converter operating in a network with distorted supply voltage. [ABSTRACT FROM AUTHOR]

A current-error space-vector-based hysteresis current controller for a general n-level voltage-source inverter (VSI)-fed three-phase induction motor (IM) drive is proposed here, with control of the switching frequency variation for the full linear modulation range. The proposed current controller monitors the space-vector-based current error of an n -level VSI-fed IM to keep the current error within a parabolic boundary, using the information of the current triangular sector in which the tip of the reference vector lies. Information of the reference voltage vector is estimated using the measured current-error space vectors, along the \alpha- and \beta-axes. Appropriate dimension and orientation of this parabolic boundary ensure a switching frequency spectrum similar to that of a constant-switching-frequency voltage-controlled space vector pulsewidth modulation (PWM) (SVPWM)-based IM drive. Like SVPWM for multilevel inverters, the proposed controller selects inverter switching vectors, forming a triangular sector in which the tip of the reference vector stays, for the hysteresis PWM control. The sector in the n-level inverter space vector diagram, in which the tip of the fundamental stator voltage stays, is precisely detected, using the sampled reference space vector estimated from the instantaneous current-error space vectors. The proposed controller retains all the advantages of a conventional hysteresis controller such as fast current control, with smooth transition to the overmodulation region. The proposed controller is implemented on a five-level VSI-fed 7.5-kW IM drive. [ABSTRACT FROM PUBLISHER]

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. [ABSTRACT FROM AUTHOR]

In this paper, a new three-phase, five-level inverter topology with a single-dc source is presented. The proposed topology is obtained by cascading a three-level flying capacitor inverter with a flying H-bridge power cell in each phase. This topology has redundant switching states for generating different pole voltages. By selecting appropriate switching states, the capacitor voltages can be balanced instantaneously (as compared to the fundamental) in any direction of the current, irrespective of the load power factor. Another important feature of this topology is that if any H-bridge fails, it can be bypassed and the configuration can still operate as a three-level inverter at its full power rating. This feature improves the reliability of the circuit. A 3-kW induction motor is run with the proposed topology for the full modulation range. The effectiveness of the capacitor balancing algorithm is tested for the full range of speed and during the sudden acceleration of the motor. [ABSTRACT FROM AUTHOR]

A torque control scheme, based on a direct torque control (DTC) algorithm using a 12-sided polygonal voltage space vector, is proposed for a variable speed control of an open-end induction motor drive. The conventional DTC scheme uses a stator flux vector for the sector identification and then the switching vector to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady-state model of IM and the synchronous frequency of operation is derived from the computed stator flux using a low-pass filter technique. The proposed DTC scheme utilizes the exact positions of the fundamental stator voltage vector and stator flux vector to select the optimal switching vector for fast control of torque with small variation of stator flux within the hysteresis band. The present DTC scheme allows full load torque control with fast transient response to very low speeds of operation, with reduced switching frequency variation. Extensive experimental results are presented to show the fast torque control for speed of operation from zero to rated. [ABSTRACT FROM AUTHOR]

This paper proposes a sensorless vector control scheme for general-purpose induction motor drives using the current error space phasor-based hysteresis controller. In this paper, a new technique for sensorless operation is developed to estimate rotor voltage and hence rotor flux position using the stator current error during zero-voltage space vectors. It gives a comparable performance with the vector control drive using sensors especially at a very low speed of operation (less than 1 Hz). Since no voltage sensing is made, the dead-time effect and loss of accuracy in voltage sensing at low speed are avoided here, with the inherent advantages of the current error space phasor-based hysteresis controller. However, appropriate device on-state drops are compensated to achieve a steady-state operation up to less than 1 Hz. Moreover, using a parabolic boundary for current error, the switching frequency of the inverter can be maintained constant for the entire operating speed range. Simple \sigma Ls estimation is proposed, and the parameter sensitivity of the control scheme to changes in stator resistance, Rs is also investigated in this paper. Extensive experimental results are shown at speeds less than 1 Hz to verify the proposed concept. The same control scheme is further extended from less than 1 Hz to rated 50 Hz six-step operation of the inverter. Here, the magnetic saturation is ignored in the control scheme. [ABSTRACT FROM AUTHOR]

A multilevel inverter topology for seven-level space vector generation is proposed in this paper. In this topology, the seven-level structure is realized using two conventional two-level inverters and six capacitor-fed H-bridge cells. It needs only two isolated dc-voltage sources of voltage rating Vdc/2 where Vdc is the dc voltage magnitude required by the conventional neutral point clamped (NPC) seven-level topology. The proposed topology is capable of maintaining the H-bridge capacitor voltages at the required level of Vdc/6 under all operating conditions, covering the entire linear modulation and overmodulation regions, by making use of the switching state redundancies. In the event of any switch failure in H-bridges, this inverter can operate in three-level mode, a feature that enhances the reliability of the drive system. The two-level inverters, which operate at a higher voltage level of Vdc /2, switch less compared to the H-bridges, which operate at a lower voltage level of Vdc/6, resulting in switching loss reduction. The experimental verification of the proposed topology is carried out for the entire modulation range, under steady state as well as transient conditions. [ABSTRACT FROM AUTHOR]

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive. [ABSTRACT FROM PUBLISHER]

This paper presents a five-level inverter scheme with four two-level inverters for a four-pole induction motor (IM) drive. In a conventional three-phase four-pole IM, there exists two identical voltage-profile winding coil groups per phase around the armature, which are connected in series and spatially apart by two pole pitches. In this paper, these two identical voltage-profile pole-pair winding coils in each phase of the IM are disconnected and fed from four two-level inverters from four sides of the windings with one-fourth dc-link voltage as compared to a conventional five-level neutral-point-clamped inverter. The scheme presented in this paper does not require any special design modification for the induction machine. For this paper, a four-pole IM drive is used, and the scheme can be easily extended to IMs with more than four poles. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive. [ABSTRACT FROM AUTHOR]

In this paper, a novel 12-sided polygonal space vector structure is proposed for an induction motor drive. The space vector pattern presented in this paper consists of two 12-sided concentric polygons with the outer polygon having a radius double the inner one. As compared to previously reported 12-sided polygonal space vector structures, this paper subdivides the space vector plane into smaller sized triangles. This helps in reducing the switching frequency of the inverters without deteriorating the output voltage quality. It also reduces the device ratings and dv/dt stress on the devices to half. At the same time, other benefits obtained from the existing 12-sided space vector structure, such as increased linear modulation range and complete elimination of 5th and 7th order harmonics in the phase voltage, are also retained in this paper. The space vector structure is realized by feeding an open-end induction motor with two conventional three-level neutral point clamped (NPC) inverters with asymmetric isolated dc link voltage sources. The neutral point voltage fluctuations in the three-level NPC inverters are eliminated by utilizing the switching state multiplicities for a space vector point. The pulsewidth modulation timings are calculated using sampled reference waveform amplitudes and are explained in detail in this paper. Experimental verification on a laboratory prototype shows that this configuration may be considered suitable for high power drives. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n ± 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n ± 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. the benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses. [ABSTRACT FROM AUTHOR]

This paper develops a seven-level inverter structure for open-end winding induction motor drives. The inverter supply is realized by cascading four two-level and two three-level neutral- point-clamped inverters. The inverter control is designed in such a way that the common-mode voltage (CMV) is eliminated. DC-link capacitor voltage balancing is also achieved by using only the switching-state redundancies. The proposed power circuit structure is modular and therefore suitable for fault-tolerant applications. By appropriately isolating some of the inverters, the drive can be operated during fault conditions in a five-level or a three-level inverter mode, with preserved CMV elimination and dc-link capacitor voltage balancing, within a reduced modulation range. [ABSTRACT FROM AUTHOR]

In this paper, a 12-sided polygonal voltage space vector generation with common-mode voltage elimination (CME) is proposed for an induction motor drive. An open-end winding configuration is used for the motor. The proposed multilevel structure is achieved by cascading only the conventional two-level inverters with asymmetrical dc link voltages. By appropriately selecting the voltage vectors with identical common-mode voltage from the opposite ends, a pulsewidth modulation (PWM) strategy with zero common-mode voltage variation can be achieved for the entire modulation range with a common dc link requirement for both the inverter systems. Along with the CME, the proposed 12-sided polygonal space vector based multilevel inverter structure has increased modulation range with the absence of 5th, 7th, 17th, 19th, etc., harmonics up to 12-step operation. The bandwidth problems associated with conventional hexagonal voltage space vector structure current controllers due to the presence of 5th and 7th harmonics in the overmodulation region are absent in the present 12-sided structure. So a simple PWM voltage control with linear voltage control up to 12-step operation is possible from the present 12-sided scheme with less current control complexity. [ABSTRACT FROM AUTHOR]

Multilevel inverters are preferred over two-level inverters in high-voltage, high-power applications mainly because low-switching-frequency PWM schemes can be implemented with power devices of low-voltage ratings. Common multilevel inverter structures such as NPC, H-bridge and flying capacitor will produce a hexagonal voltage space vector structure. In the over-modulation range a multilevel inverter with a hexagonal voltage space vector structure will produce high amplitude 5th and 7th harmonic voltages in the output voltages. The maximum phase peak fundamental voltage is 0.637 Vdc in six-step mode operation (where Vdc is the radii of the hexagonal voltage space vector structure). A 12-sided polygonal voltage space vector structure will have a maximum phase peak fundamental voltage of 0.64 Vdc in the linear modulation range itself (where Vdc is the radii of the 12-sided polygonal voltage space vector structure), which is more than the output in six-step operation in the over-modulation range for a conventional multilevel structure. Also with a 12-sided polygonal space vector structure, an additional boost of the fundamental phase voltage is possible in the 12-step operation with the elimination of the 5th- and 7th- order harmonics (6n±1, n=1, 3, 5 ... etc). A multilevel inverter structure with 12-sided polygonal voltage space vector structure is proposed for an induction motor drive. The proposed inverter structure is realised by cascading three conventional two-level inverters. This makes the power bus structure very simple. [ABSTRACT FROM AUTHOR]

Split-phase (six-phase) induction motor stator windings consist of two sets of three phase windings, which are spatially phase separated by 30 electrical degrees. Due to mutual cancellation of the air gap flux for all the 6n ± 1 (n = 1,3,5. . . .) order harmonic voltages, called zero sequence components, large harmonic currents are generated in the stator phases. Only the 12n±1 (n = 0,1,2,3 . . . .)-order harmonic voltage components contribute toward the air gap flux and electromagnetic torque production in the machine. In this paper, a novel scheme is proposed where two six-phase induction motors are connected in series with proper phase sequence so that the zero sequence component voltages of one machine act as torque and flux producing components for the other. Thus, the two six-phase motors can be independently controlled from a single six-phase inverter. A vector control scheme for the dual motor drive is developed and experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

A pulse width modulation (PWM) scheme for multilevel inverters is proposed. The proposed PWM scheme generates the inverter leg switching times, from the sampled reference phase voltage amplitudes and centres the switching times for the middle vectors, in a sampling interval, as in the case of conventional space vector PWM (SVPWM). The SVPWM scheme, presented for multilevel inverters, can also work in the overmodulation range, using only the sampled amplitudes of reference phase voltages. The present PWM technique does not involve any sector identification and considerably reduces the computation time when compared to the conventional space vector PWM technique. The present PWM signal generation scheme can be used for any multilevel inverter configuration. A five-level inverter configuration, using an open- ended winding induction motor drive, is used to verify the SVPWM generation scheme experimentally. [ABSTRACT FROM AUTHOR]

A scheme for a three-level voltage space phasor generation with common-mode voltage elimination is proposed. An open-end-winding induction motor, fed from both ends by two three- level inverters, which are realised by a cascading two two-level inverter, is used in this configuration. The voltage space vectors of individual three-level inverters, which generate the same common- mode voltage in the inverter pole voltage, are variously grouped. When these voltage space vectors are used to switch individual three-level inverters, it results in zero common-mode voltage across the motor windings. in the proposed scheme, voltage space phasors from individual inverters with zero common-mode voltage in the inverter pole voltage are used for PWM control. For the proposed drive configuration, the DC link voltage requirement is only half when compared to the DC link voltage of a conventional neutral-point-clamped (NPC) three-level inverter. The proposed inverter configuration offers reduced circuit and control complexity when compared to similar schemes with NPC or H-bridge inverter configurations. [ABSTRACT FROM AUTHOR]