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We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin $(25~\mu{\rm m})$ silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage $({\rm V}_{\rm ramp})$ breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer.

Accurate reliability predictions of real-world digital logic circuits rely heavily on the relevancy of device-level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device-level reliability data into a practical information for the real-world circuit implications. In this paper, we develop a methodology to bridge this gap by employing an eye diagram approach, which allows us to monitor, at circuit speed, device-level random jitter degradation in response to stress. By employing a variety of positive BTI gate voltage stress and sense bit sequences (including dc, ring oscillator (RO), and pseudorandom), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional RO-type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using RO structures as a proxy for real-random logic circuits. Only when a pseudorandom bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device-level reliability data to predict real-world digital logic circuit degradation.

InGaAs MOS C-V and G-V characteristics are measured under illumination to identify regions of strong minority carrier response related to surface inversion. For the MOS structure with n-type substrate biased in inversion, a high density of surface states in the proximity of the valence band edge is present that masks the response of light generated minority carriers at room temperature. Much stronger effect of illumination is observed at low temperature where the surface-state response is suppressed due to carrier freeze out. On the other hand, for the MOS structure with p-type substrate, strong minority carrier response under illumination is readily observed in inversion even at room temperature, reflecting that the density of surface states near the edge of conduction band is negligible. All the data can be explained in the framework of small-signal equivalent circuit, by modeling the minority carrier generation with a light-dependent conductance plugged in between the conduction band and the valence band. The model is validated against the measured MOS conductance with and without light in inversion.

Variability in resistive switching memory (RRAM) devices is studied by applying an AC measurement setup capable of efficiently collecting read current data in low and high resistance states (LRS and HRS, respectively) in each consecutive pulse SET/RESET cycle. It is found that HRS and LRS read current values follow the lognormal and normal distributions, respectively. Endurance test demonstrates that, in a small percentage of cycles, the set operation may fail, which might be missed when a conventional approach of a limited number of read operations is employed.

Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

BeO was investigated as the interface passivation layer (IPL) between a high-k dielectric and a III-V compound semiconductor substrate in metal-oxide-semiconductor (MOS) devices. One of the critical issues facing the fabrication of next generation MOS devices is the minimization of damage to the III-V semiconductor substrate during the etching of the thin IPL. In this study, atomic layer etching (ALET) was investigated for etching of BeO as the IPL on a GaAs substrate to control the etch depth precisely and to minimize the damage to the III-V semiconductor substrate. By using ALET to etch BeO, which uses BCl"3 as the adsorption gas for the formation of chloride compounds (Be-Cl and BCl-O) and Ar as the desorption gas for the removal of the chloride compounds, a self-limited, one-monolayer etch rate of about 0.75A/cycle was achieved with no increase of surface roughness and without change of surface composition. Moreover, under the BeO ALET conditions, which are able to precisely stop etching over the GaAs substrate after removing BeO, the exposed GaAs substrate showed surface composition and surface roughness similar to those of the as-received GaAs substrate.

We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.

Graphical abstractDisplay Omitted The origin of the TDDB bimodality was studied in high-k (HK) gate stacks using a CAFM.The roles of the interfacial layer/HK layer and the HfO2 polycrystalline structure were evaluated.Bimodal characteristic was attributed to the different electrical properties of Gs and GBs.BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the GBs.The gate stack BD is triggered by the BD of the SiO2 layer. Dielectric breakdown (BD) in polycrystalline HfO2/SiO2 gate stacks has been studied using a conductive atomic force microscopy (CAFM) technique, which allows employing a nanosize probe to apply a highly localized electrical stress. The resulting BD statistics indicate that BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the grain boundaries (GBs) of the overlaying polycrystalline HfO2 film due to higher conductivity of the GB compared to that of the grains.

We study resistive switching memories with Hf or Ti metal oxygen exchange layers.STEM dark field and EELS are used to observe the conductive filament.The filament is a cone-shaped metal-rich region in the HfO2 dielectric layer.Composition of the metallic filament is dominated by Hf or Ti depending on the OEL. A detailed physical analysis of the conductive filament electrically formed in HfO2-based resistive switching memory devices with both Hf and Ti metal oxygen exchange layers is presented. The filament, observed by applying transmission electron microscopy (TEM), scanning TEM (STEM), and electron energy loss spectroscopy (EELS) techniques to 50i?50nm2 cells, is a cone-shaped metal-rich region in the HfO2 dielectric of the resistive switching device.

For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate dielectric of CMOSFEETs.

In this paper we analyze Random Telegraph Signal (RTS) noise and Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

We introduce a data analysis methodology for multifrequency charge-pumping (CP) measurements, which allows extracting both spatial and energy profiles of the CP-active traps in the gate dielectrics along with the defect energy characteristics. The analysis is based on the charge trapping/detrapping model accounting for carriers tunneling between the substrate and the oxide traps and multiphonon-assisted structural trap relaxation associated with charge carrier localization in the trap. Comparison of the spatial and energy trap distribution profiles obtained from CP data collected on a set of high-k dielectric gate stacks of different thicknesses facilitate the calibration of the model parameters. Extraction of the bulk trap characteristics, including trap ionization and relaxation energies, extends the utility of the CP technique from quantifying defect density toward identifying the nature of defects in the dielectric.

Spike-timing-dependent plasticity (STDP) is a fundamental learning rule observed in biological synapses that is desirable to replicate in neuromorphic electronic systems. Nanocrystalline-silicon thin film transistors (TFTs) and memristors can be fabricated at low temperatures, and are suitable for use in such systems because of their potential for high density, 3-D integration. In this paper, a compact and robust learning circuit that implements STDP using biologically realistic nonmodulated rectangular voltage pulses is demonstrated. This is accomplished through the use of a novel nanoparticle memory-TFT with short retention time at the output of the neuron circuit that drives memristive synapses. Similarities to biological measurements are examined with single and repeating spike pairs or different timing intervals and frequencies, as well as with spike triplets.

In a previous study, atomic layer deposited (ALD) BeO exhibited less interface defect density and hysteresis, as well as less frequency dispersion and leakage current density, at the same equivalent oxide thickness than Al2O3. Furthermore, its self-cleaning effect was better. In this study, the physical and electrical characteristics of ALD BeO grown on Si and GaAs substrates are further evaluated as a gate dielectric layer in III–V metal-oxide-semiconductor devices using transmission electron microscopy, selective area electron diffraction, second harmonic generation, and electrical analysis. An as-grown ALD BeO thin film was revealed as a layered single crystal structure, unlike the well-known ALD dielectrics that exhibit either poly-crystalline or amorphous structures. Low defect density in highly ordered ALD BeO film, less variability in electrical characteristics, and great stability under electrical stress were demonstrated.

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO"2 thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0

In a previous study, we demonstrated that the BeO film grown by atomic layer deposition (ALD) on Si and III-V metal-oxide-semiconductor devices has excellent electrical and physical characteristics. In this paper, we discuss the physical and electrical properties of ALD BeO as an oxygen diffusion barrier on scaled 4-nm HfO2/BeO gate stacks. Thin BeO layers are deposited onto (100) p-Si substrates as an alternative to SiO2 as an interfacial passivation layer (IPL). X-ray photoelectron spec troscopy and transmission electron microscopy show that the BeO IPL acts as an effective oxygen barrier against SiOιι. native oxide formation during postdeposition annealing (PDA). The use of ALD BeO as an oxygen diffusion barrier results in lower equivalent oxide thickness, more competitive leakage current, and better reliability characteristics after PDA than Al2O3 and HfO2 gate stacks.

Beryllium oxide (BeO), which has excellent electrical insulating characteristics and high thermal stability, is a promising gate dielectric and interface passivation layer (IPL), because of its high energy bandgap (10.6 eV) and short bond distance between Be and O atoms. In a previous study, we demonstrated the excellent electrical and physical characteristics of BeO grown after atomic layer deposition (ALD) on Si and GaAs substrates. Here we report, for the first time, ALD growth of crystalline BeO as a potential high- k gate dielectric and IPL. From TEM, SAD, RHEED, and XRD, we have found that highly crystalline BeO thin film may be grown in a wurtzite structure as a (101) plane on a Si (100) oriented surface. We have also investigated a germanium epitaxial layer grown on BeO as a semiconductor-on-insulator (SOI) application, and the crystallinity of BeO on a GaAs (100) substrate for III–V MOS device applications.

Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high- k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.

In this work, we combine conductive atomic force microscopy (CAFM) and first principles calculations to investigate leakage current in thin polycrystalline HfO"2 films. A clear correlation between the presence of grain boundaries and increased leakage current through the film is demonstrated. The effect is a result of a number of related factors, including local reduction in the oxide film thickness near grain boundaries, the intrinsic electronic properties of grain boundaries which enhance direct tunnelling relative to the bulk, and segregation of oxygen vacancy defects which increase trap assisted tunnelling currents. These results highlight the important role of grain boundaries in determining the electrical properties of polycrystalline HfO"2 films with relevance to applications in advanced logic and memory devices.

Low frequency noise (LFN) characterization was performed on the HfSiON gate stacks fabricated with the SiON interfacial layers (ILs) and a La cap layer. The LFN data identified N and La related defects located in the IL/HK region.

The frequency dispersion of the maximum capacitance of GaAs metal-oxide-semiconductor (MOS) capacitors is studied. The frequency dispersion behavior observed in the capacitance-voltage characteristics of GaAs MOS capacitors is a result of low semiconductor capacitance and an interface-state capacitance that varies with frequency. The traditional approach for calculating interface-state capacitance does not result in frequency dispersion of the maximum capacitance. An interface-state capacitance model based on an extremely high number of interface states in a thin disordered interfacial region is presented to explain the frequency dispersion behavior. The model shows an excellent match with the experimental results. The model also suggests that maximum capacitance values in low-frequency capacitance-voltage characteristics may be determined by the capacitance associated with the interface traps rather than the semiconductor charge and does not necessarily indicate the presence of free carriers.

This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (V"t) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V"t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La"2O"3 capping in NMOS and a SiGe channel in PMOS to achieve acceptable V"t for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO"2/Si interface on the HKMG MOSFET V"t-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.

Hafnium dioxide has been recently introduced as a gate dielectric in the field effect transistors. It belongs to a class of high dielectric constant or high-k dielectrics. We briefly discuss the structural and electronic properties of bulk hafnia, and show how oxygen vacancies believed to affect the band alignment across the metal oxide semiconductor (MOS) stack are stabilized in hafnia films next to high work function metals.

A new ''smart'' algorithm with adaptive testing is developed for automatically monitoring gate dielectric degradation during CVS using SILC. In this approach, stress current is monitored with a sampling rate as fast as ~2ms/point while SILC data are collected based on stress current changes and/or time intervals. This automated test was applied to study degradation of nMOS transistors with TiN/HfO"2 gate stacks where changes in the SILC data correlate directly with transitions in the stress current. From this SILC data, the differential resistance can be extracted and used to monitor conductivity throughout the degradation phase until breakdown.

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO 2 /interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for extraction of the PBD time and its dependence on gate voltage are reported.

A review of literature combined with recent experimental results addressing the intrinsic and extrinsic factors controlling the effective work function (EWF) of metal gate electrodes on Hf-based high-K dielectrics is discussed. Through a systematic study including accurate extraction of EWF, our observations suggest, unlike popularly perceived, intrinsic E"f-pinning does not limit the EWF tuning on high-K. Also, a critical issue challenging the maintenance of high EWF metals at low effective oxide thicknesses (EOT), due to a new phenomena described as the ''V"f"b roll-off'', is reported for the first time.

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO"2 [email protected] gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin [email protected] layers (=

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO 2 gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, Δ V TH . The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO 2 interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO 2 interface ( P b centers) and its vicinity ( E ′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I D − V G (Δ V TH ) techniques, however, suggests that Δ V TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO 2 /SiO 2 gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO 2 and high-k gate stacks suggesting a common mechanism of the interface degradation.

The electrically active defects in high-k/SiO"2 dielectric stacks are examined using a combination of low frequency noise (LFN) and charge pumping (CP) methods. The volume trap profile in the stacks is obtained by modeling the drain current noise spectra and charge pumping currents, with each technique covering a different depth range. The LFN is dependent on both the high-k and interfacial (IL) SiO"2 thicknesses while the CP current is mainly dependent on the IL thickness.

Various conventional and novel electrical characterization techniques have been combined with careful, robust analysis to properly evaluate high- κ gate dielectric stack structures. These measurement methodologies and analysis techniques have enhanced the ability to separate pre-existing defects that serve as fast transient charging and discharging sites from defects generated with stress. In addition, the differentiation of electrically active bulk high- κ traps, silicon substrate interface traps, and interfacial layer traps has been effectively demonstrated.

Dielectrics comprised of nano-crystalline HfO2 in gate stacks with thin SiO2/SiON interfacial transition regions display significant asymmetries with respect to trapping of Si substrate injected holes and electrons. Based on spectroscopic studies, and guided by ab initio theory, electron and hole traps in HfO2 and other transition metal elemental oxides are assigned to O-atom divacancies clustered at internal grain boundaries of nano-crystalline films. Engineering solutions in which grain boundary defects are suppressed include: (i) ultra-thin

The properties of high-κ metal oxide gate stacks are often determined in the final processing steps following dielectric deposition. We report here results from medium energy ion scattering and x-ray photoelectron spectroscopy studies of oxygen and silicon diffusion and interfacial layer reactions in multilayer gate stacks. Our results show that Ti metallization of HfO2∕SiO2∕Si stacks reduces the SiO2 interlayer and (to a more limited extent) the HfO2 layer. We find that Si atoms initially present in the interfacial SiO2 layer incorporate into the bottom of the high-κ layer. Some evidence for Ti–Si interdiffusion through the high-κ film in the presence of a Ti gate in the crystalline HfO2 films is also reported. This diffusion is likely to be related to defects in crystalline HfO2 films, such as grain boundaries. High-resolution transmission electron microscopy and corresponding electron energy loss spectroscopy scans show aggressive Ti–Si intermixing and oxygen diffusion to the outermost Ti layer, given ...

Gate dielectrics comprised of nanocrystalline HfO2 in gate stacks with thin SiO2/SiON interfacial transition regions display significant asymmetries with respect to trapping of Si substrate injected holes and electrons. Based on spectroscopic studies, and guided by ab initio theory, electron and hole traps in HfO2 and other transition metal elemental oxides are assigned to O-atom divacancies, clustered at internal grain boundaries. Three engineering solutions for defect reduction are identified: i) deposition of ultra-thin, < 2 nm, HfO2 dielectric layers, in which grain boundary formation is suppressed by effectively eliminating inter-primitive unit cell π-bonding interactions, ii) chemically phase separated high HfO2 silicates in which inter-primitive unit cell p-bonding interactions are suppressed by the two nanocrystalline grain size limitations resulting from SiO2 inclusions, and iii) non-crystalline Zr/Hf Si oxynitrides without grain boundary defects.

Silicon suboxides play an important role in different industrial applications, particularly in the form of the Si–SiO2 interface, which is one of the key elements in present day microelectronics and potentially in future nano-electronics as well. This paper focuses on the chemical and mechanical effects related to the existence of different oxidation states of Si atoms in SiO x systems with various Si:O composition and topology, such as O atoms in Si, the Si–SiO2 interface, and O vacancies in SiO2. We compare the stress–strain relation in SiO2 interfaces with (100), (111) and (110) surfaces, the relative stability of oxygen vacancies at different locations in Si–SiO2 layers and defects in Si and SiO2 crystals related to O migration. Our study is based on ab initio computations of molecular and periodic systems with both localized and plane wave basis sets.

The effective work function (EWF) extracted on terraced oxide structures by capacitance-voltage-based techniques was compared with the work function calculated from the barrier height extracted by current-voltage measurements. The results show a reasonable correlation-within /spl plusmn/ 0.1 eV-in the EWF values for various metal gate electrodes, validating both techniques for EWF extraction.

Since high- k materials are very different from SiO 2 , both structurally and electrically, conventional characterization and reliability methods that have been developed for SiO 2 devices may not be applicable to high- k dielectric devices. Fast transient charging effects degrade the drive current of high- k devices due to electron trapping in the gate dielectric. Because of this phenomenon, conventional DC drain current–gate voltage ( I d –V g ) measurements may underestimate the drain current, which translates to lower extracted mobility values, which has been confirmed by ultra short pulse measurements. The fast spontaneous post-stress relaxation phenomenon could complicate the assessment and interpretation of the threshold voltage ( V TH ) instability in high- k devices. The results obtained with a novel inversion pulse measurement method demonstrate that the V TH relaxes after a post-stress period of a couple of hundred microseconds. Consequently, the magnitude of V TH instability is underestimated when a relatively slow switching matrix is used for the stress/sense measurements.

The effects of HfO"2 thickness on charge trapping and mobility were investigated. The impact of fast transient electron trapping on DC measurements results in underestimating channel carrier mobility. Scaling the physical thickness of the HfO"2 dielectric causes less charge trapping and higher mobility. A HfO"2 -based high-k solution requires fine-tuning the thickness of the high-k film to maintain a balance between electron trapping in thicker films and increased leakage current in thinner films.

Hot carrier reliability of the HfSiON dielectric with the TiN metal gate electrode has been studied in the nMOS and pMOS short channel transistors. Hot carrier induced degradation of the high-/spl kappa/ gate stack devices are severe than the one in the SiO/sub 2//poly devices. It is determined that total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects. The hot carrier contribution induces permanent damage while cold carrier contribution is shown to be reversible. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite polarity) bias after the stress.

Using ab initio density functional calculations we study implications of film growth kinetics on the structure and defects at the HfO"2/Si(001) interface region. We introduce a simplified model for the atomic layer deposition with HfCl"4 as a metal precursor and H"2O as the oxidant. The model suggests that the initial interface growth results in a typically less than 1 monolayer of Hf in the first metallic layer. As a consequence, the oxygen coordination at the interface is either two (one Si and one Hf atom) or three (two Hf and one Si atoms), which partially supports the kinetically motivated interface models but is in contrast with the epitaxially motivated models suggested previously. Further calculations show the oxygen vacancy formation energy at the Si-O-Hf sites is ~1 eV lower than that in the bulk HfO"2. This makes the Si-Hf bond a likely interface defect, which is predicted to be a shallow hole trap. Calculations also predict interstitial oxygen to migrate from HfO"2 into Si substrate resulting in the formation of the SiO"x interface layer.

We investigate the physical mechanisms of breakdown in 21A thick silicon dioxide gate oxides in n-channel and p-channel metal-oxide-semiconductor field-effect transistors. The oxide breakdown investigation is based on the direct measurement of the stress-induced charge trapped in the oxide using the direct-current current-voltage technique. The measurements show several parallel breakdown pathways with different oxide field dependence. Direct correlation was found between the steplike increase in the gate current and the oxide-trapped charge. The results point to the multistep character of the oxide breakdown that includes generation of precursor defects by the injection and trapping of either electrons or holes. The weakened defect (breakdown precursor) bonds may be broken by the applied electric field and temperature leading to generation of a conductive percolation path. Time-to-breakdown model is developed taking into the account the oxide field dependence of the different breakdown mechanisms.

Response of the high-k gate dielectrics to low voltage stresses was studied by probing high-k transistors with various voltage/time measurements at different temperatures. The observed dependence of the transistor threshold voltage on stress time was attributed to electron trapping at pre-existing defects in the high-k dielectric rather than stress-induced trap generation. The dominance of the contribution from the reversible electron trapping on the pre-existing defects in the low voltage stress response raises the question on the applicability of the conventional reliability assessment methodology to the high-k dielectrics.

Responding to the market growth for computational power in various applications, semiconductor technology continues unabated in its drive towards higher transistor densities and faster transistors. The general direction of this trend is scaling down the critical transistor dimensions of integrated circuit (IC) components.

Electron detrapping in the TiN/HfO2 gate n-MOSFET under dynamic positive-bias temperature instability (PBTI) is examined. Similar to hole detrapping under dynamic negative-bias temperature instability (NBTI), electron detrapping per relaxation cycle is a constant under a low oxide stress field (~ 5.5 MV/cm), independent of the number of times the transistor is stressed and relaxed, and it progressively decreases with the number of stress/relaxation cycles at a higher oxide stress field (~7 MV/cm). Analysis shows that the decrease is due to a portion of the electron trap states being transformed into deeper levels, thereby increasing the emission time of the trapped electrons. However, unlike hole detrapping, the decrease in electron detrapping is not accompanied by a correlated increase in the stress-induced leakage current, and it can be reversed with a moderate negative gate voltage. These differences from NBTI suggest that distinct defects are active under PBTI. Accepted version

A model is proposed to address the effects of oxide electric field and anode bias, as well as the role of hydrogen, in the trap generation process. The oxide wear-out phenomenon is considered as a multi-step process initiated by the capture of injected electrons by localized states in SiO2. The captured electrons significantly weaken the corresponding Si-O bond, which becomes unstable with respect to the applied electric field and temperature. The hydrogen present in the oxide (due to the anode hydrogen release process) prevents restoration of the broken bonds and leads to the generation of neutral E' centers. The model describes the charge-to-breakdown dependence on the electron energy, electric field, temperature, and oxide thickness.

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moore's Law towards the 10-nm physical gate length regime.

The initial steps of gate oxide wear-out phenomenon are considered using quantum mechanical cluster density functional theory calculations. As was proposed earlier, precursor breakdown defects can be formed due to capture of the injected electrons by localized gap states induced by structural imperfections in SiO2. In this publication, we have shown that the electron capture weakens the Si–O bond, which can then be broken due to its polarization and vibrational excitation. In the next step, a donor–acceptor bond between the negatively charged oxygen and neighboring silicon atom may be formed creating a chain of bond swapping. The proposed model suggests a novel mechanism for the formation of paramagnetic defects in the oxides (E 0 centers), which can contribute to the formation of a conduction path in the oxide film and its dielectric breakdown. The proposed model describes the observed charge-to-breakdown dependence on electric field, temperature, electron fluence, and oxide thickness. 2002 Elsevier Science B.V. All rights reserved.

In this letter we not only show improvement in the performance but also in the reliability of 30nm thick biaxially strained SiGe (20%Ge) channel on Si p-MOSFETs. Compared to Si channel, strained SiGe channel allows larger hole mobility ({\mu}h) in the transport direction and alleviates charge flow towards the gate oxide. {\mu}h enhancement by 40% in SiGe and 100% in Si-cap SiGe is observed compared to the Si hole universal mobility. A ~40% reduction in NBTI degradation, gate leakage and flicker noise (1/f) is observed which is attributed to a 4% increase in the hole-oxide barrier height ({\phi}) in SiGe. Similar field acceleration factor ({\Gamma}) for threshold voltage shift ({\Delta}VT) and increase in noise ({\Delta}SVG) in Si and SiGe suggests identical degradation mechanisms., Comment: 4 figures, 3 pages, accepted for publication in IEEE EDL