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This article presents an improved virtual space vector modulation scheme for the reduced switch count three-level inverter with balanced and unbalanced neutral-point voltage (NPV) conditions. By analyzing the effects of unbalanced NPV conditions on basic voltage vectors, the new virtual vectors are constructed by considering the dc unbalancing coefficient and distribution factor for small vectors simultaneously. To facilitate the calculation of duty cycles, the nonorthogonal coordinate system is employed. In addition, an optimized control scheme is developed to obtain the optimized distribution factor, and the relative durations of P-type and N-type small vectors are adjusted to control the voltages across two dc-link capacitors separately. The satisfactory quality of output currents is maintained with both balanced and unbalanced NPV conditions. The feasibility of the proposed scheme is verified by simulated and experimental results. [ABSTRACT FROM AUTHOR]

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of a three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this article proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulsewidth modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small, and zero vectors) to reduce the root mean square value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of the value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion. The effectiveness of the proposed method is validated by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

In high-power applications, selective harmonic elimination pulsewidth modulation (SHEPWM) method is widely used to eliminate low-order harmonics in three-level inverters with low power losses. However, it faces the challenges that the conventional optimization methods for solving harmonic elimination equations in SHEPWM are easy to be trapped in local optimum. Moreover, the neutral point (NP) voltage of three-level inverter cannot be balanced under low-voltage ride-through (LVRT) condition with conventional SHEPWM method. To address these problems, a SHEPWM scheme is proposed, which is on the basis of an improved particle swarm optimization (IPSO) algorithm to solve the harmonic elimination equations and an enhanced NP balance control method in LVRT operation. First, an IPSO algorithm is proposed to calculate the switching angles of the transcendental equations for harmonic elimination. The IPSO algorithm defines a nonlinear negative exponential inertia weight considering the current and optimal fitness value, which can dynamically adjust the local and global searching speed and step size according to the actual situation, greatly improving the convergence speed and solution accuracy and avoiding falling into the local optimum. Then, by increasing the degree of freedom of the output current direction and combining with the NP voltage deviation, an enhanced NP voltage balance control method of SHEPWM in LVRT operation is proposed. The validity of the proposed method is proved by simulation and experimental results. [ABSTRACT FROM AUTHOR]

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The high-frequency zero-sequence circulating current (HFZSCC) is generated when the carrier phases are different in a parallel rectifiers system. Therefore, a modified LCL filter is adopted to suppress the HFZSCC. Nevertheless, the internal common mode resonance current (ICMRC) and external zero-sequence resonance circulating current (EZSRCC) are produced, which causes system instability unavoidably. Since these two issues are coupled with each other, the conventional resonance currents control methods reported so far cannot address them properly simultaneously. To suppress ICMRC and EZSRCC, a detailed model analysis of internal common mode current and zero-sequence circulating current (ZSCC) are presented, which reveal the ICMRC and EZSRCC are related to capacitor-side ZSCC (CSZSCC). Then, based on the model, in this article, the controller of CSZSCC is presented to suppress ICMRC and EZSRCC. Additionally, a closed-loop controller is designed to reject disturbances of low-frequency zero-sequence circulating current (LFZSCC). It is realized by adjusting the duty cycle of the small vectors in each pulsewidth modulation sampling period. As a result, HFZSCC, ICMRC, EZSRCC, and LFZSCC are mitigated with the proposed scheme, thus, improving the quality of the input currents. Simulation and experimental results verify the effectiveness of proposed method. [ABSTRACT FROM AUTHOR]

With the increase of grid‐connected renewable power generation units, the three‐level converter (TLC) is widely utilized. However, when unbalanced grid voltage occurs, the converter should provide a certain of reactive power to satisfy the grid code, which decreases the power factor and degrades neutral‐point (NP) voltage balance. The existing model predictive control methods for NP voltage balance in TLC mainly focus on high power factor operation, which are not applicable to low power factor operation. To solve this problem, this study proposes a generalized model predictive control (GMPC) scheme for the TLC. By analyzing the influence of P‐type and N‐type small vectors on NP voltage, it is indicated that the charging and discharging operation of the dc‐link capacitors are determined by the grid currents directions with the defined small vectors. Since the directions of grid currents are changed with different power factors, the effect of one small vector on NP voltage is change. In the proposed GMPC scheme, the direction of grid currents and the capacitor voltage difference are simultaneously used to select the appropriate small vector to mitigate the NP voltage unbalance effectively in the full power factor range. The validity is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

The conventional model predictive control (MPC) suffers from high common-mode voltage (CMV) magnitude and large current ripples. In this article, the reduced CMV MPC strategy with double vector (RCMV-MPCDV) is proposed for three-level inverters, which adopts double vector to reduce the CMV and current ripples simultaneously in per-sampling period. First, based on geometric relationship of median, a novel cost function that evaluates median line distance is proposed to reduce the computational complexity, rather than evaluating the closest distance. Second, in order to reduce the computational burden, the double vector preselection algorithm is presented with fewer evaluation times. Third, the candidate vectors are reclassified and regrouped from partial basic vectors, which restricts CMV magnitude within one-sixth of dc-link voltage. In addition, to select more satisfactory double vectors for RCMV-MPCDV scheme, two improved methods are proposed to compensate the losing candidate vectors. The simulation and experimental results with steady-state performance and dynamic response validate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Vienna rectifier, which is a nongenerative-boost-type rectifier, is widely used in industrial applications, such as wind turbine systems. However, the Vienna rectifier will face the challenge of reducing common-mode voltage (CMV), maintaining the sinusoidal input currents, and balancing neutral-point (NP) voltage in practice. As these issues are mutually coupled, the conventional space vector modulation (SVM) and various types of enhanced schemes cannot solve these problems properly, especially under nonunity power factor operation. To overcome these limitations, a two-layer pulsewidth modulation scheme through vector selection is developed. In the first layer of the proposed strategy, the NP voltage oscillations are mitigated by adjusting the switching sequence and dwell time of large, medium, small, and zero vectors with reduced CMV as the same in large, medium, and zero vector modulation. In the second layer of the proposed strategy, the switching states are reselected, and the dwell times are real time adjusted to eliminate the distortions in input currents. Through the aforementioned two-layer control method, CMV reduction, input current distortion elimination, and NP voltage balancing in Vienna rectifier can be realized simultaneously. The correctness and effectiveness of the proposed SVM method are verified by the experiment. [ABSTRACT FROM AUTHOR]

Parallel three-level inverters have attracted considerable attention due to the advantages to increase the power rating and the flexibility of power conversion systems. However, this type of configuration requires to suppress the zero-sequence circulating current (ZSCC) through either modulation or active control strategies, to avoid overloading problems of a single three-level inverter. For the operation of paralleled three-level T-type inverters, another requirement is to reduce the common mode voltage (CMV) associated with a pulsewidth modulation method. To better solve these problems simultaneously, an optimized zero-sequence voltage injection method is proposed to both reduce CMV and eliminate ZSCC for multiparallel-connected three-level inverters. A generalized CMV reduction strategy is developed, which can reduce the magnitude of CMV to one half of the value using the conventional space vector modulation. The highlight of the method is that ZSCC is eliminated by adding an optimal compensation value to the reference duty signals with lower CMV. This compensation value is calculated simply by ZSCC, duty cycles, and filter parameters. The better ZSCC suppression performance can be obtained in both steady and transient states with the proposed scheme, thus, improving the quality of currents. [ABSTRACT FROM AUTHOR]

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

The improved LCL filter is used in transformerless three-level photovoltaic inverter system for leakage current suppression. However, the common-mode (CM) resonance circulating current (CMRCC) is generated, which causes inverter-side current oscillation, leakage current increment, and system instability. To overcome these issues, an improved CM circulating current model with detailed analyses of CMRCC is proposed in this paper. Based on above theories, the CMRCC is influenced by filter parameters, zero-sequence duty ratio, and number of switching transitions. To suppress CMRCC, a hybrid control strategy composed of proportional integral (PI) and feedforward control is presented. It is realized by real-time adjusting zero-sequence duty ratio in space vector modulation technique. Compared with the conventional damping resistor techniques, the CMRCC and leakage current are effectively suppressed with the proposed method. Thus, the performance of inverter-side currents and leakage current suppression is greatly improved. Besides, the capacitor-voltage-feedforward control is adopted to eliminate resonance peak in the differential-mode circuit. Simulation and experimental results are given to demonstrate the effectiveness of theoretical analyses and the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-sequence circulating current (ZSCC) control scheme for the multiparalleled three-level T-type inverters (3LT2Is). Based on the analysis with the proposed generalized model of multiparalleled 3LT2Is, it is seen that the ZSCC is influenced by the circuit parameters, duty cycles, and the circulating currents of the l th and first 3LT2I. To mitigate the circulating currents, a deadbeat control strategy for n-paralleled (n≥3) inverters is proposed, which is realized by adjusting the duty cycle of the small vectors in each PWM sampling period. Compared with the conventional PI control method, the ZSCC spike is mitigated with the proposed scheme, thus improving the quality of the output currents. Also, the reliability of the 3LT2Is system is improved because such a scheme only needs the information about the ZSCC and zero-sequence duty ratio in the l th and the first inverter. The proposed method can also be applied to the neutral-point-clamped converters. Simulation and experimental results verify the effectiveness of the theoretical analysis and the proposed method. [ABSTRACT FROM PUBLISHER]