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As the progress of technology continues in accordance to Moore's law, the density and downsizing of circuitry presents a significant vulnerability to the effects of soft errors. This study proposed a novel method to mitigate soft errors by increasing the robustness of complementary metal oxide semiconductor (CMOS) technology against soft errors via the use of transmission gates within the memory nodes of static random access memory (SRAM) which functioned as a low pass filter that disallowed the occurrence of data corruption. The proposed SRAM was tested against parameter variation of supply voltage and temperature. The critical charge was observed to increase with supply voltage increase, with the opposite being true of the increase in temperature. The increase in critical charge of up to 88.63% was achieved with regards to parameter variation for the transmission gate SRAM in comparison to the 6T SRAM. [ABSTRACT FROM AUTHOR]

This review explains the historical perspective of single-event effects, single-event transitions, and single-event upsets. It delves into the concept of critical charge and offers a comprehensive classification of single-event upsets. The main aspects of this work involve an explanation of the root causes of soft errors in VLSI circuits. The primary source of radiation in the space environment is thoroughly analyzed, discussing particle generation and interactions. This examination includes the behavior of energetic alpha particles and their interactions in silicon, as well as the impact of high-energy neutrons and nuclear interactions in silicon. Additionally, the study presents a detailed exploration of soft error simulation and calculation methods, enabling the estimation of soft error rates (SERs) and mean time to failure (MTTF). The focus of this research is the investigation of soft errors in memory and sequential circuitry, demonstrating the potential risks posed by these errors in electronic systems. The findings of this research provide a valuable foundation for developing strategies to mitigate soft errors and enhance the reliability of VLSI circuits for space applications. To highlight understanding, we have ended most of the sections and subsections with the questions. These questions can help researchers explore related research directions. [ABSTRACT FROM AUTHOR]

Radiation induced soft errors impact memory circuits and their response gets transposed or disturbed which makes it crucial to protect the memory unit. Radiation-immune memory devices have extensive applications in space, biomedical, smart devices, and wearable devices. A radiation hardened by design circuit using Dual Interlocked Storage Cell (DICE) is implemented with varied transistor sizing to propose the design that has optimum performance and minimum power dissipation. The design is tested for Single Event Upsets using the double exponential current model for current source of maximum amplitude 1 A. The proposed design is validated using Cadence Virtuoso version IC 6.1.5 at 180 nm CMOS technology node with variation of ± 10% of VDD = 1.8 V. The sensitivity of the circuit to process, voltage and temperature variations are shown with the help of Monte Carlo simulations. Various iterations performed during simulations make the proposed circuit suitable for use in critical applications. [ABSTRACT FROM AUTHOR]

In memory semiconductors such as a static random access memory (SRAM), a common problem is soft errors under radiation environment. These soft errors cause bit flips, which are referred to as single event upsets (SEUs). Some radiation-hardened SRAM cells such as a Quatro SRAM, we-Quatro SRAM, and DICE SRAM cells have been reported for years. However, these designs have the disadvantage of taking up more area than a conventional 6T SRAM cell. Thus, we propose a radiation-hardened SRAM cell design that we named capacitor-static random access memory (C-SRAM) without area overhead. The C-SRAM is formed by simply adding a capacitor to the conventional 6T SRAM. It was designed to mitigate the radiation effect using the conservation law of electrical charge. Moreover, it has the same cell size as the conventional 6T SRAM cell. Its static noise margins (SNMs), which are indicators of operational stability, are equal to the conventional 6T SRAM values of 530 mV, 220 mV, and 860 mV in hold, read, and write modes, respectively. The results of the SEU simulation test showed that it had 4.761 times better flipping tolerance than the conventional 6T SRAM with a charge value of 247.494 fC. In addition, irradiation experiments also confirmed that the C-SRAM cell was more tolerant than the 6T SRAM cell. The conventional 6T SRAM and C-SRAM were fabricated using a standard 0.18 μm CMOS process.

As the CMOS process continues to decrease in size, the latch becomes increasingly vulnerable to the triple-node-upset (TNU), leading to a decrease in circuit reliability in harsh radiation environments. In this paper, a low-cost TNU self-recovery latch (LCTR) is proposed, which is based on one PMOS and two NMOS (1P2N) inverters and C-elements (CEs) forming a multi-level feedback loop. Due to the error interception function of these fundamental elements, the proposed latch completely realizes TNU self-recovery capability. Then the simulated tests are used for comparing the overhead of the LCTR latch and the other two typical TNU self-recoverable latches. The results reveal that the LCTR latch decreases power consumption by 56.98%, delay by 30.08%, area by 21.25% and PDP by 70.77%, respectively. Moreover, the LCTR latch is moderately sensitive to the variation of process, voltage and temperature (PVT). [ABSTRACT FROM AUTHOR]

The problem of soft errors in the hardware implementation of Spiking Neural Networks (SNN) has always been a challenge. SNNs, unlike traditional deep learning networks, simulate the temporal dynamic behavior of biological neurons and emit spikes when a specific threshold is reached. In recent years, the hardware implementation of SNNs has shown great potential in performing efficient and low-power tasks, but as technology nodes shrink and integrated circuit complexity increases, soft errors become a key challenge. To this end, we propose a novel approach based on input and weight analysis, through specific algorithms at the hardware level, to significantly reduce the probability of soft errors affecting the results. In terms of training accuracy, our method maintains a high accuracy under various voltage fluctuation conditions, demonstrating its superior robustness. [ABSTRACT FROM AUTHOR]

Summary: Static Random Access Memory (SRAM) is vital in aerospace applications, but it may experience soft errors in strong radiation environments. This paper proposes a reconfigurable radiation SRAM with two operating modes catering to different environmental requirements: (1) traditional triple modular redundancy mode used when the radiation environment is strong and (2) SRAM cell expansion mode used when the radiation is not very strong. For example, when the memory capacity of a single module is 8 k, the memory capacity is 8 k in traditional triple modular redundancy mode, but it can be tripled to 24 K in extended mode. As can be obviously seen, this design can adjust the size according to the needs. In SRAM cell expansion mode, the proposed 14T SRAM cell enables the memory to maintain radiation resistance. Compared with DICE, RHBD‐12T, and WHIT, the read speed is improved by 3.8%, 5.7%, and 11.5% respectively, but compared with WE‐QUATRO, the read speed is reduced by 1.9%. The hold static noise margin is 1.378 times than DICE, 1.201 times than WE‐QUATRO, 1.045 times than RHBD‐12T, and 1.14 times than WHIT, respectively. The proposed 14T cell in this paper exhibits the highest critical charge value compared with the other cells. Combined with the expansion mode of the reconfiguration design, it shows great stability. [ABSTRACT FROM AUTHOR]

Numerous soft faults in SRAM memory emerge as technological innovations scales down, resulting in single and several cell upsets. The increased use of transistors in space applications has rendered semiconductor devices more vulnerable to soft errors caused by harm from radiation. A single event upset (SEU) is occurring whenever a soft error produces a tiny bit flipped in a storage device. Because SEU faults affect system performance, they must be addressed as soon as possible. Error-correcting codes, like the method known as (7,4) hamming codes, were devised and their decoding and encoding procedures were verified. It also used to detect single errors that can be fixed. It also helps detect double errors, SECDED however repair of double errors is tough. The decoding and encoding techniques of these approaches were investigated, and all computational findings had been verified and executed in a Xilinx NEXYS 4 DDR FPGA board. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. [ABSTRACT FROM AUTHOR]

The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C2P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C2N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C2P-C2N, DMR-C2P and DMR-C2N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C2N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS technology, single-event multi-node upsets (MNU) induced by charge sharing has continued to occur in latches when hit by high-energy particles. This paper presents a quadruple-node upset (QNU) tolerant latch design (referred to as P-DICE latch) to achieve both high reliability and low area overhead. The P-DICE latch takes advantage of the error-blocking properties of Cross-Coupled Element and C Element to tolerate QNU, and achieves 100% self-recovery of SNU and DNU. Compared with previous eight MNU hardened latches, the P-DICE latch has the lowest overhead in terms of area, area-power-delay product (APDP), and area-power-delay soft error rate ratio product (APDSP), and has the highest critical charge. Moreover, the proposed P-DICE latch can tolerate QNU caused by high-energy particles to ensure the reliability of the circuit. Compared with eight MNU hardened latches, the proposed P-DICE latch achieves 24.58% reduction in area, 33.05% reduction in power, 17.19% reduction in delay, 48.29% reduction in area-power-delay product, 61.60% reduction in APDSP, and 142.82% improvement in critical charge on average. [ABSTRACT FROM AUTHOR]

Introduction: While carbon ion radiotherapy is highly effective in cancer treatment, it has a high risk of causing soft error, which leads to malfunctions in cardiac implantable electrical devices (CIEDs). To predict the risk of malfunction prior to treatment, it is necessary to measure the reaction cross-sections and contributions to the soft error of secondary particles generated during treatments. Methods: A field-programmable gate array was used instead of CIEDs to measure soft errors by varying the energy spectrum of secondary particles. Results and discussion: The reaction cross-sections measured for each secondary particle were 3.0 × 10−9, 2.0 × 10−9, 1.3 × 10−8, and 1.5 × 10−8 [cm2/Mb] for thermal neutrons, intermediate-energy neutrons, high-energy neutrons above 10 MeV, and protons, respectively. The contribution of high-energy neutrons was the largest among them. Our study indicates that to reduce the risk of soft errors, secure distance and appropriate irradiation directions are necessary.

In this study, single-event transient (SET) characteristics in tunneling-based ternary complementary MOS device (T-CMOS) with gate-all-around structure (i.e., nanosheet FET) were analyzed for the first time. For low power computing systems, the transition from binary to ternary logic systems has been proposed as a solution to surmount the power density limitations inherent in conventional CMOS technology and to enhance their integration capabilities. As a part of this exploration, tunneling-based T-CMOS technologies have been extensively investigated. However, the susceptibility of those T-CMOS devices to radiation-induced effects has remained largely unexplored. Therefore, we evaluated soft error effects by observing SETs induced by heavy-ion effects in the T-CMOS inverters using 3D TCAD simulation. To clearly understand electrical characteristics related to SET effects for ternary logic system, the binary CMOS (B-CMOS) inverter was used as a reference. Then, it was revealed that the T-CMOS inverter is more vulnerable to heavy-ion effects, especially for $V_{\mathrm {OUT}} = {MID}_{\mathrm {TERNARY}}$ state, compared to the B-CMOS inverter. This is because of smaller state margin as well as lower current drivability by implementing three states. Also, SET characteristics were evaluated with variations in ground plane doping concentrations ( $N_{\mathrm {GP}}$ s), which is a key process parameter related to ${MID}_{\mathrm {TERNARY}}$ state by tunneling components. Then, it was confirmed that higher $N_{\mathrm {GP}}$ makes recovery process faster, resulting in mitigating soft errors. From these results, it would be very helpful to get valuable insights for the design of the T-CMOS inverter in terms of soft errors.

With the development of semiconductor technology, the size of transistors continues to shrink. In complex radiation environments in aerospace and other fields, small-sized circuits are more prone to soft error (SE). Currently, single-node upset (SNU), double-node upset (DNU) and triple-node upset (TNU) caused by SE are relatively common. TNU’s solution is not yet fully mature. A novel and low-cost TNU self-recoverable latch (named NLCTNURL) was designed which is resistant to harsh radiation effects. When analyzing circuit resiliency, a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs. Simulation results show that the latch has full TNU self-recovery. A comparative analysis was conducted on seven latches related to TNU. Besides, a comprehensive index combining delay, power, area and self-recovery—DPAN index was proposed, and all eight types of latches from the perspectives of delay, power, area, and DPAN index were analyzed and compared. The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable, NLCTNURL is reduced by 68.23% and 57.46% respectively from the perspective of delay. From the perspective of power, NLCTNURL is reduced by 72.84% and 74.19%, respectively. From the area perspective, NLCTNURL is reduced by about 28.57% and 53.13%, respectively. From the DPAN index perspective, NLCTNURL is reduced by about 93.12% and 97.31%. The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

Traditionally, studies have primarily focused on single event effects in aerospace electronics. However, current research has confirmed that atmospheric neutrons can also induce single event effects in China's advanced technology relay protection devices. Spallation neutron irradiation tests on a Loongson 2K1000 system-on-chip based relay protection device have revealed soft errors, including abnormal sampling, refusal of operation and interlock in the relay protection device. Given the absence of standardized evaluation methods for single event effects on relay protection devices, the following research emphasizes the use of Monte Carlo simulation and software fault injection. Various types of single event upsets, such as single bit upsets, dual bit upsets, and even eight bit upsets, were observed in Monte Carlo simulations where atmospheric neutrons hit the chip from different directions (top and bottom). The simulation results indicated that the single event effect sensitivity of the relay protection device was similar whether the neutron hit from the top or the bottom. Through software fault injection, the study also identified soft errors caused by neutron induced single event upsets on the Loongson 2K1000 system, including failure to execute, system halt, time out, and error result. And the soft error number of system halts and error results exceeded that of time outs and failures to execute in all three tested programs. This research represents a preliminary assessment of single event effects on relay protection devices and is expected to provide valuable insights for evaluating the reliability of advanced technology relay protection devices. [ABSTRACT FROM AUTHOR]

The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to failures. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to soft errors than synchronous counterparts. Duplicating ST channels instead of tripling reduces the failure-tolerant ST circuit's hardware redundancy and retains its reliability in higher level compared to synchronous counterparts. [ABSTRACT FROM AUTHOR]

The high energy particles in the space environment will perturb integrated circuits, resulting in system errors or even failures, which is also known as single event effects (SEE). To ensure the normal operation of space systems, it is first necessary to detect these errors. However, detection algorithms also bring additional overhead to the system and reduce its performance. Therefore, we aim to find a trade-off between reliability and performance. To this end, we propose a quantitative evaluation model for detection methods that evaluates the reliability gain of different detection methods under the same overhead. Our method allocates the optimal detection method to the corresponding code segment based on the quantitative results, thereby achieving a trade-off between reliability and performance. Experimental results show that the average energy efficiency of our trade-off method is 91.34%, which is 21.49% higher than the other methods. [ABSTRACT FROM AUTHOR]

Soft errors are the most common aspect of errors that are incurred in the memory devices during transmission. The common and fundamental reason of these soft errors is radiation that produces leakage of current and results in misleading information which is sent to various transmission stations via satellite and microwave communication. In this paper, the real-time embedded system is designed and implemented to mitigate the soft error using hybrid Hamming code. The work also develops the hardware system for soft error mitigation. The designed system is compared with the other coding schemes that are commonly available for error mitigation. The performance of real-time embedded system for soft error mitigation is carried out using signal-to-noise ratio and other performance metrics. The timing diagram analysis is the key metrics of the paper that defined the performance of the designed soft error mitigation design using the proposed technique. Furthermore, the results of the designed systems are demonstrated using bit error probability, Pb and channel symbol error probability (CSEP). The impact of the designed system will be that from now onwards using the proposed system, the soft error produced due to radiation and other reasons would not affect too much on transmission and reception of important data via satellite and microwave communication. [ABSTRACT FROM AUTHOR]

With aggressive technology scaling, soft errors have become a major threat in modern computing systems. Several techniques have been proposed in the literature and implemented in actual devices as countermeasures to this problem. However, their effectiveness in ensuring error-free computing cannot be ascertained without an accurate reliability estimation methodology. This can be achieved by using the vulnerability metric: the probability of system failure as a function of the time the program data are exposed to transient faults. In this work, we present a gemV-tool, a comprehensive toolset for estimating system vulnerability, based on the cycle-accurate gem5 simulator. The three main characteristics of the gemV-tool are: (i) fine-grained modeling: vulnerability modeling at a fine-grained granularity through the use of RTL abstraction; (ii) accurate modeling: accurate vulnerability calculation of speculatively executed instructions; and (iii) comprehensive modeling: vulnerability estimation of all the sequential elements in the out-of-order processor core. We validated our vulnerability models through extensive fault injection campaigns with <3% correlation error and 90% statistical confidence. Using the gemV-tool, we made the following observations: (i) the vulnerability of two microarchitectural configurations with similar performance can differ by 82%; (ii) the vulnerability of a processor can vary by more than 10×, depending on the implemented algorithm; and (iii) the vulnerability of each component in the processor varies significantly, depending on the ISA of the processor. [ABSTRACT FROM AUTHOR]

Summary: As the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations. [ABSTRACT FROM AUTHOR]

A soft error in cellular automata (CA) is a temporal miss mapping of the local function in a cell. Because the error is temporal, caused by noise, etc, the cell works correctly in the next steps. In this paper we propose a method (or an algorithm) which converts any CA solving firing squad synchronization problem (FSSP) to new CA such that the CA recover one soft error if the error makes an undefined domain of the local function. The method first alters the local function to produce a reset state if the domain is undefined. Then the reset state propagates to left and right making any states to the soldiers. Once the reset state reaches to the left boundary, the state of the general is produced and FSSP restarts. It is proved that the reset and retry actions eventually recovers the soft error and achieves the synchronization. [ABSTRACT FROM AUTHOR]

Networks-on-Chip (NoC) has become the standard paradigm for interconnect networks in multi-core processors. However, as the power supply voltage gradually decreases and the process size is reduced, the probability of soft errors in NoC increases. Error correction codes are commonly used in NoC router designs to tolerate soft errors. However, traditional router designs often only use Hamming codes for error correction, which has the problem of insufficient error correction capability, despite its simple design structure. This paper proposes a hybrid-hardening NoC router design based on error correction codes. The core idea of this design is to adopt different fault-tolerant code designs based on the importance of information bits, thus achieving a balance between router reliability and fault-tolerant overhead. Experimental results show that our design improves system reliability compared to the baseline design under synthetic traffic and PARSEC benchmark, and the hardware synthesis results also show that this design can shorten the critical path delay by 4%. [ABSTRACT FROM AUTHOR]

The multiple-node upset (MNU) phenomenon caused by charge sharing increases rapidly in advanced nano-scale latches, making it more critical to design hardened latches for MNU. This paper proposed a low overhead quadruple-node upset self-recoverable latch based on a triple-mode redundancy latch named LQNTL, which consists of three modules with data feedback interlocking within each module to achieve high reliability. Simulation results show that the proposed LQNTL reduces power consumption, delay, PDP, and area by 69.76%, 6.35%, 71.68%, and 10%, respectively, compared to the latest soft-error tolerant latch of the same fault tolerance. The analysis of PVT variation shows that the LQNTL is more stable for the process corner, supply voltage, and temperature variations. • In this paper, a low overhead QNU self-recoverable latch, LQNTL, based on triple-mode redundancy, is proposed to provide complete QNU resilience while maintaining the minimum cost in terms of PDP. • The HSPICE simulation under the 32 nm PTM shows the proposed structure fully tolerates the QNU and is QNU self-recoverable. • PVT variation analysis indicates that LQNTL has stability on delay and power consumption. • Compared with the recent QNU self-recoverable latch named QNURL, LQNTL reduces power consumption, delay, PDP, and area overhead by 69.76%, 6.35%, 71.68%, and 10%, respectively. [ABSTRACT FROM AUTHOR]

Downscaling threatens the designers invested in integrity and error mitigation against soft errors. This study formulated the probability of soft error changing the logic state of a Differential Logic with an Inverter Latch (DIL). Using Cadence Virtuoso, current pulses were injected into various nodes in stages until a logic flip was instigated. The voltage and temperature parameters were increased to observe the current level changes over time. The critical charge from each stage was obtained, and a method to formulate the probability of each instance was developed. The voltage produced a higher effect of the change to the critical charge of any instance as compared to temperature. The findings revealed that the N-channel metal-oxide semiconductor (NMOS) drain is more vulnerable to temperature and voltage variation than P-channel metal-oxide semiconductor (PMOS). [ABSTRACT FROM AUTHOR]

The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor's pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%. [ABSTRACT FROM AUTHOR]

Although a 6-MV X-ray beam is employed clinically as a non-neutron-producing beam, no studies have reported how few neutrons are produced from a 6-MV beam. This study aimed to theoretically deduce the neutron dose from a 6-MV beam using Monte Carlo simulations for the notification of safety and risk in radiotherapy. Nuclei from a nuclear database with neutron separation energies below 6 MeV were surveyed, suggesting that the certain content of 2H in the human body may result in some contribution. Thus, Monte Carlo calculation considering 2H in a phantom was performed. The calculation suggested that the distribution of the neutron dose from a 6-MV beam consisted of two components: one had neutrons from 2H concentrated within an irradiation field, and the other had those due to other elements such as 183W spreading from a gantry head to a treatment room. Although uncertainty owing to the normalization factor of the Monte Carlo calculations was a factor of three, the neutron doses at distances of 0 and 50 cm from an irradiation field were calculated as 27 and 1.5 nSv/MU, respectively, under intensity-modulated radiotherapy (IMRT) or volumetric modulated arc therapy (VMAT). The calculations suggest that neutrons produced by a 6-MV beam are approximately 70 and 20 times safer than those by a 10-MV beam in the case of IMRT/VMAT and total body irradiation, respectively. Thus, this study theoretically reported the approximate number of neutrons delivered by a 6-MV beam for the first time. [ABSTRACT FROM AUTHOR]

As microelectronics technology has continued to progress, the multiple-node upset (MNU), caused by the single-particle and charge-sharing effects, has gradually become one of the most important factors affecting chip reliability. To enhance the reliability of these latches, a TNU completely self-recoverable (TNUCR) latch is first proposed in this paper, mainly consisting of five interlocked four-input C-elements (CEs) and inverters, which are cross-connected to form a ring. For any individual CE, due to the presence of a feedback loop, the value of its output is inverted and becomes the input to the other four CEs, which enables the latch to self-recover from all TNUs. Second, we propose an improved low-cost TNU completely self-recoverable (LCTNUCR) latch. This latch replaces the inverter with a four-input CE and uses a high-speed transmission path (HSTP), which can more rapidly self-recover from all TNU situations. It is demonstrated by experimental results that the two proposed latches are not only TNU tolerant but also TNU self-recoverable. Moreover, based on special design and the adoption of clock gating techniques, the proposed TNUCR latch has a delay-power-area product reduction of about 41.05%, while the proposed LCTNUCR latch has a DPAP reduction of about 71.30% compared to the latest representative TNU hardened latch. • Proposed TNUCR and LCTNUCR with SNU recoverability, DNU recoverability and TNU recoverability, and have low DPAP. • The use of high-speed transmission paths effectively decreases the transmission delay. • The use of CG technology effectively reduces current contention and lowers power consumption. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose.

Soft error can lead to silent data corruption（SDC） that affects the reliability of computer system. One prerequisite to prevent SDC is calculating the vulnerability factor of the target program. Traditional methods were not capable of extracting program semantics, which led to inferior of the fault propagation mechanism. This paper proposed a program vulnerability factor evaluation method based on graph attention network（EpicGNN）. EpicGNN used structural multi-head self-attention to quantify importance of fault propagations from one node to it’s neighbors and further to graph, different types of edges represent different instruction relationships. Then aggregated the information of node and graph to update the representation. It applied a regression model to predict vulnerability factor. Experimental on spec2000, spec2006, rodinia and other datasets achieved 0.037 ～ 0.258 lower average absolute error compared with traditional methods. Moreover, EpicGNN was validated to obtain good performance on unseen graphs. [ABSTRACT FROM AUTHOR]

In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the '0' storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit. [ABSTRACT FROM AUTHOR]

Soft errors are transient errors caused by single-event effects (SEEs) resulting from a strike by high-energy particles acting on sensitive areas of integrated circuits. Soft errors frequently occur in the space environment, adversely affecting the reliability of aerospace-based computing. A recovery process is launched to recover the program when soft errors are detected. A periodic checkpointing recovery approach is widely utilized to prevent soft errors. However, this approach does not consider the detector locations, resulting in a large time overhead. This paper proposes a checkpointing recovery approach for soft errors based on detector locations called DLCKPT. DLCKPT reduces the time overhead by considering detector locations. The experimental results show that the percentage decrease in the time overhead between the DLCKPT and the periodic checkpointing recovery approach is 13.4%. The average recovery rate and average space overhead are 99.3% and 44.4% for the periodic checkpointing recovery approach and 99.4% and 34.6% for the DLCKPT. These results show that the DLCKPT and the periodic checkpointing recovery approach produce comparable results for the recovery rate. The DLCKPT has a lower time overhead and a slightly lower space overhead than the periodic checkpointing recovery approach, demonstrating its effectiveness. [ABSTRACT FROM AUTHOR]

The aerospace environment contains extremely energetic particles that trigger single-event transients (SET), leading to single-event upsets (SEU) in the memory cell. An efficient SRAM cell must be designed to tolerate soft error to withstand the extreme environment. This paper proposes a highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. The proposed cell has better writability, and WSNM is 1.08 × higher than its counterpart We-Quatro SRAM cell. The read access time of the proposed SRAM cell is 0.96 × , 0.91 × , 0.99 × , 0.98 × smaller than 6T, Quatro, We-Quatro, and NQuatro SRAM cells, and 1.01 × higher than RHD12T cell, and the write delay of the proposed SRAM is 0.93 × , 0.46 × , 0.72 × , 0.41 × , 0.47 × , less than that of 6T, Quatro, We-Quatro, RHD12T, and NQuatro respectively. 2000 Monte Carlo simulation for power dissipation and upset margin reveals that the process variation has less impact on the proposed SRAM and 1.64 × better tolerance against logic flipping. Further, for the P-Quatro, the critical charge is 41.51 fC and is 2.05 × , 1.75 × , 1.93 × , and 1.48 × greater than Quatro, We-Quatro, RHD12T, and NQuatro memory cells. We conducted an assessment using an electrical quality matrix (EQM) that takes into account all performance parameters. The findings reveal that the EQM of the proposed cell surpasses that of the 6T, Quatro, We-Quatro, RHD12T, and NQuatro SRAM cells by factors of 0.82 × , 0.35 × , 0.49 × , 0.71 × , and 0.21 × , respectively. This indicates that the proposed cell demonstrates superior electrical quality across various metrics compared to the other SRAM cell designs evaluated. • A highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. • Using NMOS transistors instead of PMOS helps reduce charge sharing in the circuit, improving critical charge and reducing soft error upset probability. • The electrical quality matrix (EQM) of the proposed cell surpasses that of the 6T, Quatro, WeQuatro, RHD12T, and NQuatro SRAM cells. [ABSTRACT FROM AUTHOR]

In this paper, a soft error hardened circuit with the aim ofavoiding and detecting-correctingthe soft error strikesat the same timing phase is proposed for high-speed memory applications. The proposed design is completely immune to multiple soft errors occurring in any of the nodes. The avoidance part and detection-correction part are the two major parts that tolerate multiple particle strikes. The proposed design can detect and correct a single particle strike at single node and at multiple nodes.A set of simulations are made in CMOS technology to validate the proposed circuit in terms of delay, power, and area overheads which are the main requirements of VLSI design. Compared with other techniques it is shown that the proposed circuit achieves 1.124 μm power consumption, and142.68ps delay overheads. The work also investigates about Monte Carlo simulations along with the impact of process, voltage and temperature (PVT) variations and shows that the proposed circuit is highly reliable and less sensitive to soft errors compared with other existing soft error latches. [ABSTRACT FROM AUTHOR]

Summary: Over the past four decades, single event upset (SEU) and single event multiple node upset (SEMNU) have become the major issues in the memory area. Moreover, these upsets are prone to reliability issues in space, terrestrial, military, and medical applications. This article concisely reviews different researchers and academicians who proposed resilience techniques and methods to mitigate this upset mess. In addition, we also investigated the importance of QCrit and the impact of QCrit on device scaling parameters in upset mechanism, probability of memory failure, and the figure of metrics for the stability of memory cells. [ABSTRACT FROM AUTHOR]

Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant. [ABSTRACT FROM AUTHOR]

The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations. [ABSTRACT FROM AUTHOR]

This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 3D TCAD simulations have been performed to obtain a detailed map of the sensitivity areas in a full cell 6-T SRAM 22 nm bulk-FinFET process. The influence of the well depth on the charge collected by the drain devices of the SRAM cell has been studied, and it has been concluded that the collected charge can be reduced down to 300% simply by modifying the depth of the well, without affecting the performance of the cell. Different PTS layer depths have been analyzed in order to calculate which value minimizes the impact of the charge generated by an ion during its track along the FinFET body. The simulations carried out allow to conclude that the incorporation of a PTS layer not only reduces the leakage current, but also reduces the amount of charge, delivered by the ion, that reaches the drain region. Simulation results also show that the fraction of the charge generated by the ion impact, which is collected by the drain, mainly depends on the depth of the wells, whereas the PTS layer hardly modifies the collected charge.

The rapid transistor scaling and threshold voltage reduction pose several challenges such as high leakage current and reliability issues. These challenges also make VLSI circuits more susceptible to soft-errors, particularly when subjected to harsh environmental conditions. Hybrid spintronic/CMOS technology has emerged as one of the promising techniques to achieve low leakage power and non-volatility. Moreover, the spintronic memories are inherently resistant to the radiation effects such as heavy-ion irradiation and total ionizing dose. However, its CMOS peripheral circuitry is more susceptible to radiation-induced single-event upset (SEU) and double-node upset (DNU). In this paper, a new radiation-hardened read circuit for SOT magnetic random access memory (MRAM) on 45nm technology has been presented. The proposed circuit is highly resistant to all the probable SEUs and DNUs when compared to the previously reported designs. The results show that it can tolerate 4.5X, 11X, 9X, and 10.5X more critical charge as compared to the cross-coupled CMOS transistor, 11T, 13T, and 11T radiation hardened circuits, respectively. Moreover, the recovery time of the proposed circuit is improved by 20% when compared to cross-coupled CMOS transistor circuits.

Protecting cache memories against radiation-induced soft errors is critical in designing highly reliable processors. Dirty lines in write-back data caches are more critical, since the dirty lines have no backups in lower-level memory (LLM). This paper provides a write-buffer scheme for backing up dirty lines to protect cache memories based on the replication mechanism combined with interleaving parity check against multiple-bit errors. The write-buffer contains two same replication caches to replicate the dirty data from the original cache, and the two replication caches take turns to write the replicated data back to LLM during the free time when there is no access in LLM. In this way, the dirty data in original cache is backed up to LLM that can be used for error recovery, and meanwhile, spaces of the replication caches are released to replicate new dirty data; moreover, the writebacks of the replicated data can be performed in the background without extra clocks. Simulation results show that the proposed write-buffer scheme can provide a full protection for caches without degrading system performance, while it can improve the system performance by an average of 1.4% due to the background writebacks, and compared with state-of-the-art replication-based technique, it can increase the replication capability by 11.6% and save 6.2% energy consumption in case of the optimal configuration. It is superior to the existing techniques in terms of protection capability and system performance overhead.

As electronic devices technology scales down into the deep-submicron to achieve high-density, low power and high performance integrated circuits, multiple bit upsets by soft errors have become a major threat to on-chip memory systems. To address the soft error problem, single error correction, double error detection and double adjacent error correction (SEC–DED-DAEC) codes have been recently proposed. But these codes do not troubleshoot mis-correction problem. We propose the SEC-DED_DAEC code with without mis-correction. The decoder for proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the decoder can be employed on-chip memory system. [ABSTRACT FROM AUTHOR]

The adoption of RISC-V processors bloomed in recent years, mainly due to its open standard and free instruction set architecture. However, much remains to help software engineers deliver high-reliability and bug-free applications and systems based on RISC-V IP designs. This work proposes an early soft error reliability assessment of a RISC-V processor, extending the previously proposed SOFIA fault injection framework. Results from 850k fault injections show that choosing the compiler flag -O2 to optimize performance causes 96% more Hang failures than -O0. Software engineers must evaluate compilation parameters on a case-by-case basis to find the best balance between performance and reliability. This work helps software engineers develop fault-tolerant RISC-V-based systems and applications more efficiently. [ABSTRACT FROM AUTHOR]

Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches. [ABSTRACT FROM AUTHOR]

The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%.

Graphics processing units (GPUs) are widely used in general-purpose high-performance computing applications (i.e., GPGPUs), which require reliable execution in the presence of soft errors. To support massive thread-level parallelism, a sizeable register file is adopted in GPUs, which is highly vulnerable to soft errors. Although modern commercial GPUs provide single-error-correction double-error-detection (SEC-DED) error correction code (ECC) for the register file, it consumes a considerable amount of energy due to frequent register accesses and leakage power of ECC storage. In this article, we propose to leverage the error sensitivity of instructions, the duplicate characteristics of the same-named registers, and the error sensitivity of data bits to build a unified energy-efficient ECC mechanism for a GPGPUs register file (Eff-ECC), which consists of instruction-aware ECC (IA-ECC), duplication-aware ECC (DA-ECC), and bit-aware ECC (BA-ECC). Considering the error sensitivity of instructions, IA-ECC merely implements ECCs for the write registers of critical instructions. Observing the same-named registers across threads usually keeps the same data, DA-ECC avoids unnecessary ECC generation and verification for duplicate register values. Leveraging the inherent error-tolerance features of the program, BA-ECC merely protects significant bits of registers to combat the crucial error. Experimental results demonstrate that Eff-ECC tremendously reduces 86.46% energy consumption of traditional SEC-DED ECC. [ABSTRACT FROM AUTHOR]

In an IC used for safety-critical applications, the Fault and soft-error tolerance (or FET) is often desirable. In this work, we consider a graceful degradation scheme, as the second line of defense, for a FET delay-locked loop (DLL) we have recently developed. By doing so, a FET DLL will not operate blindly when its tolerance to faults or soft errors has been degraded. This is achieved by incorporating a novel low-cost excessive phase-error monitor. Any excessive phase error beyond a prelearned phase-error tolerance range will trigger an alarm of failure. This monitor can also be used to support an online test for deciding whether there is a faulty module in our TMR-based FET DLL at any given time. We have implemented the proposed scheme in a 90-nm CMOS process. The results show that the area of this excessive phase error monitor is as small as 60 $\mu \text{m}\,\,\times $ 60 $\mu \text{m}\,\,=$ 0.0036 mm2, or only 4.12% of the entire FET DLL. [ABSTRACT FROM AUTHOR]

Soft errors are increasing in computer systems due to shrinking feature sizes. Soft errors can induce incorrect outputs, also called silent data corruption (SDC), which raises no warnings in the system and hence is difficult to detect. To prevent SDC effectively, protection techniques require a fine-grained profiling of SDC-prone instructions, which is often obtained by applying machine learning models. However, these models rely on handcrafted features, and lack the ability to reason about SDC propagation, which leads to an inferior SDC prediction performance. We propose a novel Graph Attention neTwork to Predict SDC-prone instructions (GATPS). The GATPS representation is a heterogeneous graph with different types of edges to represent various instruction relations. By stacking layers in which nodes are able to attend over their neighborhoods' features, GATPS automatically captures the structural features that contribute to SDC propagation. The attention mechanism is applied to compute the importance values to the neighboring nodes, which quantifies the fault effect on the neighboring nodes. Moreover, the inductive model of GATPS can be applied to unseen programs without retraining, and it requires no fault injection information of the target program. Experiments revealed GATPS achieved a 34% higher F1 score compared to the baseline method and a 40-fold speedup compared to the fault injection approach. [ABSTRACT FROM AUTHOR]

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

As the safety-critical applications (e.g., automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects five benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions. [ABSTRACT FROM AUTHOR]

Due to advances in digital transformation, it is important to take measures against soft errors caused by cosmic rays to maintain a safe and secure network. This article explains the latest research results on soft errors from NTT laboratories, commercialization of soft-error test technology, and standardization activities in the International Telecommunication Union - Telecommunication Standardization Sector (ITU-T). [ABSTRACT FROM AUTHOR]