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This study explores the feasibility of precisely tuning the resistive switching behavior of Au/BiFeO 3 /Pt/Ti/SiO 2 /Si memristors through controlled modulation of laser energy density during pulsed laser deposition (PLD). By systematically reducing the laser energy density within the fabrication process, notable alterations in the properties of the BiFeO 3 (BFO) thin film are observed. As the laser energy density decreases, the grain size in the BFO film and the thickness of the film decrease. Furthermore, we obtain the minute structural variations in response to the diverse laser energy densities employed during the deposition process. Energy-dispersive x-ray spectroscopy analysis is employed to investigate the distribution of Ti 4 + ions within the BFO thin film. The reduction in the grain size and film thickness, along with the prominent nucleation of specifically oriented grains, and the diffusion of Ti 4 + ions, lead to the BFO memristor fabricated with a lower laser energy density having more grain boundaries and a shortened conduction path (grain boundary) in the thickness direction. Consequently, the enhanced movement of oxygen vacancies facilitates their preferential accumulation along the grain boundaries within the BFO layer, resulting in an augmented on/off ratio, rectification factor, and set current in the devices. Overall, our findings explain the significant influence of laser energy density in PLD on the microstructure and electrical properties of BFO thin films. Particularly, the lower energy densities are employed to improve electrical characteristics. This research not only enhances our fundamental understanding but also provides valuable insights into optimizing BFO memristors for reliable, robust, and practical applications. [ABSTRACT FROM AUTHOR]

The thirst for more efficient computational paradigms has reignited interest in computation in memory (CIM), a burgeoning topic that pivots on the strengths of more versatile logic systems. Surging ahead in this innovative milieu, multi-valued logic systems have been identified as possessing the potential to amplify storage density and computation efficacy. Notably, ternary logic has attracted widespread research owing to its relatively lower computational and storage complexity, offering a promising alternative to the traditional binary logic computation. This study provides insight into the feasibility of ternary logic in the CIM domain using resistive random-access memory (ReRAM) devices. Its multi-level programming capability making it an ideal conduit for the integration of ternary logic. We focus on ternary Łukasiewicz logic because its computational characteristics are highly suitable for mapping logic values with input and output signals. This approach is characterized by voltage-reading-based output for ease of subsequent utilization and computation and validated in 1T1R crossbar arrays in an integrated ReRAM chip (Memory Advanced Demonstrator 200 mm). In addition, the effect of variability of memristive devices on logical computation and the potential for parallel operation are also investigated. This article is part of the theme issue 'Emerging technologies for future secure computing platforms'. [ABSTRACT FROM AUTHOR]

Memristive technology mitigates the memory wall issue in von Neumann architectures by enabling in-memory data processing. Unlike traditional complementary metal-oxide semiconductor (CMOS) technology, memristors provide a new paradigm for implementing cryptographic functions and security considerations. While prior research explores memristors for cryptographic functions and side-channel attack vulnerabilities, our study uniquely addresses memristor-oriented countermeasures. We review different memristive crossbar configurations, implement a four-bit S-box cryptographic function, and analyse memristor-oriented hiding and masking techniques using a self-rectifying passive crossbar. Our findings confirm the efficacy of memristor-oriented hiding techniques but highlight limitations in memristor-oriented masked dual-rail pre-charge logic (MDPL) masking methods. Effective MDPL masking depends on specific power consumption conditions, i.e. the power profile of input data '01' and '10' are not clearly distinguishable from '00' and '11', which, however, are not satisfied across various memristive logic families. Despite passing t-tests, xor4Sbox with CRS-based MDPL masking failed stochastic approaches owing to power consumption differences. Our study prioritizes memristor-oriented countermeasures, advancing the understanding of challenges and opportunities in memristive technology for cryptographic functions. This article is part of the theme issue 'Emerging technologies for future secure computing platforms'. [ABSTRACT FROM AUTHOR]

Self-rectifying analog memristors have emerged as promising components for neuromorphic computing systems due to their inherent rectifying behavior and analog resistance states. Among these devices, BiFeO 3 (BFO) memristors have shown exceptional performance, attributed to the accumulation and migration of oxygen vacancy ( V o · · ). However, the movement of V o · · within the structure of the device presents challenges in optimizing their performance. To address this, the insertion of an interfacial layer has been proposed as a strategy to change the movement of V o · · and enhance the behavior of memristor. In this study, we investigate the optimization of self-rectifying analog memristors by inserting an interfacial layer in BFO memristors. The more significant nonlinearity in high resistance state branch we observed in the current–voltage relationship leads to better rectifying behavior and a larger on/off ratio at room temperature, which indicates that the interfacial layer improves rectifying behavior. Moreover, we propose a model based on the modulation of the interfacial barrier to elucidate the impact of the interfacial layer on the BFO memristor. These findings provide insight into the design principles for optimizing self-rectifying analog memristors, with potential applications in neuromorphic computing. [ABSTRACT FROM AUTHOR]

This study explores memristor-based true random number generators (TRNGs) through their evolution and optimization, stemming from the concept of memristors first introduced by Leon Chua in 1971 and realized in 2008. We will consider memristor TRNGs coming from various entropy sources for producing high-quality random numbers. However, we must take into account both their strengths and weaknesses. The comparison with CMOS-based TRNGs will serve as an illustration that memristor TRNGs stand out due to their simpler circuits and lower power consumption— thus leading us into a case study involving electroless YMnO3 (YMO) memristors as TRNG entropy sources that demonstrate good security properties by being able to produce unpredictable random numbers effectively. The end of our analysis sees us pinpointing challenges: post-processing algorithm optimization coupled with ensuring reliability over time for memristor-based TRNGs aimed at next-generation security applications. [ABSTRACT FROM AUTHOR]

Memristors, since their inception, have demonstrated remarkable characteristics, notably the exceptional reconfigurability of their memory. This study delves into electroforming-free YMnO 3 (YMO)-based resistive switches, emphasizing the reconfigurable memory effect in multiferroic YMO thin films with metallically conducting electrodes and their pivotal role in achieving adaptable frequency responses in impedance circuits consisting of reconfigurable YMO-based resistive switches and no reconfigurable passive elements, e.g., inductors and capacitors. The multiferroic YMO possesses a network of charged domain walls which can be reconfigured by a time-dependent voltage applied between the metallically conducting electrodes. Through experimental demonstrations, this study scrutinizes the impedance response not only for individual switch devices but also for impedance circuitry based on YMO resistive switches in both low- and high-resistance states, interfacing with capacitors and inductors in parallel and series configurations. Scrutinized Nyquist plots visually capture the intricate dynamics of impedance circuitry, revealing the potential of electroforming-free YMO resistive switches in finely tuning frequency responses within impedance circuits. This adaptability, rooted in the unique properties of YMO, signifies a paradigm shift heralding the advent of advanced and flexible electronic technologies. [ABSTRACT FROM AUTHOR]

This review provides a comprehensive examination of the state-of-the-art research on resistive switching (RS) in BiFeO3 (BFO)-based memristive devices. By exploring possible fabrication techniques for preparing the functional BFO layers in memristive devices, the constructed lattice systems and corresponding crystal types responsible for RS behaviors in BFO-based memristive devices are analyzed. The physical mechanisms underlying RS in BFO-based memristive devices, i.e., ferroelectricity and valence change memory, are thoroughly reviewed, and the impact of various effects such as the doping effect, especially in the BFO layer, is evaluated. Finally, this review provides the applications of BFO devices and discusses the valid criteria for evaluating the energy consumption in RS and potential optimization techniques for memristive devices. [ABSTRACT FROM AUTHOR]

Emerging brain-inspired neuromorphic computing paradigms require devices that can emulate the complete functionality of biological synapses upon different neuronal activities in order to process big data flows in an efficient and cognitive manner while being robust against any noisy input. The memristive device has been proposed as a promising candidate for emulating artificial synapses due to their complex multilevel and dynamical plastic behaviors. In this work, we exploit ultrastable analog BiFeO3 (BFO)-based memristive devices for experimentally demonstrating that BFO artificial synapses support various long-term plastic functions, i.e., spike timing-dependent plasticity (STDP), cycle number-dependent plasticity (CNDP), and spiking rate-dependent plasticity (SRDP). The study on the impact of electrical stimuli in terms of pulse width and amplitude on STDP behaviors shows that their learning windows possess a wide range of timescale configurability, which can be a function of applied waveform. Moreover, beyond SRDP, the systematical and comparative study on generalized frequency-dependent plasticity (FDP) is carried out, which reveals for the first time that the ratio modulation between pulse width and pulse interval time within one spike cycle can result in both synaptic potentiation and depression effect within the same firing frequency. The impact of intrinsic neuronal noise on the STDP function of a single BFO artificial synapse can be neglected because thermal noise is two orders of magnitude smaller than the writing voltage and because the cycle-to-cycle variation of the current–voltage characteristics of a single BFO artificial synapses is small. However, extrinsic voltage fluctuations, e.g., in neural networks, cause a noisy input into the artificial synapses of the neural network. Here, the impact of extrinsic neuronal noise on the STDP function of a single BFO artificial synapse is analyzed in order to understand the robustness of plastic behavior in memristive artificial synapses against extrinsic noisy input. [ABSTRACT FROM AUTHOR]

Using two different types of impedance biochips (PS5 and BS5) with ring top electrodes, a distinct change of measured impedance has been detected after adding 1–5 µL (with dead or live Gram-positive Lysinibacillus sphaericus JG-A12 cells to 20 µL DI water inside the ring top electrode. We relate observed change of measured impedance to change of membrane potential of L. sphaericus JG-A12 cells. In contrast to impedance measurements, optical density (OD) measurements cannot be used to distinguish between dead and live cells. Dead L. sphaericus JG-A12 cells have been obtained by adding 0.02 mg/mL of the antibiotics tetracycline and 0.1 mg/mL chloramphenicol to a batch with OD0.5 and by incubation for 24 h, 30 °C, 120 rpm in the dark. For impedance measurements, we have used batches with a cell density of 25.5 × 108 cells/mL (OD8.5) and 270.0 × 108 cells/mL (OD90.0). The impedance biochip PS5 can be used to detect the more resistive and less capacitive live L. sphaericus JG-A12 cells. Also, the impedance biochip BS5 can be used to detect the less resistive and more capacitive dead L. sphaericus JG-A12 cells. An outlook on the application of the impedance biochips for high-throughput drug screening, e.g., against multi-drug-resistant Gram-positive bacteria, is given. [ABSTRACT FROM AUTHOR]