Search

Hydraulic solenoid valves (HSVs) are widely used for fluid control in industrial applications. Like other mechanical parts, HSVs deteriorate and faults occur during their use in industrial settings. Although several prior fault-diagnosis methods have been proposed to detect these faults, previous studies have not considered the actual implementation of the methods on the controller. Thus, to ensure reliable operation of HSVs in the field, this research paper presents an innovative HSV controller design that is able to process the proposed fault-diagnosis algorithm. In the proposed work, the hardware is designed to transmit and receive signals and data for the valve-diagnosis algorithm. For the software, an architecture is proposed to enable the fault-diagnosis algorithm to be processed in a conventional microprocessor. In this research, the proposed controller design was built and tested on an actual hydraulic system. The results show that the proposed fault-diagnosis algorithm has been successfully embedded in the microcontroller. [ABSTRACT FROM AUTHOR]

The work presented in this paper regards the improvement of a housekeeping system for data acquisition of a suborbital vehicle (VIRIATO rocket or launcher). The specifications regarding the vehicle are presented and hardware is chosen accordingly, considering commercial off-the-shelf components. Mechanical and thermal simulations are performed regarding the designed system and a physical prototype is manufactured, assembled and programmed. Functional and field test results resorting to unmanned aerial vehicles, as well as the system's integration within VIRIATO project's mock-up vehicle, are presented. These tests demonstrate the viability of this system as an independent data acquisition system, and simulation results show that commercial off-the-shelf components have the capability of surviving expected launch environments. [ABSTRACT FROM AUTHOR]

In mammalian cells, primary miRNAs are cleaved at their hairpin structures by the Microprocessor complex, whose core is composed of DROSHA and DGCR8. Here, we show that 5′ flanking regions, resulting from Microprocessor cleavage, are targeted by the RNA exosome in mouse embryonic stem cells (mESCs). This is facilitated by a physical link between DGCR8 and the nuclear exosome targeting (NEXT) component ZCCHC8. Surprisingly, however, both biochemical and mutagenesis studies demonstrate that a variant NEXT complex, containing the RNA helicase MTR4 but devoid of the RNA-binding protein RBM7, is the active entity. This Microprocessor-NEXT variant also targets stem-loop-containing RNAs expressed from other genomic regions, such as enhancers. By contrast, Microprocessor does not contribute to the turnover of less structured NEXT substrates. Our results therefore demonstrate that MTR4-ZCCHC8 can link to either RBM7 or DGCR8/DROSHA to target different RNA substrates depending on their structural context. [Display omitted] • A variant NEXT complex of MTR4 and ZCCHC8 interacts with the Microprocessor complex • RBM7 is absent from the variant NEXT (vNEXT) complex • vNEXT-Microprocessor targets 5' flanks of pre-miRNAs • Structured RNAs, independent of miRNAs, are targeted by vNEXT-Microprocessor Imamura et al. reveal a physical and functional link between the Microprocessor complex, responsible for pre-miRNA processing, and a variant NEXT complex, involved in RNA decay. Together, these complexes degrade the 5' flanks of pre-miRNAs and other stem-loop-containing RNAs. [ABSTRACT FROM AUTHOR]

MicroRNA (miRNA) biogenesis is initiated upon cleavage of a primary miRNA (pri-miRNA) hairpin by the Microprocessor (MP), composed of the Drosha RNase III enzyme and its partner DGCR8. Multiple pri-miRNA sequence motifs affect MP recognition, fidelity, and efficiency. Here, we performed cryoelectron microscopy (cryo-EM) and biochemical studies of several let-7 family pri-miRNAs in complex with human MP. We show that MP has the structural plasticity to accommodate a range of pri-miRNAs. These structures revealed key features of the 5′ UG sequence motif, more comprehensively represented as the "flipped U with paired N" (fUN) motif. Our analysis explains how cleavage of class-II pri-let-7 members harboring a bulged nucleotide generates a non-canonical precursor with a 1-nt 3′ overhang. Finally, the MP-SRSF3-pri-let-7f1 structure reveals how SRSF3 contributes to MP fidelity by interacting with the CNNC motif and Drosha's Piwi/Argonaute/Zwille (PAZ)-like domain. Overall, this study sheds light on the mechanisms for flexible recognition, accurate cleavage, and regulated processing of different pri-miRNAs by MP. [Display omitted] • The Microprocessor has the plasticity for accommodating a diversity of pri-miRNAs • RNA drives Microprocessor domain repositioning for pri-let-7 cleavage • The UG motif is redefined as a fUN motif for a comprehensive pri-miRNA classification • SRSF3 assists Drosha by positioning it at the basal junction of the pri-miRNA Garg et al. used cryo-EM to determine several structures of different pri-let-7 pri-miRNAs in complex with the Microprocessor, highlighting structural features important for flexible recognition, pri-miRNA cleavage, and cleavage regulation. The fUN structural motif and CNNC-SRSF3-assisted Drosha loading present insights applicable to the processing of hundreds of pri-miRNAs. [ABSTRACT FROM AUTHOR]

This study examines the efficiency of a microprocessor's cooling system and maintaining the optimal temperature of electronic components. To do this, experiments are carried out on the existing cooling system of the microprocessor with control of all main parameters, primarily such as the temperature and coolant flow, as well as the performance and temperature of the processor. Based on the data obtained, a mathematical model is built that describes the change in the microprocessor's power and allows us to calculate the temperatures and speeds of coolants, as well as obtain the most effective modes for the operation of the cooling system. The obtained experimental data and mathematical model make it possible to predict the required power of the cooling system and the operating parameters of microelectronic components, which is especially important when new generations of microprocessors with the highest performance appear. The data obtained also makes it possible to calculate parameters for existing processors in order to maximize the efficiency and reliability of their operation, which is also relevant for other electronic devices, in particular microcontrollers. [ABSTRACT FROM AUTHOR]

Electricity demand is rapidly increasing in many countries especially because of the increase in smart appliances, smart cities, and communities. The use of electricity ranges from agricultural load, to commercial and industrial load, and also residential load which account for the largest contributor to the increase in peak demand. Thus, residential consumers play a massive role in the national demand for electrical energy and power. The increased demand puts increasing pressure on the energy suppliers who force consumers to cope with short peaks. The need arises for an energy management technique to reduce energy consumption by allowing for consumer load control. The method explores using a Raspberry Pi to collect and evaluate the energy consumed over time and allow consumers access to directly control their home appliances. A more accurate load curve is deduced using the new readings gotten from the end-users. The data obtained from the proposed system is sent to a progressive web application that allows users manage their energy consumption. [ABSTRACT FROM AUTHOR]

A digitizer is considered one of the fundamental components of an earthquake monitoring system. In this paper, we design and implement a high accuracy seismic digitizer. The implemented digitizer consists of several blocks, i.e., the analog-to-digital converter (ADC), GPS receiver, and microprocessor. Three finite impulse response (FIR) filters are used to decimate the sampling rate of the input seismic data according to user needs. A graphical user interface (GUI) has been designed for enabling the user to monitor the seismic waveform in real time, and process and adjust the parameters of the acquisition unit. The system casing is designed to resist harsh conditions of the environment. The prototype can represent the three component sensors data in the standard MiniSEED format. The digitizer stream seismic data from the remote station to the main center is based on TCP/IP connection. This protocol ensures data transmission without any losses as long as the data still exist in the ring buffer. The prototype was calibrated by real field testing. The prototype digitizer is integrated with the Egyptian National Seismic Network (ENSN), where a commercial instrument is already installed. Case studies shows that, for the same event, the prototype station improves the solution of the ENSN by giving accurate timing and seismic event parameters. Field test results shows that the event arrival time and the amplitude are approximately the same between the prototype digitizer and the calibrated digitizer. Furthermore, the frequency contents are similar between the two digitizers. Therefore, the prototype digitizer captures the main seismic parameters accurately, irrespective of noise existence. [ABSTRACT FROM AUTHOR]

According to the World Health Organization, 430 million individuals, or more than 5% of the world's population, need hearing loss rehabilitation. They also estimate that by 2050, one in ten individuals, or over 700 million people, would suffer hearing loss, that is incapacitating. Despite these difficulties, technological developments have made it feasible to enhance these people's quality of life. The Real-time Smart Auditory Assistive Wearable (RESAAW), is a revolutionary gadget that aids people with hearing problems by employing omnidirectional microphones to record real-time surrounding noises. In the case of abrupt or harmful noises, the gadget gives the user tactile input while employing advanced digital signal processing and machine learning models to distinguish vital sounds from background noise. The goal of RESAAW is to use 4 omnidirectional microphones that constantly pick up noises in the vicinity of the individual wearing it and filter the noises using digital signal processing techniques ML models. There are people with different degrees of hearing loss. This system would be a boon to them in their work places. [ABSTRACT FROM AUTHOR]

This paper focuses on designing a 32-bit Reduced Instruction Set Computer (RISC) Scalable Processor Architecture (SPArc) subset gener al purposes processor. The design process covers instructions selection, Register Transfer Notation (RTN) design, Datapath Design, and Control Unit Design. Basic integer instruction was selected. Datapath was designed along with the RTN with a five-stage pipeline with direct connection between stages. This design was then validated using functionality simulation test and implemented in Field Programmable Gate Array (FPGA). The performance of the processor was measured using thermal report, power report, and time report. Functional test shows that the Processor can execute instructions as designed, which are Arithmetic/Shift/Logic, Control Transfers, and Memory access instructions. It was validated with the register content and signal generated in each stage. The design was also successfully implemented in FPGA with the maximum clock of 58 MHz as the synthesis report shows. Thermal report shows the thermal properties of the design, which shown the acceptable thermal margin of 56.9 ⁰C and junction temperature of 28.1 ⁰C. The power report shows the low power consumption of 0.266 W, which consists of dynamic power of 0.173 W and static power of 0.093 W. This work enables further development and to be used as master processor in System on Chip design of special purpose processors like cognitive processors. [ABSTRACT FROM AUTHOR]

One of the main difficulties in designing high-performance microprocessors is power consumption. Each CPU generation's tremendous increase in complexity and speed is beyond the advantages of feature size and voltage reduction scaling. Therefore, it's constantly a challenge for designers to come up Utilizing novel power-saving techniques while attempting to meet all the additional restrictions placed on the design. Power dense ties in electronic devices, and particularly in microprocessor chips, have increased during the last few decades. The heat problems within electronic circuits have dramatically increased as a result of the ongoing trend of decreasing device size. So, efforts to create materials and techniques to address thermal concerns within the processing unit began. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The display of the future is multimodal, integrating optical sensors, RFID antennas, ultrasound transducers, etc. The sensors produce a large amount of redundant data, which should be preprocessed on the substrate, ideally on the backpanel. Control gates and select and data drivers need to be more configurable and partitionable to create operational flexibility. This paper presents various circuit blocks for processing and control, including operational amplifiers, high‐resolution analog‐to‐digital converters, a microprocessor, DC‐DC converters, and high resolution sensor pixel array architectures. Moreover, the performance of the basic building blocks is compared in LTPS and IGZO technology. [ABSTRACT FROM AUTHOR]

This article presents the findings of an experiment designed to explore whether the utilization of a teaching aid, in this case the emulator EMU8086, can positively influence the target undergraduate students' attitude towards acquiring 8086 assembly language programming skills or not? Methods: Twenty-nine students participated in a oneday hands-on workshop. The sessions focused on 8086 assembly language programming using the EMU8086 emulator. All twenty-nine participants submitted pre- and post-workshop polls. For analyzing the pre- and post-workshop poll data, a matched-pair Wilcoxon signed-rank test was utilized. Results: The average confidence level of participants in their capability to create an assembly language program by themselves doubled from 1.7931 ± 0.1437 to 3.7586 ± 0.1071 (P = 4.68957E-21). The average confidence level of participants in the EMU8086's capability to assist in learning 8086 assembly language programming increased from 2.6207 ± 0.1749 to 3.9655 ± 0.0782 (P = 4.34958E-11). The average participant interest in similar skill enhancement opportunities soared from 3.2759 ± 0.1395 to 4.6897 ± 0.0874 (P = 5.25141E-14). The average participant interest in the domain of embedded systems slightly increased from 4.3103 ± 0.1005 to 4.6897 ± 0.0874 (P = 0.000145533). Conclusions: The findings suggest that exposure to the EMU8086 emulator had a positive impact on participants' attitude towards acquiring assembly language programming skills. Relevance: Identifying the factors that drive interest in the domain of embedded systems which may help attract a larger consortium of potential learners and even lower the dropout rate. [ABSTRACT FROM AUTHOR]

The increasing rates of colorectal cancer and associated mortality have attracted interest in the use of computer-aided diagnosis tools based on artificial intelligence (AI) for the detection of polyps at an early stage. Most AI models are implemented on software platforms; however, due to the demands of embedded devices, hardware implementations have to fulfill the demands of real-time applications with better accuracy and low-power consumption. In this letter, we propose an optimized four-layer network that can be implanted into an embedded device and determine the feasibility of implanting our convolutional neural network (CNN) into a microprocessor. The essential functions of the CNN (i.e., padding, convolution, ReLU, max-pooling, fully connected, and softmax layers) are implemented in the microprocessor. The proposed method achieves efficient classification with high performance and takes only 2.5488 mW at a working frequency of 8 MHz. We conclude this letter with a discussion of the results and future direction of research. [ABSTRACT FROM AUTHOR]

Digital system has been a part of human life since the invention of the computer with a microprocessor as the central brain. At the heart of a processor is an Arithmetic Logic Unit (ALU) that handles arithmetic and logic operations. The need for high-speed computation to handle complex computations demands microprocessors with higher performance. The existing 4-opcode 8-bit ALU cannot handle multiplication operations, so a solution is needed. In this research, while raising the appeal of beginners, a 12-bit ALU with eight operation codes (opcode) was designed and implemented in Xilinx’s Field Programmable Gate Array using a schematic diagram approach through logic gates. The designed and implemented ALU provides addition, subtraction, multiplication, square, AND, OR, NAND, and XOR operations. The multiplication operation was tested by performing the computation to provided datasets to obtain the distance travelled by ten military aircraft based on their maximum speed and air travel duration to ensure its performance. The computation performance comparison with an 8-bit ALU with four opcodes was also done. The computation was done for air travel between 10 to 60 minutes with a 10-minute difference. It was found that the 12-bit ALU with eight opcodes outperformed its contender with computation differences between 130.815 ns and 1,468.214 ns. This high performance is supported by the multiply operation that does repeated addition at one time. Based on this finding, the 8-opcode 12-bit ALU is more efficient in the context of computation time, with consistent accuracy. Moreover, the computation time required to calculate military aircraft data with different maximum speeds and air travel duration is only 119.501 ns.

Approximately 82% of amputees prefer microprocessor knees (MPKs) to the passive alternatives. However, the cost of these devices makes them inaccessible for many patients. The aim of this research is to develop an affordable MPK that allows for stumble reduction and flexion dampening at a fraction of the cost of similar devices. The GKnee was developed by a sophisticated mathematical model that can effectively calculate geometric configuration and simulate forces transferred through a prosthetic knee at any given point through the gait cycle. With a median error of 6%, the mathematical model was developed to the point of reasonable accuracy for determining component placement and force interactions. The model served as a valuable tool to assist in the iterative design process of the GKnee, influencing component selection for the hydraulic system and frame design. This model was then validated using a compression rig and a mock GKnee prototype. The GKnee was then evaluated for its ability to perform under expected loading conditions, using compression testing and dynamic flexion testing. This research led to the development of a sub USD 500 microprocessor prosthetic, while remaining under 2.27 kg.

One of the major causes of road accidents is sleepy drivers. Such accidents typically result in fatalities and financial losses and disadvantage other road users. Numerous studies have been conducted to identify the driver's sleepiness and integrate it into a warning system. Most studies have examined how the mouth and eyelids move. However, this limits the system's ability to identify drowsiness traits. Therefore, this study designed an Accident Detection Framework (RPK) that could be used to reduce road accidents due to sleepiness and detect the location of accidents. The drowsiness detectionmodel used three facial parameters: Yawning, closed eyes (blinking), and an upright head position. This model used a Convolutional Neural Network (CNN) consisting of two phases. The initial phase involves video processing and facial landmark coordinate detection. The second phase involves developing the extraction of frame-based features using normalization methods. All these phases used OpenCV and TensorFlow. The dataset contained 5017 images with 874 open eyes images, 850 closed eyes images, 723 open-mouth images, 725 closed-mouth images, 761 sleepy-head images, and 1084 non-sleepy head images. The dataset of 5017 images was divided into the training set with 4505 images and the testing set with 512 images, with a ratio of 90:10. The results showed that the RPK design could detect sleepiness by using deep learning techniques with high accuracy on all three parameters; namely 98% for eye blinking, 96% for mouth yawning, and 97% for head movement. Overall, the test results have provided an overview of how the developed RPK prototype can accurately identify drowsy drivers. These findings will have a significant impact on the improvement of road users' safety and mobility. [ABSTRACT FROM AUTHOR]

This study aims to determine the effect of critical thinking aspects on students' psychomotor skills. Aspects of critical thinking include interpreting, planning, predicting, analyzing, evaluating, and decision-making. This research was applied to a microprocessor and microcontroller programming technique subject at a vocational higher school in Surabaya-Indonesia. The multiple linear regression method was chosen to analyze the effect of simultaneous and partial aspects of critical thinking on students' psychomotor skills. The results showed that there was a significant influence between aspects of critical thinking simultaneously on students' psychomotor skills. While partially, only the predicting aspect has a significant influence on students' psychomotor skills. For other aspects, there is no significant effect on students' psychomotor skills. [ABSTRACT FROM AUTHOR]

Approximately 82% of amputees prefer microprocessor knees (MPKs) to the passive alternatives. However, the cost of these devices makes them inaccessible for many patients. The aim of this research is to develop an affordable MPK that allows for stumble reduction and flexion dampening at a fraction of the cost of similar devices. The GKnee was developed by a sophisticated mathematical model that can effectively calculate geometric configuration and simulate forces transferred through a prosthetic knee at any given point through the gait cycle. With a median error of 6%, the mathematical model was developed to the point of reasonable accuracy for determining component placement and force interactions. The model served as a valuable tool to assist in the iterative design process of the GKnee, influencing component selection for the hydraulic system and frame design. This model was then validated using a compression rig and a mock GKnee prototype. The GKnee was then evaluated for its ability to perform under expected loading conditions, using compression testing and dynamic flexion testing. This research led to the development of a sub USD 500 microprocessor prosthetic, while remaining under 2.27 kg. [ABSTRACT FROM AUTHOR]

The nuclear cleavage of a suboptimal primary miRNA hairpin by the Drosha/DGCR8 complex (“Microprocessor”) can be enhanced by an optimal miRNA neighbor, a phenomenon termed cluster assistance. Several features and biological impacts of this new layer of miRNA regulation are not fully known. Here, we elucidate the parameters of cluster assistance of a suboptimal miRNA and also reveal competitive interactions amongst optimal miRNAs within a cluster. We exploit cluster assistance as a functional assay for suboptimal processing and use this to invalidate putative suboptimal substrates, as well as identify a "solo" suboptimal miRNA. Finally, we report complexity in how specific mutations might affect the biogenesis of clustered miRNAs in disease contexts. This includes how an operon context can buffer the effect of a deleterious processing variant, but reciprocally how a point mutation can have a nonautonomous effect to impair the biogenesis of a clustered, suboptimal, neighbor. These data expand our knowledge regarding regulated miRNA biogenesis in humans and represent a functional assay for empirical definition of suboptimal Microprocessor substrates. [ABSTRACT FROM AUTHOR]

In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an FPGA-based development platform, through an SoC project, the implementation of HW_nMPRA_RTOS (a unified acronym for multi pipeline register architecture (nMPRA) where $n$ is the degree of datapath resource multiplication, hardware scheduler engine (nHSE) for $n$ threads and RTOS application programming interface (API)), dedicated processor architecture was developed, simulated and validated. This paper proposes an innovative soft-core implementation to reduce interrupt latencies while maintaining strong spatial and temporal isolation. Among the results which contain relevance and novelty, we can mention: rapid tasks context switching (1 clock cycle); The implementation of a distributed and versatile interrupt system that allows the interrupt attachment to any task; The implementation of a static scheduler and support for the dynamic tasks scheduling; Rapid response to events of up to 2 clock cycles. We demonstrate the architecture’s predictability, scalability, and performance by running a set of benchmark applications on several configurations of HW_nMPRA_RTOS synthesized on a Xilinx 7 Series FPGA.

In various fields, such as those with high-reliability requirements, there is a growing demand for high-performance microprocessors. Whereas commercial microprocessors offer a good trade-off between cost, size, and performance, they often need to be adapted to meet the reliability demands of safety-critical applications. To address this challenge, a Supervised Triple Macrosynchronized Lockstep architecture for multicore processors is presented in this work. Multiple recovery mechanisms, including rollback and roll-forward, have been implemented to harden the system. By integrating these mechanisms, the microprocessor becomes more robust and capable of mitigating potential errors or failures that may occur during operation. A quad-core ARM Cortex-A53 processor has been used as a case study, and an extensive fault injection campaign in the register file has been conducted to evaluate the effectiveness of our proposed approach. The results show that the hardened system exhibits high reliability, with 100% error coverage and error correction capabilities of up to 86.40%.

This article discusses the topical issues of managing information security vulnerabilities in the life cycle stages of processors and computer equipment. An analysis of the experience of identifying vulnerabilities in the course of the joint design of the processor, computing module and computing complex was carried out. A number of actions have been developed and presented to ensure the control of hardware vulnerabilities in the development stage. The use of the binary translation technology of the Elbrus platform is proposed to prevent the execution of malicious software. A method has been developed to eliminate vulnerabilities in computer equipment for automated systems used for various purposes by using the Lintel binary translation system component. An experiment is described, the purpose of which was to successfully exploit the Meltdown vulnerability on a computer with an Elbrus processor. The experiment showed that, due to the peculiarities of the microarchitecture of Elbrus processors, the exploitation of Meltdown-type vulnerabilities is impossible. [ABSTRACT FROM AUTHOR]

Copyright of UCV Hacer is the property of UCV Hacer and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The requirement for alternatives in roll-to-roll (R2R) processing to expand thin film inspection in wider substrates at lower costs and reduced dimensions, and the need to enable newer control feedback options for these types of processes, represents an opportunity to explore the applicability of newer reduced-size spectrometers sensors. This paper presents the hardware and software development of a novel low-cost spectroscopic reflectance system using two state-of-the-art sensors for thin film thickness measurements. The parameters to enable the thin film measurements using the proposed system are the light intensity for two LEDs, the microprocessor integration time for both sensors and the distance from the thin film standard to the device light channel slit for reflectance calculations. The proposed system can deliver better-fit errors compared with a HAL/DEUT light source using two methods: curve fitting and interference interval. By enabling the curve fitting method, the lowest root mean squared error (RMSE) obtained for the best combination of components was 0.022 and the lowest normalised mean squared error (MSE) was 0.054. The interference interval method showed an error of 0.09 when comparing the measured with the expected modelled value. The proof of concept in this research work enables the expansion of multi-sensor arrays for thin film thickness measurements and the potential application in moving environments. [ABSTRACT FROM AUTHOR]

BackgroundLaser simulation technology is widely used in the research of transient ionizing radiation effects in semiconductor devices. Fully dielectrically isolated silicon-on-insulator (SOI) devices exhibit different responses to dose-rate gamma irradiation compared to bulk-Si devices.PurposeThis study aims to examine the photocurrents of both Si-based and SOI NMOS transistors, and investigate the performance of a SOI MCU with varying dose rates.MethodAn irradiation experiment was conducted on three types of transistors by using a 1 064 nm/12 ns laser device, and the photocurrent was tested under various laser energies. A pulsed γ-ray source was employed to perform the transient γ dose rate radiation test on an SOI-integrated circuit. The function, electrical parameters, and flipflop chain status of the SOI-integrated circuit under different dose rates were measured. Based on theoretical model for the generation of photocurrent in SOI transistor, the dose-rate threshold for logic flipping and corresponding critical charge were estimated based on theoretical model for the generation of photocurrent in SOI transistor.ResultsThe results indicate that the peak photocurrent of the SOI transistor is approximately 20 times lower than that of the bulk silicon transistor with the same feature size under identical irradiation conditions. This reduction is attributed to the decreased charge collection sensitive area of the SOI transistor. Within a dose rate range from 1.0×109 rad(Si)·s-1 to 4.2×1011 rad(Si)·s-1, the SOI-integrated circuit exhibites no latch-up effect. However, irradiation-induced upsets are observed in the SOI-integrated circuit.ConclusionsThese upsets caused by transient radiation effects manifest as transient functional interruptions, variations in operating current and voltage, and erroneous flip-flop statuses. These irradiation-induced upsets in the SOI-integrated circuit are likely attributable to, among other factors, transistor upsets and circuit-level voltage fluctuations on printed circuit board.

Aiming at the booming building breeding mode, basis on the traditional one-story pig breeding control system, a set of building breeding intelligent control systems based on Model-Free Adaptive Control (MFAC) algorithm was designed. The system adopts the control mode of primary control plus sub-control, which has higher control precision and faster response speed. This paper first designs the hardware system based on the operating principle of the system and then creates the controller software of the system based on the principle of MFAC. Through simulation verification, the results show that the proposed control system based on MFAC can realize the precise control of the environmental parameters of each building unit and has good robustness and adaptability. [ABSTRACT FROM AUTHOR]

The subject of research is the development and implementation of Internet of Things (IoT) network structures for monitoring and analyzing audio information based on Raspberry microprocessor (MP) and an Arduino controller. The purpose of the article is to detail the process of developing an IoT based audio information monitoring network and evaluate the results. The authors have developed two variants of IoT structures for monitoring and analyzing audio and voice information. The IoT network includes a sound sensor (microphone), a unit for analyzing the information received from it and a decision-making module. A diagram of the first IoT structure for assessing the sound level based on the MP and controller is given.The algorithm of IoT network functioning for the analysis of voice information is detailed. It includes receiving information from the microphone, transmitting this information to the MP, processing it according to certain rules, forming a solution by the controller and issuing recommendations to a user. The algorithm is implemented in the IoT network, which includes a microphone, Raspberry MP, Arduino controller, software, applications for the operator.A prototype of the IoT network was created for the analysis of voice information and experiments were conducted to test its functioning. The audio recognizer was trained using various audio samples. The voice sound analysis system was tested in four scenarios: with a large and small amount of background noise, loud and quiet voice. Analysis of the results of the experiment showed that the voice sound analysis system works better when the voice is loud, as well as in a place where the situation is with minimal background noise.

MicroRNAs are small RNAs, 20–22 nt long, the main role of which is to downregulate gene expression at the level of mRNAs. MiRNAs are fundamental regulators of plant growth and development in response to internal signals as well as in response to abiotic and biotic factors. Therefore, the deficiency or excess of individual miRNAs is detrimental to particular aspects of a plant's life. In consequence, the miRNA levels must be appropriately adjusted. To obtain proper expression of each miRNA, their biogenesis is controlled at multiple regulatory layers. Here, we addressed processes discovered to influence miRNA steady-state levels, such as MIR transcription, co-transcriptional pri-miRNA processing (including splicing, polyadenylation, microprocessor assembly and activity) and miRNA-encoded peptides synthesis. MiRNA stability, RISC formation and miRNA export out of the nucleus and out of the plant cell also define the levels of miRNAs in various plant tissues. Moreover, we show the evolutionary conservation of miRNA biogenesis core proteins across the plant kingdom. [ABSTRACT FROM AUTHOR]

FYVE domain protein required for endosomal sorting 1 (FREE1), originally identified as a plant‐specific component of the endosomal sorting complex required for transport (ESCRT) machinery, plays diverse roles either in endosomal sorting in the cytoplasm or in transcriptional regulation of abscisic acid signaling in the nucleus. However, to date, a role for FREE1 or other ESCRT components in the regulation of plant miRNA biology has not been discovered. Here, we demonstrate a nuclear function of FREE1 as a cofactor in miRNA biogenesis in plants. FREE1 directly interacts with the plant core microprocessor component CPL1 in nuclear bodies and disturbs the association between HYL1, SE and CPL1. Inactivation of FREE1 in the nucleus increases the binding affinity between HYL1, SE, and CPL1 and causes a transition of HYL1 from the inactive hyperphosphorylated version to the active hypophosphorylated form, thereby promoting miRNA biogenesis. Our results suggest that FREE1 has evolved as a negative regulator of miRNA biogenesis and provides evidence for a link between FYVE domain‐containing proteins and miRNA biogenesis in plants. Synopsis: The plant‐specific FYVE domain‐containing protein FREE1 acts as a cofactor of microprocessor through interacting with CPL1 in the nucleus. This interaction regulates the phosphorylation status of HYL1 and represses miRNA biogenesis. FREE1 interacts with the plant core microprocessor component CPL1 in nuclear bodies.FREE1 affects the phosphorylation of HYL1 by reducing the binding between HYL1, SE, and CPL1.FREE1 acts as a negative regulator of miRNA biogenesis in Arabidopsis. [ABSTRACT FROM AUTHOR]

This paper presents a dual fire-fighting robot designed to operate in a variety of environments. Firefighting portends serious safety challenges and high-risk factors for human firefighters. The use of robots for such tasks will surmount these challenges if adequately applied. The dual-mode robotic system described here utilizes two types of fire suppression modes--automatic and manual. Equipped with sensors the robot detects the location and intensity of the fire and can navigate its way to extinguish it. In autonomous mode, the robot senses any occurrence of flame and approaches it and activates its water spraying system to put off the flames and reverse back to its detection/patrol operation. In manual operation, an operator controls the whole movement and the pumping action of the system remotely using a smart device or PC via a Wi-Fi network. The robot was tested in several simulated fire scenarios and demonstrated a high level of effectiveness in extinguishing fires. Results indicate the dual-mode firefighting robot has the potential for safety and efficiency improvement in fire suppression operations in a range of settings. [ABSTRACT FROM AUTHOR]

Despite their low emissions, hybrid electric cars have caused concerns for the safety of other road users (pedestrians, cyclists, etc.). At low speeds (below 30 km/h), electric and hybrid cars are almost quiet, which poses a risk to pedestrians. This is particularly true for those who are more susceptible to harm, such as the visually handicapped. The primary goal of this project is to create a working prototype of a vehicle (robot) equipped with a pedestrian-detecting automated signaling system and speakers aimed towards the pedestrian. This enhances the vehicle's capacity for responding to its surroundings. The alert tone must also be fine-tuned so that it is audible but not obnoxious.

Extreme weather events cause stream overflow and lead to urban inundation. In this study, a decentralized flood monitoring system is proposed to provide water level predictions in streams three hours ahead. The customized sensor in the system measures the water levels and implements edge computing to produce future water levels. It is very different from traditional centralized monitoring systems and considered an innovation in the field. In edge computing, traditional physics-based algorithms are not computationally efficient if microprocessors are used in sensors. A correlation analysis was performed to identify key factors that influence the variations in the water level forecasts. For example, the second-order difference in the water level is considered to represent the acceleration or deacceleration of a water level rise. According to different input factors, three artificial neural network (ANN) models were developed. Four streams or canals were selected to test and evaluate the performance of the models. One case was used for model training and testing, and the others were used for model validation. The results demonstrated that the ANN model with the second-order water level difference as an input factor outperformed the other ANN models in terms of RMSE. The customized microprocessor-based sensor with an embedded ANN algorithm can be adopted to improve edge computing capabilities and support emergency response and decision making. [ABSTRACT FROM AUTHOR]

Long non-coding RNAs (lncRNAs) have emerged as key regulators in a wide range of biological processes. Here, we identified a mouse miRNA-host gene lncRNA (Lnc-Nr6a1) upregulated early during epithelial-to-mesenchymal transition (EMT). We show that when lncRNA is processed, it gives rise to two abundant polyadenylated isoforms, lnc-Nr6a1-1 and lnc-Nr6a1-2, and a longer non-polyadenylated microprocessor-driven lnc-pri-miRNA containing clustered pre-miR-181a2 and pre-miR-181b2 hairpins. Ectopic expression of the lnc-Nr6a1-1 or lnc-Nr6a1-2 isoform enhanced cell migration and the invasive capacity of the cells, whereas the expression of the isoforms and miR-181a2 and miR-181b2 conferred anoikis resistance. Lnc-Nr6a1 gene deletion resulted in cells with lower adhesion capacity and reduced glycolytic metabolism, which are restored by lnc-Nr6a1-1 isoform expression. We performed identification of direct RNA interacting proteins (iDRIP) to identify proteins interacting directly with the lnc-Nr6a1-1 isoform. We defined a network of interacting proteins, including glycolytic enzymes, desmosome proteins and chaperone proteins; and we demonstrated that the lnc-Nr6a1-1 isoform directly binds and acts as a scaffold molecule for the assembly of ENO1, ALDOA, GAPDH, and PKM glycolytic enzymes, along with LDHA, supporting substrate channeling for efficient glycolysis. Our results unveil a role of Lnc-Nr6a1 as a multifunctional lncRNA acting as a backbone for multiprotein complex formation and primary microRNAs. [ABSTRACT FROM AUTHOR]

Wave energy is a renewable resource with high energy potential. This research work proposes a low power piezoelectric energy harvesting system based on the heave motion of ocean buoys. This Piezoelectric Energy Harvester (PEH) is composed of piezoelectric diaphragms coupled with superballs to enhance the output of the piezoelectric sensor. The PEH setup is designed within a floating buoy and tested in a wave flume by varying the frequency of regular waves. The heaving of the buoy causes the superball to oscillate and impact upon the piezo diaphragms thereby producing power. This output is then processed using appropriate AC to DC converter and booster circuits. The single-axis sensor-diaphragm responses under regular wave conditions with varying wave heights were analyzed. A rms voltage of about 2.56 V was generated for a wave height of 0.21 m and wave period of 1.2 s. The wave flume experimental results show that the maximum harvested power was about 80 mW by the entire piezo sensor diaphragm setup for the wave height range of 0.06 m to 0.21 m and wave period of 1.22 s to 2.13 s. Using the same technique in the ocean buoys of diameter 0.9 m in the swell wave conditions between 0.5 to 3.5 m significant wave height, the system can generate maximum voltage of up to 16 V using 28 numbers of superballs with sensors arranged in parallel/series combinational power circuits. This harvesting technique will be very much useful for coastal & offshore buoys to harvest power in a hybrid approach during the failure in solar battery charging during monsoon and unfavorable weathers. [ABSTRACT FROM AUTHOR]

This article discusses the topical issues of managing information security vulnerabilities in the life cycle stages of processors and computer equipment. An analysis of the experience of identifying vulnerabilities in the course of the joint design of the processor, computing module and computing complex was carried out. A number of actions have been developed and presented to ensure the control of hardware vulnerabilities in the development stage. The use of the binary translation technology of the Elbrus platform is proposed to prevent the execution of malicious software. A method has been developed to eliminate vulnerabilities in computer equipment for automated systems used for various purposes by using the Lintel binary translation system component. An experiment is described, the purpose of which was to successfully exploit the Meltdown vulnerability on a computer with an Elbrus processor. The experiment showed that, due to the peculiarities of the microarchitecture of Elbrus processors, the exploitation of Meltdown-type vulnerabilities is impossible.

MicroRNAs (miRNAs) are small non-coding endogenous RNA molecules, 18–24 nucleotides long, that control multiple gene regulatory pathways via post-transcriptional gene silencing in eukaryotes. To develop a comprehensive picture of the evolutionary history of miRNA biogenesis and action in land plants, studies on bryophyte representatives are needed. Here, we review current understanding of liverwort MIR gene structure, miRNA biogenesis, and function, focusing on the simple thalloid Pellia endiviifolia and the complex thalloid Marchantia polymorpha. We review what is known about conserved and non-conserved miRNAs, their targets, and the functional implications of miRNA action in M. polymorpha and P. endiviifolia. We note that most M. polymorpha miRNAs are encoded within protein-coding genes and provide data for 23 MIR gene structures recognized as independent transcriptional units. We identify M. polymorpha genes involved in miRNA biogenesis that are homologous to those identified in higher plants, including those encoding core microprocessor components and other auxiliary and regulatory proteins that influence the stability, folding, and processing of pri-miRNAs. We analyzed miRNA biogenesis proteins and found similar domain architecture in most cases. Our data support the hypothesis that almost all miRNA biogenesis factors in higher plants are also present in liverworts, suggesting that they emerged early during land plant evolution. [ABSTRACT FROM AUTHOR]

The objectives of this Classroom Action Research were to determine: (1) increase student activity during the learning process of Microprocessors and Microcontrollers by applying the Problem Based Learning model at SMK Negeri 2 Pematangsiantar, (2) increase student learning outcomes in Microprocessor and Microcontroller learning by applying the Problem Based Learning model at SMK Negeri 2 Pematangsiantar. This research was conducted at SMK Negeri 2 Pematangsiantar for 1 month starting from August 2019. The subjects of this study were 22 students of class X1 TAV 1. The action in this study consisted of two cycles, namely Cycle I and Cycle II. Cycle I was carried out using the Problem Based Learning model. The results of the first cycle showed that 45.63% of students were active and the mean score of vocational competence students for Microprocessor and Microcontroller was still 56.82. However, these results do not meet the action indicators, namely 75% of students get a value > 75, then second cycle II is carried out. Cycle II carried out the same application. In cycle II 84.38% of students are active, and the average value of vocational competence for Microprocessors and Microcontrollers increases to 80.27. So it can be concluded that the learning process using the Problem Based Learning model can increase the activeness and ability of students in learning vocational competencies in Audio Video Engineering. The implication is that teachers must apply innovative and creative learning models. And it is suggested that Electronics Engineering teachers can improve their teaching skills to be more communicative and active in participating in various pieces of training. [ABSTRACT FROM AUTHOR]

The development of devices for the Internet of Things (IoT) requires the rapid prototyping of different hardware configurations. In this paper, a modular hardware platform allowing to prototype, test and even implement IoT appliances on low-cost reconfigurable devices is presented. The proposed platform, named Dracon, includes a Z80-clone microprocessor, up to 64 KB of RAM, and 256 inputs/outputs (I/Os). These I/Os can be used to connect additional co-processors within the same FPGA, external co-processors, communications modules, sensors and actuators. Dracon also includes as default peripherals a UART for programming and accessing the microprocessor, a Real Time Clock, and an Interrupt Timer. The use of an 8-bit microprocessor allows the use of the internal memory of the reconfigurable device as program memory, thereby, enabling the implementation of a complete IoT device within a single low-cost chip. Indeed, results using a Spartan 7 FPGA show that it is possible to implement Dracon with only 1515 6-input LUTs while operating at a maximum frequency of 80 MHz, which results in a better trade-off in terms of area and performance than other less powerful and less versatile alternatives in the literature. Moreover, the presented platform allows the development of embedded software applications independently of the selected FPGA device, enabling rapid prototyping and implementations on devices from different manufacturers. [ABSTRACT FROM AUTHOR]

NAND Flash memory is widely used as storage device in embedded systems, because of its advantages on capacity, cost and speed. However, due to the inherent device characteristics of NAND Flash, complex driver is required to read and write it, and the code stored on it cannot be executed directly. Therefore, NAND Flash is not suitable for boot code storage. Generally, boot code is stored on NOR Flash and executed on it directly. The boot code on NOR Flash will boot the operating system stored in NAND Flash, which increases the system cost and power consumption. This paper designs and implements a CPU secure boot method based on NAND Flash. The structure of block mapping table is added in NAND Flash controller, and the code stored in the first block of NAND Flash is used to search and fill in the block mapping table. Using this method, part of NAND Flash storage blocks can be directly mapped to memory space, so that the boot code stored on NAND Flash can be executed directly without drivers. Besides, an extended BootRom scheme is proposed. Combining with the structure of NAND Flash address mapping, part of on-chip BootRom is extended to the first block of NAND Flash. Hash comparison is used to verify the extended BootROM, which effectively reduces the design complexity and code amount of on-chip BootRom. Our method can effectively implement the secure boot of single NAND Flash system, thus reducing the system cost and improving the system security. [ABSTRACT FROM AUTHOR]

As semiconductor technology scales, modern microprocessors are more vulnerable to transient faults. Software-level fault tolerance schemes are promising because they can improve reliability effectively without extra hardware. Redundant Multi-threading (RMT) uses off-the-shelf cores as redundancy to achieve error resilience. Latest software RMT fault-tolerance models do not effectively cope with transient faults occurring on multiple components during the application execution, resulting in a large number of silent data corruptions (SDC). To address this challenge, we propose FERNANDO, a software-level RMT runtime fault tolerance scheme which provides enhanced error detection and comprehensive error recovery by Triple-Modular Redundancy (TMR). On an ARM Cortex-A57 like simulated microprocessor, we performed probability model transient fault injection experiments in different components of all cores. The results demonstrate that, compared to the state-of-the-art technique, FERNANDO can reduce the SDC rate by about 86.67 percent and optimize the execution time overhead by about 19.64 percent.

Asynchronous systems are native to a full custom domain. Their implementation using auto place-and-route tools requires dynamic calibration of interconnects delays in addition to the placement of predefined static delay elements. This paper presents a completion detector for a single-rail bit encoded datapath that, as an adaptive-delay element, eliminates the need to insert any predefined delay element and caters to routing delays dynamically. A programmable pulse-generator is also proposed that empowers the designers to generate clock signals based on the timing report obtained from the CAD tool to drive various synchronous subsystems and embedded resources like BRAMs in FPGAs. Employing these components, we present an asynchronous pipeline model with implicit control to expedite migration from the traditional synchronous pipelines to their asynchronous counterparts. A single-rail bit encoded datapath has been used to utilize chip area effectively instead of a delay-insensitive dual-rail datapath, and a two-phase handshake protocol has been adopted as opposed to a four-phase handshake protocol to lower handshaking overhead. A RISC processor validates the proposed asynchronous pipeline model, exhibiting a smooth functionality and power-delay parameter comparable to that of a synchronous pipeline, in addition to ease of routing and avoiding clock skews in a complex system-on-chip.

Security is the condition of being protected against danger or loss. In the general sense, security is a concept similar to safety. The word "security" in general usage is synonymous with "safety," but as a technical term "security" means that something not only is secure but that it has been secured. Women safety is a very important issue due to rising crimes against women these days. To help resolve this issue we propose a GPS based women's safety system that has dual security feature. This device consists of a system that ensures dual alerts in case a woman is harassed or she thinks she is in trouble. [ABSTRACT FROM AUTHOR]

To bridge up the quality gaps and excel in the production of eggplant there is a need to switch the conventional production system to smart greenhouse house monitoring system. The study was designed to evaluate the growth parameters using smart greenhouse monitoring system designed with Raspberry-Pi microprocessor and sensors to control the microclimate (temperature and humidity) of a prototype greenhouse. A set of experiment was designed, one in a smart greenhouse system and the 2nd in the conventional greenhouse system to evaluate the growth parameters of eggplant. In a microclimate of smart greenhouse the temperature and humidity was set controlled using two sensors and automation system to control the mist spray and heating/cooling system inside the prototype greenhouse. Standard production technology was adopted in both the experiments and the experiment was replicated thrice. It was observed that the smart greenhouse monitoring system maintained the microclimate inside the prototype greenhouse ultimately effect the growth and yield parameters. The results predicted a progressive increase in growth parameter up to 10-20% in plant height, flowers per plant, fruits per plant and weight of fruit in automated greenhouse using microcontroller. Similarly quality of fruit was significantly affected as maximum fruit diameter 35 mm and fruit firmness 6.9 libre was recorded that was significantly higher than the fruit in the conventional greenhouse. The over average yield of eggplant per plant was recorded 5.6 kg/plant in automated greenhouse while 4 kg/plant fruit yield was recorded in conventional greenhouse that was significantly higher. The findings of current study predicted that the overall yield of eggplant was significantly higher and the growth and quality parameters were also higher in automated greenhouse using microcontroller and can be used for the potential eggplant production in urban agriculture. [ABSTRACT FROM AUTHOR]