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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

The electromigration (EM) activation energy ( $\text {E}_{\text {A}}$ ) of alternative metals, such as Ru and Co, was obtained using low-frequency noise (LFN) measurements. High activation energies were expected, but values of ≈1 eV are found, most likely related to diffusion along with the metal-dielectric interface. Wafer-level accelerated EM tests were carried out to compare the LFN $\text {E}_{\text {A}}$ to the EM $\text {E}_{\text {A}}$ in the Ru wires. The calculation of the EM $\text {E}_{\text {A}}$ is found to be strongly dependent on the assumed temperature profile in the wire due to Joule heating (JH). The temperature profile was calculated analytically, assuming the contacts are at ambient temperature. For a void forming in direct proximity of the contact, the EM $\text {E}_{\text {A}}$ then matches the LFN $\text {E}_{\text {A}}$ . For a void at average wire temperature (ambient + JH), $\text {E}_{\text {A}}\approx $ 2 eV. In addition to demonstrating the application of LFN to study EM in alternative metals, this article also cautions for the impact of JH on the calculation of $\text {E}_{\text {A}}$ in interconnects.

In this paper the electromigration (EM) limits of Cu nano-interconnects are studied considering the impact of microstructure in Co cap schemes and performance booster technologies i.e. via pre-fill and scaled barrier-liner schemes. A combination of experimental and physics-based modelling approaches is employed to provide fundamental understanding of the involved mechanisms. The results show that linewidth reduction, higher trench depth, i.e. larger aspect ratio (AR) and thinner barrier and liners result in more polycrystalline copper texture. It was found that at 10.5 nm linewidth, ~95% of the nano-interconnect length is polycrystalline while for 25 nm linewidth this is ~85%. A 90% drop of jfail i.e. the current density that induces failure at 10 years, was found by scaling linewidth from 25 nm to 10.5 nm in Cu interconnects with Co cap. Experiments show a 70% drop of time to failure due to barrier film thickness scaling from 3 nm to 2 nm for PVD TaN. Utilization of Co cap and via prefill were found to increase jfail by ~10 fold and ~3 fold, respectively.

Cu pumping is defined as the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. In previous publications both a lognormal distribution and a distribution of the maximum of two normal variables were used to fit experimental data. In this paper, these two types of statistical distribution are compared, showing that the maximum of two normal distributions provides a better fit, in particular at the right tail which is more significant for the potential reliability impact of Cu pumping. Also, it is shown how Cu pumping is determined by the network of random high angle grain boundaries in the Cu region near the TSV top, as an extension of a previous analysis which occurred at the TSV top surface only. This relation between Cu pumping and Cu microstructure provides a physical interpretation of the maximum of two normal distributions, based on the deformation mechanisms underlying Cu pumping.

This paper demonstrates the deteriorating electromigration (EM) reliability of Cu interconnects when scaling the metal pitch from 54 to 44nm. The study is carried out using a new EM test method based on low-frequency noise. Both EM lifetime and activation energy are found to decrease when scaling the line-width from 32 to 22nm. The decreasing activation energy is attributed to an increased number of grain boundaries and therefore enhanced grain boundary diffusion in narrow lines. The paper also shows that EM lifetimes can be qualitatively predicted based on the data obtained from LFN measurements.

Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing. At such small dimensions, the ruthenium effective resistance depends less on the scaling than that of Cu/barrier systems. Ruthenium effective resistance potentially crosses the Cu curve at 14 and 10 nm according to the semiempirical interconnect resistance model for advanced technology nodes. These extremely scaled ruthenium lines show excellent electromigration behavior. Time-dependent dielectric breakdown measurements reveal negligible ruthenium ion drift into low-κ dielectrics up to 200 °C, demonstrating that ruthenium can be used as a barrierless metallization in interconnects. These results indicate that ruthenium is highly promising as a replacement to Cu as the metallization solution for future technology nodes.

This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions that are being developed at imec.

High-aspect-ratio (HAR) Ru power rails, buried in front-end-of-line (FEOL) oxide, can potentially replace conventional middle-end-of-line (MOL) Cu power rails. The HAR feature can boost performance by reducing resistance and voltage drop along the power line. The buried nature, helps to minimize standard cell height by freeing up routing resources at MOL, enabling overall area scaling. This paper demonstrates, Ru lines of aspect ratio up to 7, at a CD of 18 nm. Line resistance at these dimensions, measures at 60 Ω/µm, with the minimum electrical resistivity of 8.8 µΩcm, as extracted from the temperature-controlled-resistance (TCR) measurements. HAR Ru lines are also found to withstand very high FEOL thermal budgets, such as 1000 °C activation anneal for 1.5 s. The combination of all these factors, make HAR Ru buried power rail, a promising scaling booster for next generation technology nodes.

We show the first electromigration (EM) failures of full ruthenium interconnects with a cross sectional area of 60nm2. The void is observed at the anode, which demonstrates that in p-type metals, such as Ru, the electromigration force acts in the direction of the electric field. The conventional representation of electromigration as electrons transferring their momentum onto the metal ions, thus has to be adapted for such metals. Moreover, we find that diffusion at the Ru-SiO 2 interface is the dominant diffusion mechanism for EM failure in these specific Ru lines.

To predict the impact of technological variables such as materials, dimensions, interfaces, and operating conditions on Cu electromigration, in this study a hybrid modeling framework is developed by coupling a global Korhonen-type electromigration modeling module with a cellular automaton-based void dynamics module. The modeling framework is corroborated and benchmarked using experiments on Cu interconnects and is used to predict the impact of scaling on Cu electromigration induced stress evolution. The simulations shed light on the impact of dimensional scaling on stress kinetics, void nucleation, and growth phases, where the nucleation phase is found to become longer than the growth phase and voids are found to grow relatively more rapidly upon nucleation in highly scaled linewidth. In addition, the simulations predict 22% lower median time to failure and a higher variability of time to failure for downstream vs upstream electromigration modes due to the more critical impact of near via voiding in downstream cases. Lending further credence to its predictive merits, the model predicts and explains complex R-shift signatures occurring at high temperature electromigration experiments due to void dynamics.

This paper reports on the mechanical design, the fabrication technology and the key performance and reliability aspects of novel 0-level thin film vacuum packages for (RF-)MEMS. The packages typically feature a dielectric cap composed of nanoporous alumina and PECVD silicon nitride with a total thickness between 6 and 8.3 μm. The surface micromachining fabrication process is based on a relatively simple method for the wafer-level formation of freestanding nanoporous alumina membranes, featuring extremely narrow cylindrical nanopores with diameters in the range of 10–20 nm and aspect ratio exceeding 100. The package impact on an encapsulated coplanar waveguide (CPW) is minimized (up to 67 GHz) by locally narrowing the RF feedthroughs underneath the package anchor. Furthermore, the hermeticity of various package configurations is evaluated by means of optical monitoring of the cap deflection under different environmental conditions, including short-term exposure to helium and long-term (up to 14 months) exposure to air. Finally, a comprehensive investigation of the reliability of the thin film packages and their compatibility with high-pressure epoxy overmolding 1-level packaging is discussed.

We demonstrate 10 nm half-pitch (HP) Ruthenium interconnects filled by atomic layer deposition (ALD). The resistivity and the cross-sectional area of Ruthenium interconnects were determined via the Matthiessen's rule method. We find that the resistivity of Ru was rather independent of the cross-sectional area of the interconnect, increasing from 12 µΩcm for larger lines to 15–17 µΩcm for cross-sectional areas of 200–300 nm2. 10 nm HP Ru lines showed no electromigration failures at 5 MA/cm2 and 300°C during 1000 hours. Time-dependent dielectric breakdown measurements indicated that Ruthenium does not require a diffusion barrier on both dense and porous low-κ dielectrics.