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An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.

In this letter, a novel Superjunction Metal-Oxide -Semiconductor Field Effect Transistor with wave-type field limiting ring (WFLR-SJ-MOSFET) is proposed to improve the di/dt robustness of body diode reverse recovery. When SJ-MOSFET body diode goes through reverse recovery, the WFLR can suppress and rebuild the peak electric field which is resulted from the large current flowing through the sensitive terminal boundary region. As a consequence, the ruggedness of dynamic avalanche during reverse recovery is optimized. Finally, the di/dt robustness of WFLR-SJ-MOSFET body diode reverse recovery is improved by 3.2 times from 72 A/μs to 320 A/μs comparing with the conventional SJ-MOSFET.

In this paper, a novel failure mechanism under unclamped inductive switch (UIS) for Split-Gate Trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with large current is investigated. The device sample is tested and analyzed in detail. The simulation results demonstrate that the nonuniform potential distribution of the source poly should be responsible for the failure. Three structures are proposed and verified available to improve the device UIS ruggedness by TCAD simulation. The best one of the structures the device with source metal inserting into source poly through contacts in the field oxide is carried out and measured. The results demonstrate that the optimized structure can balance the trade-off between the UIS ruggedness and the static characteristics.

The failure mechanism of the single-phase power module for three-phase converter applications with high output power is investigated. It illustrates that the higher current density on the near-terminal side of the power device, along with the abreast bonding that induces thermal coupling at the second footprints of bond wires, together result in the failure of the power device in the module. Then, an improved bonding method by redistributing the bond wires is proposed to solve the reliability problem. The bond wires are staggerly soldered on the surface of the device, avoiding the second footprints from listing in a line to reduce the thermal accumulation. The simulation performed by TCAD ANSYS shows that the junction temperature ( ${\mathbf{T}}_{\mathbf{j}} $ ) can be effectively decreased through this way. A practical experiment is also carried out to verify the availability of the optimized bonding method, which demonstrates that the improved method can decrease the ${\mathbf{T}}_{\mathbf{j}} $ of the device by 17 °C under 65A operating current.

In this paper, we designed a 1.5-kV trench-gate field-stop IGBT (FS-IGBT) and its on-state saturation voltage, which is smaller than 1.6 V. However, during the avalanche test, when the current limiting value of the tester is large, we have found a breakdown failure phenomenon in the designed IGBT structure although the breakdown voltage in the termination is higher than that in the cell region. The failure mechanism is investigated. It is illustrated that a filament is triggered due to some hole carriers, which can flow beneath the trenches from the cell region and then accumulate in the transition region if the trenches are ending at the deep $p$ - well region in the termination, which is different from that in the VDMOS. To improve the avalanche reliability, a new termination structure with segregated deep $p$ - well regions and the isolated trench is proposed and verified by numerous measurements. This paper has a significant meaning for the design of the termination of the trench-gate FS-IGBT with very low saturation voltage.

In this Letter, a novel 1200 V FS- insulated gate bipolar transistors (IGBT) is proposed to improve the trade-off between avalanche ruggedness and on-state voltage drop. The proposed IGBT features the high doping and thin n-layer under trench gates and we call it the electric field modulation layer (EFM layer). Under the avalanche condition, the EFM layer can form the sharp electric filed distribution in the EFM layer and the avalanche multiplication is constrained in the thin EFM layer. The difference between the holes and electrons due to the avalanche multiplication effect at the emitter side of the IGBT is minished. Therefore, the negative difference resistance in the avalanche I–V curve caused by the difference between the holes and electrons is eliminated. As a consequence, the avalanche ruggedness of the EFM-IGBT is improved. In the on-state, the high doping EFM layer can store the carriers and the on-state voltage drop of the EFM-IGBT is reduced to 1.48 V at 200 A/cm2. Finally, the EFM-IGBT improves the trade-off between avalanche ruggedness and on-state voltage drop.

In this paper, the switching noise of Super-junction MOSFET in full bridge converter system has been investigated. According to the experimental results, the largest noise is induced by the steep reverse recovery current variation (dirr/dt) during the Super-junction MOSFET body diode reverse recovery. In order to understand the phenomena, the TCAD simulations and analyses have been carried out. It is found that the reverse recovery currents in the cell region and the termination region combine to result in the steep dirr/dt. The current in cell region aggravates the current variation, however, the current in termination region contributes to alleviate the current variation. Furthermore, it is also shown that increasing the hole injection level in termination region can alleviate the dirr/dt, and then the switching noise is reduced effectively. Finally, an optimized structure with heavily doped main junction in the termination region is proposed for the SJ-MOSFET, which can increase the hole injection efficiency greatly to reduce the switching noise during the Super-junction MOSFET body diode reverse recovery.

The influence of forward current freewheeling time on the reverse recovery di/dt robustness of Superjunction (SJ) MOSFET body diode is investigated in detail. It is found that the maximum di/dt capability of body diode is improved dramatically with reducing the forward current freewheeling time. To explore this phenomenon, physical TCAD simulations and experiments have been carried out. It shows that there is an extremely inhomogeneous reverse recovery behavior between the cell region and the termination region in the SJ-MOSFET, which results in a destructive dynamic avalanche behavior at the edge of the termination. The reduction of the forward current freewheeling time can suppress the inhomogeneous phenomenon and impact the reverse recovery di/dt robustness of body diode. Thereby, it points out that the real di/dt robustness of SJ-MOSFET body diode should be evaluated with the long enough forward current freewheeling time.

This work provides a physical insight into the failure of Superjunction MOSFET (SJ-MOSFET) for full bridge inverter system during an reverse recovery behavior. The inspection of failed SJ-MOSFET reveals burnt-out points in the vicinity of the device edge termination. To explore this result, physical TCAD simulations have been carried out. It is found that there is an extremely inhomogeneous reverse recovery behavior between the active region and the termination region in the SJ-MOSFET. And a destructive dynamic avalanche phenomenon is occurred at the edge of the termination, which is identified as responsible for the observed failure. Finally, an optimization termination structure with P+ dynamical field limiting ring (DFLR) is proposed to suppress the dynamical avalanche and the reverse recovery robustness of the proposed structure is improved by 200%.

In this paper, the EMI (Electro-Magnetic Interference) noise caused by the switching of the Superjunction DMOS in the flyback converter system is investigated. It is found that the radiation noise during the turn-on process is more severe than that during the turn-off process, and the turn-on behavior is not just affected by the CGS (gate source capacitance) and RG (gate driving resistance). To prove that, a theoretical discussion is performed to illustrate the turn-on behavior of the device in the flyback system and it shows that larger CGDOX (the oxide part of the feedback capacitance) can also cause more severe EMI noise, which has been verified by numerous simulations and measurements. Finally, several SJ-DMOS structures with varied CGD OX and CGS are fabricated and evaluated in the same testing system. The measurement shows that the EMI noise in the flyback system is reduced obviously with large CGS and small CGDOX, which agrees with the theoretical analysis well. This work has significant meaning for design of SJ-DMOS to reduce the EMI noise in the flyback system.