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International audience; Before metal deposit or epitaxial regrowth steps, efficient surface preparations are mandatory in order to remove both contaminants (C, F) and surface oxides. In this paper, we assess several cleaning sequences and compare their efficiency toward GaAs oxides removal. As III/V materials are very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi chamber) might be useful on GaAs surfaces. This way, the queue-time issues associated with wet surface preparations could be avoided. In this study, GaAs substrates were chemically oxidized to first characterize the oxide removal efficiency of HF, HCl and Siconi processes. Then, a new surface preparation strategy was proposed based on i) a wet chemical treatment followed by ii) a standard Siconi process. In situ Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxides and evaluate the impact of the various treatments on the GaAs surface. SIMS analyses were used to measure/quantify the efficiency of surface preparations on Carbon and Arsenic / Gallium oxides removal.

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International audience; The low temperature integration of new materials (such as SiGe channels for the holes) is mandatory in advanced metal oxide semiconductor field effect transistors (i.e. in 14 nm technology node devices and beyond). In this paper, we have investigated the removal of SiGe oxides prior to Selective epitaxial Growth of Si or SiGe:B in Sources/Drains regions. A very efficient removal of contaminants (C, F, O…) is mandatory if the H2 bake that precedes epitaxy is removed because of thermal budget constraints. As germanium is very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi® chamber) might be useful on SiGe surfaces. This way, the queue-time issues associated with “HF-Last” (HF/HCl follow by deionization water rinse) processes in single wafer wet cleaning tools are avoided. Germanium-rich SiGe layers (Si0.6Ge0.4) were used to characterize the native oxide removal efficiency of “HF-Last” and Siconi® processes. Then, a new surface preparation strategy was developed based on i) a wet chemical oxide formation followed by ii) a standard Siconi® process whose efficiency towards SiO2 has conclusively been demonstrated. Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxide and evaluate the efficiency of that treatment on carbon, germanium oxide and silicon oxide.

This paper investigates the interest of synchronous pulsed plasmas to etch silicon in HBr/O2 chemistries. Using mass spectrometry, ellipsometry and angle resolved X-ray photoelectron spectroscopy, we demonstrate that the radical concentration in the plasma, the etch rate and formation of passivation layers, can be controlled by the RF pulse parameters (frequency and duty cycle). Accordingly, pattern profiles are improved, selectivity to the mask is increased and the silicon recess is reduced from 4 to 0.8 nm when the HBr/O2 plasma lands on thin silicon oxide.

This work focuses on the impact of oxidizing (O2) and reducing plasma ashing chemistries (NH3, CH4) on the modifications of dielectric materials in a porous or an hybrid state (SiOCH matrix+porogen). The plasma ashing processes have been performed on blanket wafers using O2, NH3, and CH4 based plasmas. The modifications of the remaining film after plasma exposures have been investigated using different analysis techniques such as x-ray photoelectron spectroscopy, infrared spectroscopy, x-ray reflectometry, and porosimetric ellipsometry. For the porous material the authors have shown that NH3 and O2 plasmas induce carbon depletion and moisture uptake while the CH4 plasma only leads to important carbon depletion without moisture uptake and to the formation of a thin carbon layer on the surface. For the hybrid material, no significant material modification is evidenced with the O2 plasma while an important methyl depletion and porogen degradation are observed with reducing chemistries such as CH4 and NH3 plasmas. The impact of the porogen on the film modification and the value of the dielectric constant will be presented and discussed.This work focuses on the impact of oxidizing (O2) and reducing plasma ashing chemistries (NH3, CH4) on the modifications of dielectric materials in a porous or an hybrid state (SiOCH matrix+porogen). The plasma ashing processes have been performed on blanket wafers using O2, NH3, and CH4 based plasmas. The modifications of the remaining film after plasma exposures have been investigated using different analysis techniques such as x-ray photoelectron spectroscopy, infrared spectroscopy, x-ray reflectometry, and porosimetric ellipsometry. For the porous material the authors have shown that NH3 and O2 plasmas induce carbon depletion and moisture uptake while the CH4 plasma only leads to important carbon depletion without moisture uptake and to the formation of a thin carbon layer on the surface. For the hybrid material, no significant material modification is evidenced with the O2 plasma while an important methyl depletion and porogen degradation are observed with reducing chemistries such as CH4 and NH3 pla...

Several issues associated with plasma etching of high aspect ratio structures originate from the ions' bombardment of the sidewalls of the feature. The off normal angle incident ions are primarily due to their temperature at the sheath edge and possibly to charging effects. We have measured the ion velocity distribution function (IVDF) at the wafer surface in an industrial inductively coupled plasma reactor by using multigrid retarding field analyzers (RFA) in front of which we place 400 μm thick capillary plates with holes of 25, 50, and 100 μm diameters. The RFA then probes IVDF at the exit of the holes with Aspect Ratios (AR) of 16, 8, and 4, respectively. The results show that the ion flux dramatically drops with the increase in AR. By comparing the measured IVDF with an analytical model, we concluded that the ion temperature is 0.27 eV in our plasma conditions. The charging effects are also observed and are shown to significantly reduce the ion energy at the bottom of the feature but only with a “minor” effect on the ion flux and the shape of the IVDF.

Plasma etching has been a key driver of miniaturization technologies toward smaller and more powerful devices in the semiconductor industry. Thin layers involved in complex stacks of materials are approaching the atomic level. Furthermore, new categories of devices have complex architectures, leading to new challenges in terms of plasma etching. New plasma processes that are capable to etch ultra-thin layers of materials with control at the atomic level are now required. In this paper, the authors demonstrate that Si etching in Cl2 plasma using plasma pulsing is a promising way to decrease the plasma-induced damage of materials. A controlled etch rate of 0.2 nm min−1 is reported by pulsing the chlorine plasma at very low duty cycles. Using quasi-in-situ angle resolved XPS analyses, they show that the surface of crystalline silicon is less chlorinated, the amorphization of the top crystalline silicon surface is decreased, and the chamber wall are less sputtered in pulsed plasmas compared to continuous wave plasmas. This is attributed to the lower density of radicals, lower ion flux, and lower V-UV flux when the plasma is pulsed.

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO2, HfO2,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

With the emergence of new semiconductor devices and architectures, there is a real need to limit plasma induced damage. This study clearly demonstrates the capability of pulsed plasma technology to minimize plasma induced silicon oxidation that leads to the silicon recess phenomenon during polysilicon gate patterning. Indeed, the authors show that by pulsing optimized continuous wave overetch plasma conditions using HBr/He/O2 plasmas, the silicon recess is reduced from 0.6 to 0.2 nm, while the gate profiles are maintained anisotropic. Synchronous pulsed plasmas open new paths to pattern complex stacks of ultrathin materials without surface damage.

Patterning complex metal gate stack becomes increasingly challenging since the gate dimension for all isolated as well as dense gate structures present on 300 mm wafer needs to be controlled within the nanometer range. In this article, the authors show that SF6/CH2F2/Ar plasma chemistries to etch the polysilicon gate present very interesting critical dimension (CD) control capabilities for advanced gate etch strategies compared to commonly used HBr/O2/Cl2 plasma chemistries, thanks to the different mechanisms involved in the passivation layer formation on the gate sidewalls. Indeed, contrary to HBr/Cl2/O2 plasma chemistries, the passivation layers in SF6/Ar/CH2F2 plasmas are not formed from deposition of etch by-products coming from the gas phase but the passivating species are chemically sputtered from the bottom of the etched structures and coat the silicon sidewalls by line of sight deposition. Such mechanisms result in thin and uniform CFX passivation layers on the gate sidewalls very similar in dense...

The authors have investigated the dry etch mechanisms of complex poly-Si∕TiN∕HfO2 gate stacks and the issues that are correlated with the introduction of a thin metal layer in the gate stack. Based on atomic force microscopy (AFM) and scanning electron microscope measurements, they will first show that a mixture of HBr and Cl2 at low rf bias power is required to successfully pattern the TiN layer without damaging the HfO2 gate oxide. Second, it is demonstrated that the introduction of a metal layer in the gate stack prevents charging effects during the last etching steps of the silicon part of the gate. Transmission electron microscope measurements and x-ray photoelectron spectroscopy analyses of the gate sidewalls show that the thickness of the silicon sidewall passivation layer decreases during the O2 free metal etching step potentially inducing silicon gate profile distortion such as notch. However, the notch can be eliminated by etching the Si∕TiN gate in a single step process instead of stopping at t...

International audience; For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO2 hard mask may lead to severe profile distortions, attributed to TiFx compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.

Wafer-to-wafer reproducibility is a major challenge in gate etching processes. Periodic dry cleaning of the reactor in F-based chemistry between wafers is the most common strategy to ensure process repeatability. However X-ray Photoelectron Spectroscopy analysis of the chamber walls show that this cleaning procedure leaves AlF x species on the reactor walls, eventually resulting in process drifts and formation of particles. We have thus investigated a new cleaning/conditioning strategy of plasma etching reactors, in which the chamber walls are coated by a carbon-rich film between each wafer, allowing stable processing conditions and highly anisotropic etching profile to be achieved in advanced gate stacks. Finally, we present a new method (based on the detection of Cl 2 by laser absorption) to characterize the reactor walls conditions that could prevent process drifts.

This study is dedicated to the etching of a low-k material using the late porogen removal approach. In this approach, the porogen is removed by thermal annealing or UV curing after patterning or copper filling. Starting from a CF4 based plasma, the etch rate decreases with an Ar dilution or by adding a polymerizing gas such as CH2F2. On the other hand, the etch rate increases with O2 or N2 addition in the fluorocarbon gas mixture. X-ray photoelectron spectroscopy analyses show that the etching is controlled by the thickness of the fluorocarbon layer formed at the top surface of the hybrid material during the steady state etch regime. An etch stop phenomenon is even observed with highly polymerizing etch chemistries due to the formation of a thick fluorocarbon layer. Infrared spectroscopy analysis shows that the hybrid film is not damaged by the different etching chemistries investigated in contrast to the porous material.

This study focuses on the etching characteristics of a TiN hard mask in terms of etch rate and faceting when using a dielectric etch process. The etching experiments have been performed on blanket wafers and patterned structures in an inductively coupled plasma using a conventional CF4∕Ar based plasma. The etch rate and faceting of TiN have been measured as a function of the plasma parameters (bias power and pressure) and also plasma chemistries (Ar dilution and CH2F2 addition). The TiN etch rate is about 30nmmin−1 using the base line process conditions (70SCCM CF4, source power of 500W, bias power of 100W, and pressure of 4mTorr). Lower etch rate is observed at lower pressure and bias power and with higher Ar dilution and CH2F2 addition. The faceting is strongly reduced at lower bias power and higher pressure whereas higher Ar dilution and CH2F2 addition have no clear effect on the facet formation. Surface analysis using x-ray photoelectrons spectroscopy reveal that the top surface of TiN is mainly fluor...

International audience; Plasma etching of HfO2 at an elevated temperature is investigated in chlorine-based plasmas. Thermodynamic studies are performed in order to determine the most appropriate plasma chemistry. The theoretical calculations show that chlorocarbon gas chemistries (such as CCl4 or Cl2–CO) can result in the chemical etching of HfO2 in the 425–625K temperature range by forming volatile effluents such as HfCl4 and CO2. The etching of HfO2 is first studied on blanket wafers in a high density Cl2–CO plasma under low ion energy bombardment conditions (no bias power). Etch rates are presented and discussed with respect to the plasma parameters. The evolution of the etch rate as function of temperature follows an Arrhenius law indicating that the etching comes from chemical reactions. The etch rate of HfO2 is about 110Å/min at a temperature of 525K with a selectivity towards SiO2 of 15. x-ray photoelectron spectroscopy analyses (XPS) reveal that neither carbon nor chlorine is detected on the HfO2 surface, whereas a chlorine-rich carbon layer is formed on top of the SiO2 surface leading to the selectivity between HfO2 and SiO2. A drift of the HfO2 etch process is observed according to the chamber walls conditioning due to chlorine-rich carbon coatings formed on the chamber walls in a Cl2–CO plasma. To get a very reproducible HfO2 etch process, the best conditioning strategy consists in cleaning the chamber walls with an O2 plasma between each wafer. The etching of HfO2 is also performed on patterned wafers using a conventional polysilicon gate. The first result show a slight HfO2 foot at the bottom of the gate and the presence of hafnium oxide-based residues in the active areas.

During plasma etching processes, organic or mineral layers are deposited on the chamber walls. In general, these layers cause large and uncontrolled shifts in the etch process, which is becoming a major issue in some of the plasma processes used in integrated circuit fabrication. The chemical nature of these layers and their deposition mechanisms remain poorly understood due to the lack of in situ surface diagnostics available to monitor the reactor walls. In this article, we present a simple technique using x-ray photoelectron spectroscopy (XPS) analyses to monitor the chemical composition of the layer deposited on a sample floating on top of a 200-mm-diam wafer where the layers deposited are identical to those deposited on the chamber walls. The principle of the technique is to stick a small Al2O3 sample onto the 200-mm-diam silicon wafer, with an air gap between the sample and the wafer. Providing that the air gap is thick enough, the Al2O3 surface will be electrically floating even when the silicon wa...

Critical dimension (CD) control during silicon gate etching has been investigated with state-of-the-art chemistries. In particular, we have compared the etched profile of both isolated and dense gates obtained after the main etch step of a gate etch process using HBr/Cl2/O2 and HBr/Cl2/O2/CF4 gas mixtures, and study the influence of the CF4/O2 ratio in this mixture. We demonstrate that the gate etch profile is mainly driven by the passivation layer deposited on the gate and mask sidewalls during the etching. Due to aspect ratio dependant etching effect the passivation layer formation is thinner in dense than in isolated structures resulting in significant profile microloading. However, CF4 addition to HBr/Cl2/O2 strongly minimizes the difference in passivation layer thickness between dense and isolated lines thus potentially improving the critical dimension control. These results will be discussed in terms of chemical composition of the passivation layer and deposition mechanisms, based on previous studie...

Broadband ultraviolet absorption spectroscopy of the weak Cl2 continuum between 250 and 400 nm was used to measure the molecular Cl2 density in pure chlorine inductively coupled plasmas at pressures of 15–100 mTorr and radio-frequency (rf) power up to 800 W. The depletion of the Cl2 density was greatest at high-rf power and low pressure, and reached 80% at 15 mTorr 800 W. A simple global model was developed to explain the variation of the Cl2 dissociation rate as a function of source power and total gas pressure, and was in excellent agreement with the observations.

In less than ten years, we will be approaching the limits of the complementary metal-oxide-semiconductor technology with transistor gate length of between 10 and 30 nm. In the present article, we present a type of process allowing the design of gates having a bottom dimension smaller than the top dimension (the so-called “notched gate”). We discuss the design of the notched gate process with respect to a typical gate etch process and give some details on the sidewall passivation layer engineering. Finally, some results of critical dimension control across a 200-mm-diam wafer are shown and the potential implementation of the process in manufacturing is discussed.

We have studied the etching of low dielectric constant polymers in halogen- and sulfur-free chemistries under various plasma operating conditions. The polymer graphitization phenomenon, which corresponds to the transformation of the aromatic hydrocarbon network into an amorphous carbon backbone, has been fully investigated under several plasma conditions by in situ mass spectrometry and quasi-in situ x-ray photoelectron spectroscopy (XPS). Profile control in high aspect ratio contact holes is obtained thanks to the formation of a passivation layer on the polymer sidewalls preventing the spontaneous chemical attacks by the oxygen reactive species of the plasma. XPS studies show that the passivation layer only forms under conditions where the plasma induces a polymer graphitization. Strong correlations are observed between plasma conditions leading to the polymer graphitization, the presence of heavy carbon byproducts detected in the plasma gas phase, and the passivation layer formation.

We have studied the etching of very high aspect ratio contact holes in hydrocarbon materials SiLK™, potential dielectric candidates for the next generation of interconnections. During the etch process, slight deformation of the etch profiles such as bowing are observed. Experiments described in this article suggest that bowing originates from the deflection of ions on the sidewalls of the polymer, generating some etching. The mechanisms leading to the ion deflection on the sidewalls are presented and discussed. This study also shows how the process can be tuned to minimize the bow formation.

We have used x-ray photoelectron spectroscopy (XPS) to investigate the composition of sidewall passivation films formed during the plasma patterning of 0.1 μm silicon gates in a high density plasma source, as a function of plasma operating conditions for HBr, Cl2, and O2 based chemistry. XPS analyses clearly show that sidewall passivation films SiXxOy (X=Br, Cl, x+2y⩽4) are formed during the main step of the gate etch process and become oxidized at the early stage of the overetch step leading to an oxidelike layer after halogen desorption. Sidewall passivation films are thicker under HBr based chemistry than under chlorine containing chemistries. In addition, the film thickness seems to be highly sensitive to oxygen dilution in HBr based plasma. These results are discussed in view of the critical dimension deviation budget bearable in sub-0.1 μm gate fabrication.

Plasma etching is the most standard patterning technology used in micro- and nano-technologies. Chlorine-based plasmas are often used for silicon etching. However, the behavior of thin silicon oxide exposed to such a plasma is still not fully understood. In this paper, we investigate how a thin silicon oxide layer on silicon behaves when it is exposed to a Cl2 plasma. The authors show that chlorine atoms diffuse and/or Cl+ ions are implanted through the thin (

We have evidenced an unexpected behavior of thin gate oxide layers (thickness in the range 2–4 nm) exposed to plasma processes developed for the patterning of 0.1 μm silicon gates. During the low-energy overetch step of the process, an oxidation of the bulk underlying silicon takes place, leading to the growth of the gate oxide layer. Experimental results obtained from in situ kinetic and spectroscopic ellipsometry measurements and supported by x-ray photoelectron spectroscopy analyses are presented to highlight this phenomenon.

This article demonstrates that a 10 nm isolated silicon pattern on a very thin gate can be achieved if the plasma parameters and chemistry that impact the critical dimension (CD) control are well understood. The parameters investigated are the passivation layers that form on the silicon gate sidewalls which directly impact the CD control, the nature of the mask used during the gate process (resist mask or SiO2 hard mask), the charging effects developed when the plasma lands on a thin gate oxide.

We have used x-ray photoelectron spectroscopy (XPS) to analyze resist patterned silicon surfaces etched in a commercial 200 mm high density plasma etcher. After anisotropic etching using gate etching chemistries based on HBr/Cl2/O2 gas mixtures with or without CF4 addition, wafers are transferred under vacuum to perform chemical topography analysis using XPS in order to measure the element concentration on the silicon surfaces at the bottom of the trenches as well as the silicon sidewalls. Composition of the layers formed on the silicon sidewalls as a function of the plasma operating conditions is reported and discussed. The sidewall layer formation is mainly attributed to the oxidation of silicon etching by-products and the deposition of fluorocarbon species. Depending on the O2 and CF4 amount during a silicon gate main etch step, composition of the layer can be either SiOx-like or fluorocarbon rich. In all cases, the sidewall layer is transformed into a SiOx material during the subsequent fluorine free ...

Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.