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This paper describes a short-reach serial link to connect chips mounted on the same package or on neighboring packages on a printed circuit board (PCB). The link employs an energy-efficient, single-ended ground-referenced signaling scheme. Implemented in 16-nm FinFET CMOS technology, the link operates at a data rate of 25 Gb/s/pin with 1.17-pJ/bit energy efficiency and uses a simple but robust matched-delay clock forwarding scheme that cancels most sources of jitter. The modest frequency-dependent attenuation of short-reach links is compensated using an analog equalizer in the transmitter. The receiver includes active-inductor peaking in the input amplifier to improve overall receiver frequency response. The link employs a novel power supply regulation scheme at both ends that uses a PLL ring-oscillator supply voltage as a reference to flatten circuit speed and reduce power consumption variation across PVT. The link can be calibrated once at an arbitrary voltage and temperature, then track VT variation without the need for periodic re-calibration. The link operates over a 10-mm-long on-package channel with −4 dB of attenuation with 0.77-UI eye opening at bit-error rate (BER) of 10−15. A package-to-package link with 54 mm of PCB and 26 mm of on-package trace with −8.5 dB of loss at Nyquist operates with 0.42 UI of eye opening at BER of 10−15. Overall link die area is 686 $\mu \text{m}\,\,\times $ 565 $\mu \text{m}$ with the transceiver circuitry taking up 20% of the area. The transceiver’s on-chip regulator is supplied from an off-chip 950-mV supply, while the support logic operates on a separate 850-mV supply.

A recent trend in high-performance systems is distribution of computing across many chips and packages to sustain performance scaling while achieving high yield and alleviating power delivery. High-end data center systems and new applications like deep neural network (DNN) accelerators with scalable architecture [1] may extend the system from large chip-scale computing not just to package-scale multi-chip modules (MCM), but also to PCB-scale computing systems. An essential requirement for these distributed systems is a highly scalable low-power and high-bandwidth interconnect system, that can cover a wide range of integration and channel distances. Ideally, the same low-power links designed for ultra-short reach interconnects in MCM should be used in more challenging board-level environments.

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with fine-grained chiplets for deep learning inference, an application area with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with batch size of one, delivering inference latency of 0.50 ms.

Analog/mixed-signal (AMS) computation can be more energy efficient than digital approaches for deep learning inference, but incurs an accuracy penalty from precision loss. Prior AMS approaches focus on small networks/datasets, which can maintain accuracy even with 2b precision. We analyze applicability of AMS approaches to larger networks by proposing a generic AMS error model, implementing it in an existing training framework, and investigating its effect on ImageNet classification with ResNet-50. We demonstrate significant accuracy recovery by exposing the network to AMS error during retraining, and we show that batch normalization layers are responsible for this accuracy recovery. We also introduce an energy model to predict the requirements of high-accuracy AMS hardware running large networks and use it to show that for ADC-dominated designs, there is a direct tradeoff between energy efficiency and network accuracy. Our model predicts that achieving $\lt0.4$% accuracy loss on ResNet-50 with AMS hardware requires a computation energy of at least $\sim 300$ fJ/MAC. Finally, we propose methods for improving the energy-accuracy tradeoff.

High-speed serial links require a very high frequency clock source. Multi-rings oscillator is a practical solution to this challenge. A new phase-interpolator embedded quadrature oscillator was designed and tested. Voltage-follower based cross-coupling loops create reliable and tunable phase relationship among OSC rings. The measurement results show that the proposed PI-OSC provides 1.25/0.97 LSB INL/DNL performance at 24GHz while consuming only 8.1mW power. This compact oscillator is suitable for clock generation in high-speed low-power links.

This paper presents a highly configurable low-voltage write-ability assist implementation along with a sense-amplifier offset reduction technique to improve SRAM read performance. Write-assist implementation combines negative bit-line (BL) and $V_{\text{DD}}$ collapse schemes in an efficient way to maximize $V_{{\min}}$ improvements while saving on area and energy overhead of these assists. Relative delay and pulse width of assist control signals are also designed with configurability to provide tuning of assist strengths. Sense-amplifier offset compensation scheme uses capacitors to store and negate threshold mismatch of input transistors. A test chip fabricated in 28 nm HP CMOS process demonstrates operation down to 0.5 V with write assists and more than 10% reduction in word-line pulsewidth with the offset compensated sense amplifiers.

The current resurgence of artificial intelligence is due to advances in deep learning. Systems based on deep learning now exceed human capability in speech recognition [1], object classification [4], and playing games like Go [9]. Deep learning is enabled by powerful, efficient computing hardware [5]. The algorithms used have been around since the 1980s [7], but it has only been in the last few years - when powerful GPUs became available to train networks - that the technology has become practical. This paper discusses the circuit challenges in building deep-learning hardware both for inference and for training.

While high-speed single-ended signaling maximizes pin and wire utilization within on- and off-chip serial links, problems associated with conventional signaling methods result in energy inefficiencies. Ground-referenced signaling (GRS) solves many of the problems of single-ended signaling systems and can be adapted for signaling across RC-dominated channels and LC transmission lines. The combination of GRS and clock forwarding enables simple but efficient signaling across on-chip communication fabrics, off-chip organic packages, and off-package printed circuit boards. Various methodologies compatible with GRS are presented in this paper, including design considerations and various circuit architectures. Experimental results for multiple generations of GRS-based serial links are presented, which includes a 16Gb/s 170fJ/b/mm on-chip link, a 20Gb/s 0.58pJ/b link across an organic package, and a 25Gb/s 1.17pJ/b link signaling over a printed-circuit board.

Point of load regulators, with fast response to load transients, are becoming critical components in low power systems. Linear regulators are an area-efficient way to implement fast-response regulation as they require only the transistors and capacitors available in any standard CMOS process. This paper presents a switching linear regulator with a comparator that samples the difference between the regulated voltage and the reference (error) at 4GHz. The comparator uses a novel self-clocking scheme to achieve extremely low probability of meta-stability, even at very high clock frequency. In fast transient mode, the regulator achieves zero droop when the load current steps from < 1mA to 170mA in 100ps. A digital ripple control mechanism, and an analog ripple control module work together to reduce the ripple on the regulated output. The regulator, fabricated in TSMC's 16nm finFET technology, achieves a peak current efficiency of 97.6% when operating at 4GHz.

Toward the end of the Moore's-law era, increases in system complexity will rely more heavily on packaging technology. Systems will increasingly comprise multiple chips that must be linked by high-speed data channels carrying a substantial fraction of on-chip bandwidth. To take advantage of inexpensive organic packages and conventional printed circuit (PC) boards, data links that are both energy and pin efficient are needed. A link between neighboring packages is by far the more challenging application due to increased cross-talk, signal attenuation, and reflections from impedance discontinuities. The combination of signal integrity challenges and production margining requires increased amplitude, equalization, ESD protection, and PVT-tolerant circuit design techniques.

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based V MIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V.

Supply voltage integrity during a load transition is a critical problem. Droop on the supply may lead to logic failures, and overshoot can reduce reliability. Voltage deviations from the nominal forces designers to apply margins in design to ensure correct operation. This paper addresses two main causes of droop/overshoot on the supply line namely the sluggish converter response and the parasitics between the converter and the load. We present current parking regulator (CPR), a voltage down-converter with almost zero droop or overshoot during a load transient along with implementation techniques to nullify the effect of the parasitics. The underlying principle involves avoiding the inductor slewing time by parking sufficient excess current in the inductor, which is available to use immediately when the need arises. The system design involves on-die, package, and PCB co-design to minimize the impact of parasitics. Measurement results show negligible droop/overshoot when the load current transitions from 0.8A to 7.5A and vice versa in 2ns with only 200nF of load capacitance on the regulated output voltage node. The design was fabricated in a 28nm CMOS technology and integrated in the same package as the load using an 8 layer substrate. It achieves a peak efficiency of 83% at 8A load current.

Signaling over chip-scale global interconnect is consuming a larger fraction of total power in large processor chips, as processes continue to shrink. Solving this growing crisis requires simple, low-energy and area-efficient signaling for high-bandwidth data buses. This paper describes a balanced charge-recycling bus (BCRB) that achieves quadratic power savings, relative to signaling with full-swing CMOS repeaters. The scheme stacks two CMOS repeated wire links, one operating in the Vtop domain, between Vdd and Vmid=Vdd/2, the other, Vbot, between Vmid and GND. Unlike previous work [1], we require no voltage regulator to maintain the Vmid voltage at Vdd/2, to compensate for differences in data activity in Vtop and Vbot domains. The BCRB also uses simple single-ended signaling, to achieve higher bandwidth per unit bus width than differential buses [2] and lower signaling energy than precharging schemes [3], since we take full advantage of low switching activity and bus-invert coding.