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This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation (PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The principle analysis shows that the fractional-spaced FFE can provide an extended compensation range beyond the Nyquist frequency without amplifying noise. For the transmitter prototype implementation, the tap delay is adjusted by a coarse–fine capacitor array-based delay cell located in the quarter-rate clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 multiplexers are employed to guarantee an adequate timing margin and a sufficient bandwidth for the data rate of 112 Gb/s. A linearity-optimized FFE driver is employed to overcome the current compression caused by the channel-length modulation. Fabricated in a 65-nm CMOS process, the measurement results show that the proposed fractional-spaced FFE can significantly improve the eye-opening in terms of expanding the eye width and optimizing the eyelid thickness. The PAM-4 transmitter can operate in both full-rate PAM-4 and half-rate NRZ modes, achieving a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.

This article presents a complete frequency-domain model for injection-locked oscillators (ILOs), which is applicable to all ILO topologies. Based on the essence of the phase accumulation within ILOs, an equivalent linear frequency-domain feedback loop is constructed. By introducing an injection factor that depicts the proportion of the phase shift perturbation with respect to the injection phase disturbance, the phase transfer function (PTF)/noise transfer function (NTF) and tracking bandwidth equation of ILOs are formulated. In addition, a general single transient simulation-based injection factor-extraction procedure is proposed. Theoretical analysis for the injection factor based on both traditional vector diagram and the impulse sensitivity function is also demonstrated. Based on a ring oscillator-based pulse ILO fabricated in a 65-nm CMOS process, the deduced PTF/NTF, tracking bandwidth equation, and their properties are verified using the simulated results and measured phase noise, respectively.

This paper presents a 20 GHz subharmonic injection-locked clock multiplier (SILCM), which adopts a mixer based self-align injection timing control loop to guarantee the optimal injection point. In addition, to further improve the injection time accuracy and reduce the super, a V/I mismatch cancellation are utilized. Furthermore, a frequency-locked loop with a frequency-lock detection and enable control switch is employed to expand the injection-locked range and save power. Fabricated in a 65 nm CMOS technology, the SILCM can lock from 19.2 GHz to 23.2 GHz. It exhibits − 125.5 dBc/Hz phase noise at 1 MHz offset and consumes 8 mW under 1.2 V power supply. The measured root-mean-square jitter integrating from 0.1 kHz to 100 MHz is 106 fs and the reference spur is − 43 dB.

This paper presents a power scalable clock data recovery (CDR) suitable for multilane and multirate applications. To make the power consumption scale with the data rate and guarantee appropriate edge overlaps for the phase interpolation, a delay-locked loop-based global biasing strategy is proposed to automatically adjust the bandwidth of the current-mode logic buffers and phase interpolator (PI). The I, Q clocks are generated by a local clock conditioner, which employs an open-loop voltage-controlled delay line to produce the evenly spaced multiple phases and adopts a two-stage timing averaging to correct the duty cycle distortion and I, Q mismatch. Additionally, a phase-compensating technique is adopted in the PI to optimize its linearity. Implemented in a 65-nm CMOS process with an area occupation of 0.12 mm2, the presented CDR can operate from 2 to 10 Gb/s with a scalable power consumption from 11 to 42 mW. When it operates at 10 Gb/s, the maximum tolerable amplitude of the sinusoidal jitter at 50 MHz is 0.52 UIpp, and the total jitter of the recovered clock is 16.6 ps at a BER of 1e-12.

This paper presents a 32 Gb/s low power little area re-timer with Phase Interpolator (PI) based Clock and Data Recovery (CDR). To further ensure signal integrity, both a Continuous Time Linear Equalizer (CTLE) and Feed Forward Equalizer (FFE) are adapted. To save power dissipation, a quarter-rate based 3-tap FFE is proposed. To reduce the chip area, a Band-Band Phase Discriminator (BBPD) based PI CDR is employed. In addition, a 2-order digital filter is adopted to improve the jitter performance in the CDR loop. This re-timer is achieved in 65 nm CMOS technology and supplied with 1.1 V. The simulation results show that the proposed re-timer can work at 32 Gb/s and consumes 91 mW. And it can equalize >−12 dB channel attenuation, tolerate the frequency difference of 200 ppm.

This paper presents a 20 GS/s four-channel time-interleaved sample-and-hold amplifier (SHA), which aims to improve the harmonic distortion performance, eliminate the common-mode voltage fall in track-to-hold transition, and solve the difficulty of timing mismatch calibration among different sampling channels. In data path, the harmonic distortion of the track-hold switch is optimized by introducing a distortion-improving resistor into the switched emitter follower. The common-mode voltage fall is eliminated by an inserted delay-regulating resistor. Additionally, broadband data buffers are utilized to further guarantee a wide bandwidth. In clock path, an interpolator-based phase regulator in analog domain is implemented to calibrate the timing mismatch, hence avoiding the large area cost and complicated algorithm in the digital domain. Fabricated in a 0.18 &mu, m SiGe BiCMOS process, the experimental results show that the SHA achieves a bandwidth of 16 GHz and a total harmonic distortion of &minus, 39.6 to approximately &minus, 51.8 dB with a &minus, 3 dBm input. By applying the proposed sampling phase regulator, the timing mismatch can be optimized to satisfy the requirement of 6-bit resolution at a 4 &times, 5 GS/s sampling rate. The proposed SHA shows prominent performance on both bandwidth and linearity, which makes it suitable for ultra-high-speed communication networks.

This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time linear equalizer as the analog front end and integrates a low-cost sign-based zero-forcing engine relying on edge-data correlation to automatically adjust the tap weights of the TX-FFE. By embedding low-pass filters with an adaptively adjusting bandwidth into the data-sampling path and adopting high-linearity compensating phase interpolators, the clock data recovery achieves both high jitter tolerance and low jitter generation. The fabricated TX and RX chipset delivers 40-Gb/s PRBS data at BER 16-dB loss at half-baud frequency, while consuming a total power of 370 mW.

This letter presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter with a 2-tap fractional-spaced feed-forward equalizer (FFE) implemented in a 65-nm CMOS process. The tap delay is adjusted by a coarse-fine capacitor array-based delay cell located in the clock path. Dynamic latches, pseudo-AND2s, and bandwidth-enhanced 4:1 MUXs are employed to guarantee an adequate timing margin and a sufficient bandwidth for the 112-Gb/s design. The measurement results show that the fractional-spaced FFE can significantly optimize the eye opening. The fabricated PAM-4 transmitter achieves a maximum data rate of 112 Gb/s with an energy efficiency of 2.17 pJ/bit.

This paper presents a 4-40 Gb/s PAM-4 transmitter using a novel hybrid driver. Different from conventional current-mode (CM) drivers with poor linearity and source-series terminated (SST) drivers with limited differential output swing, the proposed hybrid driver delivers a differential output swing exceeding the supply voltage with high linearity using a combination structure of the CM and SST driver. In addition, a 4-40 Gb/s quarter-rate transmitter with one-tap feedforward equalization is designed in 65nm CMOS technology using the hybrid driver, yielding a 1.8V differential peak-to-peak output swing at 1.2 V supply voltage with a 96.4% ratio of level mismatch.

A 10 GHz 4-phase ring-VCO based injection-locked clock multiplier (RILCM) for 40 Gb/s SerDes application is presented in this paper. The RILCM adopts two loops which share common part circuit to realize the injection lock. The first loop which is the frequency lock loop (FLL), drags the VCO's free-running frequency to the injection lock-in range. Another loop which is the injection timing control loop (ITCL), controls the injection timing of the pulse to reduce the race condition and improve the phase noise. The RILCM is designed in a 65nm CMOS technology and supplied with 1.1V. The simulation results show that the proposed RILCM can provide 4-phase 10 GHz clocks with 3.61ps total jitter, at this time the total consumption is 17 mW.

An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the edge and data information generated by the middle slicer for extraction the phase error between the data and clock. The receiver is designed in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed PAM4 receiver can work at 80 Gb/s with 235mW consumption.

A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of 6.1 ps after a 17 dB loss channel at 60Gb/s.

This paper presents a 56 Gb/s 4-level pulse amplitude modulation (PAM4) wire-line receiver, which employs a quarter rate architecture. By employing a ring voltage control oscillator (VCO) based clock and data recovery (CDR) with separate proportional path, the complexity, power consumption and area can all be reduced. To reduce the noise of the detector and improve the stability of the CDR, both the major and minor transitions with the central crossover point are utilized to extract the phase error. The receiver is designed in a 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed PAM4 receiver can work at 56 Gb/s with 76 mW consumption.

This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation (PAM4) and consumes 173mW at 80 Gb/s.

This paper presents a wideband LC PLL designed for multi-protocol serial link applications. Dual LC voltage controlled oscillator (VCO) cores are used to cover a wide frequency range while keeping a high Q factor of the LC tank, and multi-ratio dividers are used to satisfy the multi-protocol requirements. Each LC VCO adopts a 4-bit switch capacitor to increase the frequency tuning range and decrease the VCO gain. Meanwhile, the phase frequency detector (PFD), charge pump, and loop filter (LPF) are fully differential to suppress the ground and substrate noise. The PLL is implemented in SMIC 40nm CMOS technology and covers an area of 0.32mm2. The two VCOs' free running phase noise at 1MHz are −108.1dBc/Hz and −105.7dBc/Hz respectively. The whole power of the PLL under 1.1V supply is 19.52mW, comprising 4.56mW of the VCO and 14.96mW of the other parts.

This paper presents a low jitter ring-VCO based injection-locked clock multiplier (RILCM) with a phase-shift detection based hybrid frequency tracking loop (FTL). A full-swing pseudo-differential delay cell (FS-PDDC) is proposed to lower the device noise to phase noise conversion. To obtain high operation speed, high detection accuracy, and low output disturbance, a compact timing-adjusted phase detector (TPD) tightly combining with a well-matched charge pump (CP) is designed. Additionally, a lock-loss detection and lock recovery (LLD-LR) scheme is devised to equip the RILCM with a similar lock-acquisition ability to conventional PLL, thus excluding the initial frequency setup aid and preventing potential lock loss. Implemented in 65 nm CMOS, the RILCM occupies an active area of 0.07 mm2 and consumes 59.4 mW at 10 GHz. The measured results show that it achieves 56.1 fs rms-jitter and −57.13 dBc spur level. The calculated figure-of-merit (FOM) is −247.3 dB, which is better than previous RILCMs and even comparable to those large-area LC-ILCMs.

This paper presents a 4–40 Gb/s current mode PAM4 transmitter with an optimized eye linearity. By embedding an additional mixed combiner and an extra current source into the output driver and developing a coherent scaled-replica based bias generator, the channel-length modulation caused tail-current variations for both DC and AC coupling modes can be effectively compensated. Implemented in 65 nm CMOS, the transmitter occupies an area of 1.02 mm2 and consumes 102 mW at 40 Gb/s. After applying the proposed linearity optimization, the measured eye linearity can be optimized from 1.28 to 1.01 with a single-end swing of 480 mV in AC coupling mode.

This paper presents a 5-50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4:1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming technique is designed. Implemented in 65 nm CMOS technology, the transmitter occupying an area of 0.6 mm2 achieves a maximum data rate of 50 Gb/s with an energy efficiency of 3.1 pJ/bit.