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Source degenerative feedback is extensively applied in the low-noise amplifier design. The beneficial effects of this technique are well established in the open literature. However, the designer is often left to trial-and-error or optimization procedures to identify the adequate amount of feedback when other linear requirements, such as signal matching, come into play. This issue is even more relevant in multistage designs. In this article, we present a synthesis procedure and the relevant design chart to identify the optimum feedback inductor value on all transistors of an $N$ -stage amplifier to obtain a perfect match at its external ports in conjunction with amplifier noise figure minimization and a specified gain requirement. It is shown that the method is applicable to arbitrary $N$ values although it becomes more elaborate for $N$ greater than 6. The method is deterministic as opposed to optimization or trial-and-error-based procedures. The design flow is illustrated at first through a four-stage design with ideal matching elements and subsequently validated by an monolithic microwave integrated circuit (MMIC) test vehicle designed and realized in the WIN foundry’s Gallium Arsenide PIH1-10 process. The measured performance of the test vehicle is NF = 1.9 dB, 26 dB gain, typical I/O return loss of 15 dB in the 26.5–29.5-GHz bandwidth, and practically ideal behavior at the design frequency of 28 GHz.

This article addresses the classical problem of determining the extrinsic resistances ( $R_{G}$ , $R_{S}$ , and $R_{D}$ ) of field-effect transistors (FETs) and, in particular, of high-electron-mobility transistors (HEMTs). The presented approach relies on small-signal measurements of open-channel transistors, as often proposed both for traditional metal–semiconductor FETs (MESFETs) and HEMTs. Unlike what is common practice with HEMTs, the method proposed here does not oversimplify the model of the active channel. On the contrary, we retrieve from the literature a possible analytical model for the open-channel HEMT and use it to determine the triplet of extrinsic resistances without the need of stressing the gate junction with too high currents. Another result of the approach, valid both for MESFETs and HEMTs, is a deterministic way to remove the contribution of the gate junction from the small-signal parameters of the measured devices. All extractions process data that are available on suitable ranges in frequency or in bias voltage, without taking to the limit the sweep parameters or seeking specific resonances. Also, optimizations are only allowed to refine the nominal values, not as the main technique of extraction. These goals are achieved by setting up different subproblems in the form of overdetermined linear systems and then solving by pseudoinversion. The validity of the approach is demonstrated on the measurements of devices from advanced HEMT technologies realized by OMMIC, both GaAs-based (40-nm gate length) and GaN-based (100 and 60 nm).

In this letter, we present the design of a V- band low-noise amplifier for intersatellite crosslink receivers. The test vehicle, realized on industrial metamorphic gallium arsenide technology, operates from 57 to 66 GHz exhibiting 23-dB gain and an average 1.8-dB noise figure. Particular attention was devoted to the analysis and synthesis of an alternative bias injection topology to obtain a sharp gain roll-off at lower frequencies, thus avoiding the insertion, at system level, of an image-reject filter.

This paper is focused on the extraction of the noise parameters of a linear active device by exploiting both forward and reverse noise power measurements associated with different terminations. In order for load-pull measurements to yield a significant marginal improvement (as compared to forward measurements only) it is expected that the device under test should appreciably deviate from unidirectionality. For this reason, the source/load-pull technique is applied to frequencies at which the considered devices are still usable but their reverse noise factor exhibits a measurable dependence on the output terminations. Details on the test bench set up to the purpose, covering the 20–40 GHz frequency range, are provided. A characterization campaign on a 60 nm gate length, 4×35 µm GaN-on-Si HEMT fabricated by OMMIC is illustrated.

Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC&rsquo, s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader&rsquo, s convenience.

In this work, a Ka-Band MMIC LNA designed with two different gate length GaN-on-Si devices is shown. Measurements show a gain higher than 29dB, 2.1dB average NF in the 34÷37.5GHz design band and a 1dBcp around 23-24dBm in the 35÷36.5GHz target band, showing a good suitability to highgain, low-noise and medium-power requests. Comparison with GaN-on-SiC-based similar works confirms the feasibility of the adoption of GaN-on-Si technology for space-borne applications.

Design solutions and technology considerations of a 6–52 GHz cascode distributed amplifier are presented in this paper. The amplifier is designed in a Gallium Nitride on Silicon process with two different gate length transistors, namely 60 nm and 100 nm, connected in cascode configuration. The test vehicle, whose additional aim is to show the possibility to integrate transistors with different gate lengths onto the same chip, demonstrates 9 dB gain, 28 dBm saturated output power, 20% PAE and 37 dBm IP3, on average. Comparison with Gallium Nitride on Silicon Carbide based similar works reveals satisfactory performance obtained however on a cost effective and high volume production substrate.

In this paper, a Single-Chip Front-End (SCFE) operating in Ka-Band (35–36.5 GHz) is presented. Chip is designed exploiting a GaN-on-Si technology featured by 100nm gate length provided by OMMIC foundry. This MMIC integrates high-power, low-noise amplification functionalities enabled by a couple of synchronous Single-Pole Double-Throw (SPDT) switches, occupying a total surface of 4.7×3 mm2. Transmit-mode (Tx) performance present a 36 dBm output power, a Power Added Efficiency (PAE) higher than 25% and a 20dB power gain at 2 dB compression. Regarding the receiving-mode (Rx) performance, a sub-3.2 dB Noise Figure (NF) and a linear gain just below the 32 dB level is obtained, with a I/O matching better than 20 dB, as well.

In this paper a GaN-on-Si MMIC Low-Noise Amplifier (LNA) working in the Ka-band is shown. The chosen technology for the design is a 100 nm gate length HEMT provided by OMMIC foundry. Both small-signal and noise models had been previously extracted by the means of an extensive measurement campaign, and were then employed in the design of the presented LNA. The amplifier presents an average noise figure of 2.4 dB, a 30 dB average gain value, and input/output matching higher than 10 dB in the whole 34&ndash, 37.5 Ghz design band, while non-linear measurements testify a minimum output 1 dB compression point of 23 dBm in the specific 35&ndash, 36.5 GHz target band. This shows the suitability of the chosen technology for low-noise applications.

A MMIC demonstrator for RF phase and amplitude control with on board 18-bit serial to parallel conversion (Multi-Functional Chip) is presented. Thanks to an alternative digital building block topology, the DC power consumption of the digital serial to parallel converter is noteworthy: less than 43 mW (2 mW/bit). The main RF performances are 0° – 360° phase coverage and 0 dB – 31.5 dB attenuation setting, in the 7.6 GHz – 9.1 GHz operating bandwidth. The circuit, whose area is 6 mm2, is realised in an industrial and commercially available GaAs technology. This component can be used in active electronically scanned arrays for beam steering.

The feasibility of a W-band (81-86 GHz) downconverter for space-borne communications is verified in this paper through the design of a custom MMIC chip-set. The latter is composed of three functionalities: a low-noise amplifier (LNA), a sub-harmonically pumped mixer (SHM), and an active frequency doubler that provides the local oscillator (LO) pump to the mixer. The MMICs have been designed with OMMIC’s 70 nm and UMS’s 100nm GaAs technologies, in order to exploit the best-of-both technologies (low-noise and power-handling at millimetre-wave). The LNA features 23 dB gain and sub-2.5 dB Noise Figure in the whole operating band, while the mixer shows 13 dB conversion loss (CL). Finally, the active doubler provides > +10dBm pump at the necessary LO frequency.

In this paper, the feasibility of a V-band MMIC chipset is tested by the design of a Low-Noise Amplifier (LNA) operating in the 59-66 GHz frequency band and two Mixers exploiting two different topologies that convert signals from the 60-60.4 GHz band to 8-8.4 GHz band and vice versa. The MMICs have been designed exploiting OMMIC’s 70 nm and 130 nm GaAs technologies. LNA shows a 23 dB gain and a sub-2 dB Noise Figure in the whole operating band, while the two Mixers show a 11-12 dB conversion loss, along with LO isolation towards RF and IF port higher than 22 dB and a simulated Input 1 dB Compression Point of 10 dBm.

Global automotive fuel economy and emissions pressures mean that 48 V hybridisation will become a significant presence in the passenger car market. The complexity of powertrain solutions is increasing in order to further improve fuel economy for hybrid vehicles and maintain robust emissions performance. However, this results in complex interactions between technologies which are difficult to identify through traditional development approaches, resulting in sub-optimal solutions for either vehicle attributes or cost. The results presented in this paper are from a simulation programme focussed on the optimisation of various advanced powertrain technologies on 48 V hybrid vehicle platforms. The technologies assessed include an electrically heated catalyst, an insulated turbocharger, an electric water pump and a thermal management module. The novel simulation approach undertaken uses an integrated toolchain capturing thermal, electrical and mechanical energy usage across all powertrain sub-systems. Through integrating 0-D and 1-D sub-models into a single modelling environment, the operating strategy of the technologies can be optimised while capturing the synergies that exist between them. This approach enables improved and more informed cost/benefit ratios for the technologies to be produced and better attributes by identifying the optimum strategy for the vehicle. The results show the potential for CO2 reductions in the range of 2-5% at no additional cost, through co-optimisation of the technologies in a single simulation environment. The simulation work forms part of the THOMSON project, a collaborative research project aiming to develop cost effective 48 V solutions, in order to reduce the environmental impact of the transportation sector.

This paper provides an assessment between two MMIC foundry processes for millimetre-wave high-performance receiver applications, namely, OMMIC’s 70 nm GaAs and 60 nm GaN-on-Si processes. To do so, a characterization and modelling campaign was carried out on transistors provided by OMMIC for the two processes, whose commercial names are D007IH (70 nm GaAs) and D006GH (60 nm GaN). The resulting models were employed to design several test vehicle Low-Noise Amplifiers (LNA) operating above 30 GHz. The GaAs LNAs have been manufactured and characterized, while the GaN-on-Si LNAs are being manufactured. The initial outcome of the assessment is that GaAs is still ahead if Noise Figure is the crucial and mandatory requirement. GaN-on-Si, on the other hand, proves to be a viable solution if a – slightly – higher Noise Figure is acceptable. Moreover, the benefits of GaN-on-Si, with respect to GaAs, are higher robustness, output power, linearity, and higher integration capability with CMOS technologies.

In this paper a MMIC Low-Noise Amplifier operating in Ka-band is presented. The chosen technology is a 100 nm GaN HEMT on a High Resistivity Silicon substrate. A fully deterministic approach based on constant mismatch circles has been used for the preliminary synthesis of matching networks. The designed four-stages LNA presents a 33 dB gain, Input/Output matching better than 21 dB and a Noise Figure of no more than 2.3 dB in the whole operating band, showing the suitability of the chosen technology to low-noise, high gain and linearity applications.

In this paper, a times four K- to W-Band frequency multiplier involved in the generation of a Local Oscillator signal is presented. The chosen technology for this design is the D01MH, a metamorphic GaAs mHEMT with a 0.13 µm channel length. The designed MMIC is expected to convert a 5 dBm, 23–24 GHz input signal into a 11 dBm, 92–96 GHz output signal. Simulations show an output power harmonic suppression over 50 dBc between the desired and unwanted ones. Input and Output matching respectively better than 13 and 16 dB is expected. The MMIC occupies an area of 3 × 2 mm2, and is currently being manufactured.