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This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- $\mu \text{W}$ power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8. [ABSTRACT FROM AUTHOR]

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62- $\mu \text{W}$ power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively. [ABSTRACT FROM AUTHOR]

This article presents a low-power code-recombination (CR) analog-to-digital converter (ADC) with generic feature extraction for wearable electrocardiogram (ECG) sensors in wireless body sensor network (WBSN) applications. The CR ADC features a search forward procedure (SFP) and a search backward procedure (SBP) to hunt for part of the quantization steps cutting down bitcycle and power consumption. Also, CR ADC outputs a digital stream named $K$ data served as a compressed feature. A prototyped chip including a proposed ADC is fabricated in a 0.13- $\mu \text{m}$ CMOS process. With a 0.6-V supply voltage and a 10-kS/s sampling rate, the measured signal-to-noise-distortion range (SNDR) and spurious-free dynamic range (SFDR) are 58.34 and 70.2 dB, respectively. The ADC consumes only 40-nW power when input residue is within the prediction range defined by ADC’s resolution and the reference voltage, achieving a figure-of-merit (FoM) of 6.2 fJ/conversion-step. The data $K$ occupy 2/5 of the raw data and are conducted to categorize cardiovascular diseases illustrating at least 96% accuracy. [ABSTRACT FROM AUTHOR]

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed, low-jitter, and high-precision clock receiver circuit (CLKRX) for time-interleaved ADCs with a sampling rate of 4 GS/s operating in the 3–5 GHz frequency range. The CLKRX circuit is composed of a continuous-time linear equalizer (CTLE) and a duty-cycle corrector (DCC). The CTLE featuring active feedback, negative Miller capacitance, and source-follower feedback is capable of enhancing the bandwidth, and improving the quality of the high-speed clock. Whereas the 3–5 GHz DCC module contains a common-mode voltage correction circuit and a wideband amplifier that corrects the input signal's duty cycle ranging from 20% to 80%. A second-order duty-cycle detection circuit is used in the feedback loop, which significantly improves the range and accuracy of duty-cycle correction and greatly reduces duty cycle jitter.The clock receiver circuit proposed in this paper was verified in a 28 nm CMOS process, and the test results show that the output duty cycle is corrected to 50 ± 0.1% within the input duty cycle range of 20–80% (3–5 GHz). [ABSTRACT FROM AUTHOR]

A high-linearity input-buffer with high output common-mode stability for 10-bit 3.2 GS/s ADC is proposed in this Letter. The buffer is mainly composed of a source follower for strong driving ability. To enhance its linearity, a feed forward signal path from input to output is proposed. A replica buffer-based common-mode feedback is designed to achieve high output common-mode stabilisation of input-buffer. The prototype is implemented in 40 nm CMOS process. The output common-mode variation is reduced from 200 to 1 mV. Input-buffer consumes 96 mW in 3.2 GHz sampling rate and achieves 69.3 dB spur-free dynamic range at 1581 MHz input frequency. [ABSTRACT FROM AUTHOR]

This paper presents a power and area efficient pseudo single ended switching ADC for portable biomedical signal monitoring applications. The switching method features an 8-bit binary-weighted DAC array with a novel layout method called limited bottom-plate routing (LBPR) maintaining both feasibility and symmetry, a dynamic biased comparator and dynamic control logic. As a result, the proposed ADC saves 96.7% power consumption and 87.5% area occupation compared with conventional SAR ADC. Also, a novel DAC array layout method is promoted maintaining both feasibility and symmetry. A prototyped chip including a proposed ADC is fabricated in a 0.13 μm CMOS process. On condition of 0.6 V supply voltage and 10 kS/s sampling rate, the measured signal-to-noise-distortion (SNDR) and spurious free dynamic range (SFDR) are 57.8 dB and 64.3 dB, respectively. Besides, the ADC consumes only 40 nW power and 0.053 mm2 area achieving a figure-of-merit (FoM) of 6.26 fJ/conversion-step. Low power and low area occupation make it a good candidate for biomedical signal monitoring applications. [ABSTRACT FROM AUTHOR]

This paper presents a second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing the error-feedback (EF) structure. With the finite impulse response (FIR) filter based on a single operational transconductance amplifier (OTA), it realizes noise transfer function (NTF) zeros optimization. The specifications of OTA are relaxed without high-gain and fast-settling. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-coded 4-bit MSBs are implemented with the data weighted averaging (DWA) technique. The overall architecture is simple and robust. It does not need additional complicated digital calibrations, and only requires minor modifications to the standard SAR ADC. Design and simulation in a 130 ​nm CMOS process, the prototype consumes 96 ​μW of power when operating at 1 ​MS/s sampling frequency. The proposed ADC achieves peak Schreier FoM of 165 ​dB with 76.95 ​dB signal to noise and distortion ratio (SNDR) and 97.34 ​dB spurious free dynamic range (SFDR) at an oversampling ratio (OSR) of 8. [ABSTRACT FROM AUTHOR]