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The article presents information on low-cost programmable gate arrays. Now nothing will impede the field-programmable gate array's (FPGA) march into scores of volume applications. New architectures both lower the cost and improve functionality, enabling them to cost-effectively compete with application specific integrated circuits (ASICs). Smaller process geometries that shrink chip size go a long way toward reducing cost. But size isn't the only factor in the cost equation. Also driving the use of programmable devices is the shorter product life of many mass-market products. With ASICs, designers typically must allow for manufacturing cycle times of a month or more. Then there are the nonrecurring-engineering (NRE) costs. Programmable logic devices combat all of the above issues. These off-the-shelf parts have no significant NRE charges. If the system is designed properly, they can be updated in the field to correct system flaws or add new features. The per-chip costs might be higher than those of an ASIC, but after considering these other factors, FPGAs become a more cost-effective solution. To further the trend, all companies that offer FPGAs have developed families of low-cost devices that now target mass-market applications.

This article focuses on application specific integrated circuits (ASIC). The rules of the ASIC game are changing as the cost to fabricate a custom solution creeps past the million-dollar mark. And, new rules are emerging due to the shorter market life of the end system and the continuous need to upgrade or update a product's features. Device cost is always a key factor for filed programmable gate arrays (FPGAs), especially those used in the final version of a product. The high-density, resource-rich, top-of-the-line FPGAs tend to cost several hundred dollars to over a $1000 apiece, even in moderate volume. INSETS: FPGAs ENTER NEW DESIGN TERRITORY;STRUCTURED ASICs COMPETE WITH, AND COMPLEMENT, FPGAs.

Over the last half decade, a new class of configurable application specific integrated circuits (ASIC) has made inroads by bridging the performance and cost gap between designs based on full custom ASIC and high density field programmable gate arrays (FPGA). Known as platform and structured ASICs, these system-on-a-chip solutions are some of the best aspects of custom ASIC and FPGA. As a result, designers have a quick time-to-market option that features lower development costs than ASIC and higher performance and often lower unit costs that FPGAs.

Focuses on designs of field programmable gate arrays. Challenges facing application specific integrated circuits system-on-a-chip design; Megagate competition. INSET: MEGAGATE FPGAs.

Reports on a second-generation family of low-density FPGA, QuickLogic's pASIC 2 series, that offers 3000 up to 20000 usable gates, datapath speeds exceeding 200 MHz and counter speeds that go beyond 150 MHz without increasing chip area or slowing the logic. Three-layer metallization scheme created to achieve denser interconnections for the logic; Design of the pASIC 2 series. INSET: Not the only three-level metal antifuse solution..

Describes the capabilities of reconfigurable computer fabric to replace application specific integrated circuits and field programmable arrays for base-station signal processing and other applications. Specification of the multiplier-accumulator and other computer resources; Development of computational array.