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The technology development, combined with chip size reductions, has significantly increased power density. Furthermore, the power limitation in portable devices has increased the importance of power consumption considerably. Approximate computing as an emerging paradigm leverages the error resiliency of applications to decrease power consumption. In this paper, we propose four approximate 4:2 compressors. We utilize the gate diffusion input to achieve significant area reduction in the proposed compressors. Afterward, we employ these compressors in the structure of Dadda multipliers. Compared to the state-of-the-art works, the proposed compressors result in, on average, 45% and 42% higher accuracy and lower area, respectively. Circuit simulations were carried out at a 32-nm carbon nanotube field-effect transistor technology node by HSPICE. The comparisons between our proposed compressors and exact compressor indicate that there has been an average improvement of 55%, 60% and 46% in the number of transistors, power consumption, and delay, respectively. In addition, the proposed multipliers were used in three image processing applications, including image multiplication, sharpening, and smoothing. The results show up to 46% and 70% improvement in the mean structure similarity index metric and peak signal-to-noise ratio compared to the state-of-the-art. [ABSTRACT FROM AUTHOR]

This paper proposes a configurable reduced worst-case error approximate adder, named BEAD (B ounded E rror A pproximate A d der). The proposed adder is based on segmentation and carry speculation methods to cut long critical paths. Furthermore, a high accuracy speculation method is proposed to calculate the sum bits. However, the data of real-world applications is often not uniformly distributed, which leads to taking values that result in a worst-case error of the approximate adder quite frequently; therefore, considerable distortion occurs at the output. To overcome this, the carry prorogation scheme of the BEAD is such that the error distance is bounded to a given value, which makes it more accurate rather than prior works. Specifically, the BEAD offers a smaller worst-case error in addition to improved mean relative error distance. The results show between 50% and 80% smaller maximum error compared to the related works. Also, by synthesizing the different adders using a 15-nm FinFET technology, the results demonstrate that the BEAD has at least 30% area saving compared to the exact adder in the various studied configurations. The proposed adder achieves the almost lowest figure of cost (FoC) compared to state-of-the-art approximate adders. Moreover, BEAD's evaluation in image processing and DCT applications shows its great superiority over recently proposed structures. • Porposing an approximate adder based on segmentation and carry speculation methods. • Proposing a high precision speculation method to calculate the sum bits. • Bounding the error distance achieving in a smaller worst-case error. • Achieving the lowest figure of cost compared with prior approximate adders. [ABSTRACT FROM AUTHOR]

Approximate computing is one of the promising techniques in error-resilient applications to overcome high-density integration challenges, such as energy consumption and performance. Multipliers constitute a significant portion of computer arithmetic units, leading to considerable energy and time consumption. In this paper, we propose low-power and compact approximate compressors for composing approximate Dadda multiplier structures, including compressors, half adders, and full adders, which utilize three-phase partial product compression: truncated, approximation, and exact columns. In approximate columns, we consider approximate compressors derived from the truth table of the exact 4:2 compressor and simplified K-map entries based on the probability of each combination of inputs. An error-correcting module (ECM) is designed to distinguish specific cases and reduce the error metrics. All circuits were simulated using ModelSim and then synthesized using Design Compiler with the 15 nm FinFET technology. When compared to state-of-the-art works, our multipliers exhibit approximately 30%, 43%, and 10% reductions in power, area, and delay, respectively. To evaluate their functionality, we conducted image multiplication and implemented a simple multi-layer perceptron (MLP) neural network using the modified National Institute of Standards and Technology (MNIST) dataset in MATLAB with 0.998 mean structural similarity index metric (MSSIM), 51 dB peak-signal noise ratio (PSNR), and 95% classification accuracy. • Introducing novel ultra-compact approximate compressor structures to reduce design metrics. • Proposing an error-correcting module (ECM) for compensating errors of approximation. • Proposing truncated 8 × 8 Dadda multipliers using the proposed approximate compressors and ECM. • Evaluating the accuracy of approximate multipliers in error-tolerant applications. [ABSTRACT FROM AUTHOR]