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Ayat is a system of self-improvement of health and self-consciousness, which was proposed by Abdullayev Farkhat Muhamedovich more than 20 years ago and today, is used by many people all over the world. It helps thousands to regain health and live normal healthy and happy life.

This letter presents a single-electron injection device for position-based charge qubit structures implemented in 22-nm fully depleted silicon-on-insulator CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5-nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small $0.7\times 0.4\,\,\mu \text{m}^{2}$ elementary quantum core is co-located with control circuitry inside the quantum operation cell which is operating at 3.5 K and a 2-GHz clock frequency. With this apparatus, we demonstrate a single-electron injection into a quantum dot.

This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies $3.5\times 45\,\,\mu \text{m}^{2}$ and consumes 0.27mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1mW (including its output driver) with an area of $40\times 25\,\,\mu \text{m}^{2}$ . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 $\mu \text{V}$ -rms is estimated through mathematical analysis while the ≤ 0.225mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.

We present an RF clock distribution system for a fully integrated and scalable quantum processor core operating at 3.8 K. An external 2.4 GHz signal is guided from the generator to the flip-chip package IC through a cryogenic coaxial cable. The choice of coaxial cable and the clock routing design on the PCB and IC, minimizes path loss and coupling to the supplies, the I/O signals, and more importantly the sensitive quantum core. The clock integrity up to the quantum core is maintained and verified by the jitter measurement of 0.8 ps from a test port while all circuitry within the cryo-cooler operates within the thermal load specification of 1.5 W.

A new photon-counting camera based on hybrid pixel technology has been developed at the SOLEIL synchrotron, making it possible to implement pump–probe–probe hard X-ray diffraction experiments for the first time. This application relies on two specific advantages of the UFXC32k readout chip, namely its high frame rate (50 kHz) and its high linear count rate (2.6 × 106 photons s−1 pixel−1). The project involved the conception and realization of the chips and detector carrier board, the data acquisition system, the server with its specific software, as well as the mechanical and cooling systems. This article reports on in-laboratory validation tests of the new detector, as well as on tests performed at the CRISTAL beamline within the targeted experimental conditions. A benchmark experiment was successfully performed, showing the advantages of the pump–probe–probe scheme in correcting for drifts of the experimental conditions.

Small-angle X-ray photon correlation spectroscopy (XPCS) measurements spanning delay times from 826 ns to 52.8 s were performed using a photon-counting pixel array detector with a dynamic range of 0–3 (2 bits). Fine resolution and a wide dynamic range of time scales was achieved by combining two modes of operation of the detector: (i) continuous mode, where data acquisition and data readout are performed in parallel with a frame acquisition time of 19.36 µs, and (ii) burst mode, where 12 frames are acquired with frame integration times of either 2.56 µs frame−1or 826 ns frame−1followed by 3.49 ms or 1.16 ms, respectively, for readout. The applicability of the detector for performing multi-speckle XPCS was demonstrated by measuring the Brownian dynamics of 10 nm-radius gold and 57 nm-radius silica colloids in water at room temperature. In addition, the capability of the detector to faithfully record one- and two-photon counts was examined by comparing the statistical distribution of photon counts with expected probabilities from the negative binomial distribution. It was found that in burst mode the ratio of 2 s to 1 s is markedly smaller than predicted and that this is attributable to pixel-response dead-time.

This paper presents the performance of a single-photon-counting hybrid pixel X-ray detector with synchrotron radiation. The camera was evaluated with respect to time-resolved experiments, namely pump–probe–probe experiments held at SOLEIL. The UFXC camera shows very good energy resolution of around 1.5 keV and allows the minimum threshold setting to be as low as 3 keV keeping the high-count-rate capabilities. Measurements of a synchrotron characteristic filling mode prove the proper separation of an isolated bunch of photons and the usability of the detector in time-resolved experiments.

We present a standalone and autonomous X-ray detector capable of operation with the speed of up to1.2 Mfps. The detector utilizes UFXC32k hybrid pixel detectors for sensing X-rays, Spartan-6 LX45 FPGA placed in commercially available sbRIO 9628 controller for data acquisition and processing including a compression with zero-suppression algorithm. A Linux-RT system working on the 400 MHz Dual-Core CPU is used for FPGA control and data streaming to the higher-level system over 1 Gbps Ethernet connection. 1.2 M frames per second is achieved in so-called burst mode of operation while in zerodead-time mode 70 kfps is possible. Due to efficient data compression in FPGA there's no need of using high-speed transceivers and Frame-Grabber cards on the data server side and the detector can stream the data infinitely over standard 1 Gbps network connection. Operation modes were tested at Advanced Photon Source Synchrotron at Argonne National Laboratory.

We present the design and measurements of a proton detection system built using a single photon counting hybrid pixel array detector. The system uses the UFXC detector designed for operating with very high photon fluxes. We demonstrate, that with appropriately modified data acquisition firmware, the UFXC detector is capable of operating in the frame-triggered zero dead-time mode, which captures every frame containing desired information, at a rate of up to 50 kfps. The detector consists of a 128 x 256 matrix of square-shaped pixels with a pitch of 75 μ m , which makes it suitable for particle tracking applications in test beam environments. We estimate the position resolution achieved with a single layer of the UFXC detector to be around 40 μ m .

Voltage-controlled magnetic anisotropy (VCMA) is increasingly gaining attention as a promising approach for low power manipulation method of spin [1]. The VCMA effect originates from voltage-induced charge accumulation/depletion at the interface of ultrathin ferromagnetic metal and insulative layers, such as in MgO-based magnetic tunnel junction (MTJ). One of the most important technical challenges for the VCMA effect is the scalability issue. For example, for G-bit class memory applications, high VCMA coefficient of more than 1000 fJ/Vm is demanded. However, the demonstrated VCMA effect with high speed response is limited to be only 100 fJ/Vm at present [2].

We present the FPGA implementation of the zero dead-time mode operation for the Ultra Fast X-Ray Camera. The camera consists of two UFXC32k chips bump-bonded to a single silicon sensor incorporated in a stand-alone camera communicating with an external system via Ethernet or Camera Link interface. Commercially available controller sbRIO 9651 including Zynq FPGA was used for both chip communication and Camera Link data streaming. Single software platform used for FPGA, Linux RT and Windows programming allows for efficient memory utilization and a high functionality operation in single-clock cycle in FPGA target as well as a multithread RT application in a state-machine paradigm. Presented solution allows for 7.3 kfps - the fastest framerate among commercial single photon counting x-ray cameras.

The paper presents a highly efficient system for automated wafer testing implemented on a single software platform. Building fully functional device requires often expensive and time consuming, manufacturing steps. Thus, the ASICs on the wafer ought to be tested in advance to ensure that only the chips with no manufacturing defects will be used in the further process. The presented testing system was used for the tests of the readout chip for hybrid pixel detectors working in a single photon counting mode. The aim of the system is to detect both digital and analog blocks' issues that might cause incorrect chip functioning. The system setup, software implementation, the methodology and the choice of the tests performed are described.

The UFXC32k is a single photon counting hybrid pixel detector with 75 μm pixel pitch. It was designed to cope with high X-ray intensities and therefore it is a very good candiate for synchrotron applications. In order to use this detector in an application, a dedicated setup must be designed and built allowing proper operation of the detector within the experiment. The paper presents two setups built for the purpose of Pump-Probe-Probe experiments at the Synchrotron SOLEIL and XPCS experiments at the APS.

Voltage control of spin enables both a zero standby power and ultralow active power consumption in spintronic devices, such as magnetoresistive random-access memory devices. A practical approach to achieve voltage control is the electrical modulation of the spin–orbit interaction at the interface between 3d-transition-ferromagnetic-metal and dielectric layers in a magnetic tunnel junction (MTJ). However, we need to initiate a new guideline for materials design to improve both the voltage-controlled magnetic anisotropy (VCMA) and perpendicular magnetic anisotropy (PMA). Here we report that atomic-scale doping of iridium in an ultrathin Fe layer is highly effective to improving these properties in Fe/MgO-based MTJs. A large interfacial PMA energy, Ki,0, of up to 3.7 mJ m−2 was obtained, which was 1.8 times greater than that of the pure Fe/MgO interface. Moreover, iridium doping yielded a huge VCMA coefficient (up to 320 fJ Vm−1) as well as high-speed response. First-principles calculations revealed that Ir atoms dispersed within the Fe layer play a considerable role in enhancing Ki,0 and the VCMA coefficient. These results demonstrate the efficacy of heavy-metal doping in ferromagnetic layers as an advanced approach to develop high-density voltage-driven spintronic devices. Researchers from Japan's AIST demonstrated a new approach to reduce the energy consumption of spintronic devices. Magnetic random-access memory requires approximately 10,000 times more energy to record data than to safely maintain it — a discrepancy that arises due to the wastefulness of electric-current-based switching of magnetic bits. Takayuki Nozaki and colleagues now report a device that enables us to write magnetic memory using electric fields, a more energy-efficient control mechanism. The team introduced an iridium-doped ultrathin iron film in magnesium oxide-based magnetic tunnel junctions, and found that the heavy-metal dopants provoked a strong voltage-controlled magnetic anisotropy change with high-speed response. Physical role of heavy metal dopants was unveiled by first-principles calculations. The developed technique can lead to a new type of non-volatile memory with ultra-low energy consumption. Highly efficient voltage control of magnetic anisotropy has been demonstrated utlizing an ultrathin Ir-doped Fe layer in MgO-based magnetic tunnel junctions. Ir adoms are dispersed inside the ultrathin Fe layer through the interdiffusion process. Large spin–orbit interaction of Ir atoms having proximity-induced magnetism is attributed to the enhancement of the voltage-controlled magnetic anisotropy (VCMA) effect. High speed response of the VCMA effect was also confirmed by voltage-induced ferromagnetic resonance. The achieved properties first satisfy the required specification for the new type of magnetoresistive random access memory (MRAM) driven by voltage.

We report on the design of a portable X-Ray camera working in single photon counting mode and a very high frame rate exceeding 20000 fps. The camera consists of hybrid pixel detector, where a two readout ASICs consisting of 23552 pixels of 75um pitch are used. A new approach is used for designing the camera using the commercially available controller board supplied with Zynq FPGA, ARM controller and custom PCB integrating readout chips bump-bodnded to the silicon sensor, power supply, variety of communication ports including USB, Ethernet and Camera Link. All levels of the system (FPGA, microcontroller and Windows Application) are programmed with National Instruments LabVIEW allowing extreme acceleration of developing process due to single software platform.

Single photon counting pixel detectors become increasingly popular in various 2-D X-ray imaging techniques and scientific experiments mainly in solid state physics, material science and medicine. This paper presents architecture and measurement results of the UFXC32k chip designed in a CMOS 130 nm process. The chip consists of about 50 million transistors and has an area of 9.64 mm × 20.15 mm. The core of the IC is a matrix of 128 × 256 pixels of 75 μm pitch. Each pixel contains a CSA, a shaper with tunable gain, two discriminators with correction circuits and two 14-bit ripple counters operating in a normal mode (with energy window), a long counter mode (one 28-bit counter) and a zero-dead time mode. Gain and noise performance were verified with X-ray radiation and with the chip connected to Si (320 μm thick) and CdTe (750 μ m thick) sensors.

We present three hardware solutions designed for a detector module built with a 2 cm × 2 cm hybrid pixel detector built from a single 320 or 450 μ m thick silicon sensor designed and fabricated by Hamamatsu and two UFXC32k readout integrated circuits (128 × 256 pixels with 75μ m pitch, designed in CMOS 130 nm at AGH-UST). The chips work in a single photon counting mode and provide ultra-fast X-ray imaging. The presented hardware modules are designed according to requirements of various tests and applications: ⋅Device A: a fast and flexible system for tests with various radiation sources. ⋅Device B: a standalone, all-in-one imaging device providing three standard interfaces (USB 2.0, Ethernet, Camera Link) and up to 640 MB/s bandwidth. ⋅Device C: a prototype large-area imaging system. The paper shows the readout system structure for each case with highlighted circuit board designs with details on power distribution and cooling on both FR4 and LTCC (low temperature co-fired ceramic) based circuits.

Integrated circuits designed for specific applications generally use non-standard communication methods. Hybrid pixel detector readout electronics produces a huge amount of data as a result of number of frames per seconds. The data needs to be transmitted to a higher level system without limiting the ASIC's capabilities. Nowadays, the Camera Link interface is still one of the fastest communication methods, allowing transmission speeds up to 800 MB/s. In order to communicate between a higher level system and the ASIC with a dedicated protocol, an FPGA with dedicated code is required. The configuration data is received from the PC and written to the ASIC. At the same time, the same FPGA should be able to transmit the data from the ASIC to the PC at the very high speed. The camera should be an embedded system enabling autonomous operation and self-monitoring. In the presented solution, at least three different hardware platforms are used—FPGA, microprocessor with real-time operating system and the PC with end-user software. We present the use of a single software platform for high speed data transfer from 65k pixel camera to the personal computer.