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Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

The use of chirp signals in modern radar and ranging systems have numerous benefits. They are extensively used to improve signal-to-noise ratio and range resolution. The performance capabilities of these signals are directly related to their time-bandwidth product, i.e., the duration and bandwidth of the pulse. Ultra-wideband chirp signals are further desirable because they span a large bandwidth, making them resistant to narrowband environmental interference. The accurate detection and measurement of high chirp signals is difficult due to the necessity of a high-sampling analog-digital converter, a target measurement platform with high computational power, and a time-of-arrival (TOA) estimator with high temporal resolution. The difficulty of the problem is further compounded with the requirement that no a priori knowledge of the signal, noise, or operating environment is known. This paper presents a practical approach and implementation of a high linear chirp rate receiver and TOA estimator pair capable of detecting and measuring stationary radio frequency pulses as well as linear chirp rates up to 1.18 GHz in 400 ns. The high-resolution TOA algorithm and linear chirp receiver have been prototyped, synthesized, and placed and routed for a Virtex 6 SX475 FPGA.

A classic second-order coupled-capacitor Chebyshev bandpass filter using resonator of tunable active capacitor and inductor is presented. The low cost and small size of CMOS active components make the bandpass filter (BPF) attractive in fully integrated CMOS applications. The tunable active capacitor is designed to compensate active inductor’s resistance for resistive match in the resonator. In many design cases, more than 95% resistive loss is cancelled. Meanwhile, adjusting design parameter of the active component provides BPF tunability in center frequency, pass band, and pass band gain. Designed in 1.8 V 180 nanometer CMOS process, the BPF has a tuning frequency range of 758–864 MHz, a controllable pass band of 7.1–65.9 MHz, a quality factor Q of 12–107, a pass band gain of 6.5–18.1 dB, and a stopband rejection of 38–50 dB.

Dynamic CMOS circuits are significantly used in high-performance very large-scale integrated (VLSI) systems. However, they suffer from limitations such as noise tolerance, charge leakage, and power consumption. With the escalating impact of process variations on design performance, aggressive technology scaling, noise in dynamic CMOS circuit has become an imperative design challenge. The design performance of dynamic circuits has to be first improved for reliable operation of VLSI systems. Alongside, this impact of process variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, these problems of process variations, timing, noise tolerance, and power are investigated together for performance optimization. We propose a process variation-aware load-balance of multiple paths transistor sizing algorithm to: 1) improve worst-case delay, delay uncertainty, and sensitivity due to process variations in dynamic CMOS circuits, and 2) optimize dynamic CMOS circuits with MOSFET-based keepers to improve the noise tolerance. Implemented using 90-nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 34%, delay uncertainty by 40.3%, delay sensitivity by 25.1%, and noise margins by 19.4% when compared to their initial performances.

A system-on-a-chip (SoC) built with embedded intellectual property (IP) cores offers attractive methodology design reuse, reconfigurability, and customizability. However, the integration of the design-for-testability (DfT) structures of the IP cores in these complex SoCs presents daunting challenges to designers and ultimately affects the time-to-market goals. In this paper, we introduce a design methodology to reduce the time to market by taking core test data from the design environment and automatically generating DfT structures that can easily be integrated into the SoC. A novel automated synthesis methodology to generate an SoC built-in self-test (BIST) to test the IP and custom logic cores is proposed. The proposed technique, i.e., NonExclusive Xor Test of 2D linear feedback shift register (NEXT 2D LFSR), is modeled after the principle of configurable 2D LFSR design, which generates a deterministic sequence of test vectors for random-vector-resistant faults and then random test vectors for random-vector-detectable faults. The basis of this method is to explore the design solution space for optimal 2D LFSR while embedding the test patterns by nonexclusively considering xor gates as the conventional LFSR does but including a simple logic solution for minimal hardware optimization. Moreover, the proposed approach is capable of optimizing the 2D LFSRs with consideration of the don't-care bits in the incompletely specified test patterns.

A band pass filter (BPF) for center frequency over a wide frequency span and pass band is presented, which uses an efficient synthesis via two design stages: 1) the transconductance stage and 2) the transimpedance stage. Changing design parameters in the two design stages in 1.8 V 180 nanometer TSMC CMOS process, a BPF for a tuning frequency range of 1.0–2.04 GHz and a controllable pass band of 5.5–51.2 MHz is designed, which achieves a high pass band gain of 45.2–65.1 dB and a stopband rejection of 25 db. The noise figure is kept low to a range of 1.49–5.88 dB when pass band is 12 MHz. It provides a good solution to pre-tune desired signals while reject interfering signals.

Today's very deep submicron IC technology enables high-performance analog and digital applications to be integrated on a single piece of silicon. For this effort, a design of 2.5 giga-sample per second (GSPS) receiver-on-a-chip (ROC) is presented. For our design, we take advantage of a compensation technique to reduce spurs and improve instantaneous dynamic range. A major goal is to produce a low-cost, small, and lightweight, and low-power ROC. Our design will cover a 1-GHz bandwidth (125 - 1125 MHz), and it will correctly process two simultaneous signals by detecting their frequency, pulsewidth (PW), and time of arrival (TOA). The single or dual signal, spur-free dynamic ranges and two signal instantaneous dynamic ranges of our design are high. The minimum frequency separation of two signals is 10 MHz (one channel width), and the maximum amplitude separation (dynamic range) of two signals is 18 dB with the second signal false alarm less than 1%.

A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.

As a modern radar receiver must rapidly search a large frequency range with maximum sensitivity, capabilities such as high instantaneous dynamic range (IDR), good multiple-signal-detection capability, wider bandwidth (BW), and high-frequency resolution are indispensable. Many techniques proposed to improve digital wideband receiver performance are computationally intensive and limit their real-time performance due to hardware constraint. In this paper, an innovative three gigasample-per-second hybrid computing platform digital wideband receiver system is presented, which employs two Nvidia Tesla C2050 graphics processor units and a Xilinx Virtex-5 field-programmable gate array for hardware acceleration to drastically improve receiver performance over its predecessor designs. The receiver detects five simultaneous signals in 1.25-GHz BW (125-1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture achieves high-resolution spectral estimation and employs a hardware mechanism for multiple-signal detection before the next set of data arrives for processing.

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that (BIST and its derivative (BIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead.

For pt. I see ibid., vol. 32, no. 1, p. 1-15 (1996). Common buses are an extremely efficient structure for achieving area minimization so that the bus-oriented interconnection of registers and data operators plays an important role in data path synthesis. The overriding design goal is efficiently allocating the minimum number of buses and gating elements (i.e. multiplexers) for achieving communication between the data path elements. New efficient algorithms for the automated allocation of buses in data paths have been developed. The entire allocation process can be formulated as a graph partitioning problem. This formulation readily lends itself to the use of a varieties of heuristics for solving the allocation problem We present efficient algorithms which provide excellent solutions to this formulation of the allocation problem The operation of the algorithms is clearly demonstrated using detailed examples.

A data path consists of memory elements (i.e., registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to hardware allocation for data path synthesis have been proposed in the literature; however, only single-port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. A novel design methodology for data path synthesis using multiport memories is proposed which can be applied to hardware allocation algorithms or to already synthesized data path as a postprocessor to achieve a better design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. Experiments on benchmarks show very promising results.

BIST techniques for analog and mixed-signal circuits have attracted considerable research activity; especially utilizing on-chip ROMs to store high precision sinusoidal stimuli and pre-calculated Delta-Sigma modulated bit-streams. However, usage of ROMs in high-performance circuits has poses substantial challenges, mainly because of its inability to run at-speed tests and high area overhead due to its prohibitively large size. An alternative to ROM utilization is the use of LFSRs. But, the computation time of the LFSR based BIST synthesis for large mixed-signal SoC poses a huge challenge. A high-performance computing (HPC) based automated mixed-signal SoC BIST synthesis technique that can outperform the conventional ROM implementation not only with respect to the computation time needed to generate the test vectors or waveforms, but also the BIST hardware required, is presented in this paper. Furthermore, the versatility of the presented LFSR based BIST test vector generator, that allows itself to be used for embedding deterministic patterns for LBIST and storing sinusoidal stimuli or pre-calculated Delta-Sigma modulated bit-stream for analog BIST, is demonstrated.

Design and implementation of a modern radar receiver that is capable of rapidly searching a large frequency range with maximum sensitivity in real time presents a challenge. Such a receiver not only has stringent operational requirements like high instantaneous dynamic range (IDR), multiple signal detection capability, wider bandwidth and also high frequency resolution. Currently, operating speeds of digital processors are not on par with state-of-the-art ADCs. To overcome this impediment, researchers are exploring methods of offloading the computational intensive tasks to specialized hardware accelerators. A 3 giga-sample-per-second (GSPS) wideband digital receiver system implemented on a unique hybrid computing platform, which is composed of two Tesla C2050 GPUs and a Xilinx Virtex-5 FPGA, is presented. Drastically improving its performance over its predecessors, the proposed receiver system detects five simultaneous signals in 1.25 GHz bandwidth (125–1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture performs a high-resolution spectral estimation and employs a hardware efficient platform for detecting multiple signals before the next set of buffered data arrives for processing.

Performance variation is one of the primary concerns in nanoscale CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware, Transistor (PVT) sizing algorithm is proposed, which is capable of reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in nanoscale CMOS circuits. The proposed algorithm is based on identifying the significance of timing paths in a design, and performing respective optimization for optimal design performance. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.

To overcome the read data destruction and to gain stability at Iow-VDD a seven-transistor (7T) SRAM cell is implemented and compared with the conventional six-transistor (6T) SRAM cell. To illustrate the robust performance of an 8-bit SRAM statistical simulation and data analysis by considering the process variations and mismatch was conducted for every operation of the 8-bit SRAM. The measurement results show that the static noise margin (SNM) of the 7T SRAM cell is better than that of the 6T SRAM cell. The stability of the 8-bit 7T SRAM at low-VDD is also proved by testing the SRAM at 720 mV.

Digital wideband receivers are essential elements used in electronic warfare applications. Instantaneous Frequency Measurement (IFM) receivers are suitable for use in EW systems due to the ultra-wideband instantaneous radio- frequency (RF) bandwidth, fine-frequency resolution, and moderately high sensitivity and dynamic range. Conventional IFM receivers use analog components such as power dividers, crystal video detectors, and hybrids. This paper presents the architecture and design implementation of a patented "digital IFM receiver" algorithm. The invention is capable of detecting short wave pulse or CW signal of 1.2 GHz bandwidth with a major error within 2 MHz for every 100 nsec.

A practical fast Fourier transform (FFT) processor can contain several millions of gates, so effective design techniques usually are required in order to guarantee high-speed products. A look-up table (LUT) methodology is developed and demonstrated on variable length (128-1024 point), variable bit-precision (6-12 b) FFT with uniform bit truncation and optimum bit truncation for wideband digital receiver in radar applications. The FFT processors are designed using a standard 130 nanometer CMOS process and operates down to 120 mV. The required processing time for the non-configurable 12-b 1024-point LUT FFT is 15.78 ns at a clock frequency of 470 MHz. The required time for configurable LUT 12-b 1024-point FFT processing is 61 ns. The configurable LUT FFT processor with short transform lengths can be expandable so that they can be used easily to form new FFT processors with longer transform lengths. The performance comparison of conventional FFT, LUT FFT, and configurable LUT FFT for digital wideband receiver application is discussed.

A configurable wideband digital receiver with multiple signal detection capability is presented The implementation of multiple signal detection scheme is often a challenge due to the timing and hardware constraints. The efficient multiple detection scheme presented in this paper employs hardware reuse by effective configuration and detects multiple signals before the next set of buffered data arrives for processing. Performance evaluation of the configurable receiver to detect up to five signals, their maximum attainable instantaneous dynamic range (IDR) and frequency detection error analysis are presented.

A low-power 1.25-GHz signal bandwidth 4-bit ADC designed in a standard 130 nanometer digital CMOS process for high spurious-free dynamic range (SFDR) wideband communications is presented. The ADC uses new clocked digital comparators designed by a dynamic offset suppression technique. The SFDR and ENOB of this 4-bit ADC achieve 31.44 dB and 3.75 bits at input signal of 39 MHz. Near Nyquist frequency input signals, the SFDR and ENOB maintains above 22.79 dB and 2.37 bits at input signal of 1.23 GHz. This ADC has a latency of two and half clock cycles, a low input capacitance of 300 fF, and a low power consumption of 7.9 mW at a 2.5 GHz conversion rate operating down to 120 mV. The ADC has a figure-of-merit (FoM) of 0.611 pJ per conversion step.

In this paper we describe the use of the FFT on an FPGA to perform lock on coarse acquisition (C/A) code and carrier frequency in a global positioning system (GPS) receiver. A novel technique of sub-sampling is used in this system to obtain data block sizes that match hardware limitations. The system uses 10 ms of data to perform the lock with 6 ms of processing time and theoretically can operate on signals 20 db below the noise floor.

This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for System-on-a-Chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2.5 Gsamples/s current steering digital-to-analog converter (DAC). Both integral nonlinearity (INL) and differential nonlinearity (DNL ) errors of test signals were obtained about 0.5 LSB by the sine wave histogram testing. The measured power dissipation for generated test signals of 600 MHz at the power supply of 1.2 V is about 5.32 mW. The current steering DAC achieves 22.3 dB of spur free dynamic range (SFDR) for 600 MHz signals.

A technique of using the Kaiser window to reduce the spectral leakage by eliminating the discontinuities at the time window edges and using the compensation method to uncover the weak signal for extension of the two signal spur free dynamic range (SFDR) for a wideband digital receivers is presented. The combination of both techniques extends the two signal SFDR of the receiver to 24 db.

This paper presents a built-in self-test (BIST) architecture for testing high speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations is proposed along with hardware architecture for performing on-chip BIST. The architecture presented utilizes an on-chip ROM and allows for the generation of test signals with multiple frequencies as well as single frequency signals. The issues associated with BIST signal generation for low voltage ADCs are also discussed

This paper presents a built-in self-test (BIST) architecture for testing high speed analog-to-digital converters (ADCs) with sampling rates in excess of 1 GHz. A methodology for performing mixed-mode BIST simulations in SoC applications is proposed along with hardware for performing on-chip BIST. The architecture presented utilizes an on-chip ROM and allows for the generation of test signals with single frequency as well as multiple frequencies signals. The issues associated with BIST signal generation for low voltage ADCs are also discussed. Simulations revealed that the SFDR of the sinusoidal signal generated from the BIST hardware was 25.28 dB with a frequency of 312.5 MHz and 19.88 dB with a frequency of 416.67 MHz.

1ABsfrarf - A design of 2.5 GSPS digifal receiver using fhe superresolufion fechnique to improve fhe insfanfaneous dynamic range is presenfed The digifal design can cover 1 GHz bandwidfh (125 MHz - 1125 MHZ) and can correcffy process fwo simultaneous signals. This design uses a fast Fourier fransform (FFV fo obfain frequencies on two simultaneous signals. If has a beffer sensiriviry than IFM receivers because fhe FFT channelizes the input info narrower bandwidth It has fine frequency resolufion (able fo separaie two closefrequencies) and goodfrequency accuracy. The single signal, fwo signal spur free dynamic ranges, 'and two signal insfanfaneous dynamic ranges are high.

A configurable 2D LFSR based test generator and an automated synthesis procedure is presented. Without storage of test patterns, a 2D LFSR based test pattern generator can generate a sequence of pre-computed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable). The hardware overhead is decreased considerably through configuration. The configurable 2D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2D LFSR can also be adopted in chip-level and system-on-chip (SoC) BIST.

This paper introduces a Built-In Self-Test (BIST) design methodology that can sequentially test large VLSI circuits with very high fault coverage. The proposed techniques, Circular Built-In Self-Test (CBIST) and CBIST with pseudo-partial scan (PP-SCAN), are modeled after the principles of the Circular Self-Test Path. The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It will be shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared to existing sequential test methods. >

A built-in self test (BIST) method for a systolic array controller chip/multiplier-accumulator chip (SAC/MAC) was used to generate the signatures for all combinational blocks of each cell in parallel. The BIST is combined with a scan path design; therefore, all registers in the array cells are connected as a scan chain and all signatures are shifted out by this scan chain to be compared with a previously generated fault-free signature. Thus, the signature generated by the BIST circuitry determines the status of each cell (fault-free or faulty). The self-diagnostic capabilities were then incorporated into the BIST SAC/MAC cell to solve the problem of the long testing time caused by the long time required to scan out the test results when large arrays are used. Although incorporating BIST into the SAC/MAC cell made the array more testable, some redesign had to be done. The major change was using one chip instead of two. >

The authors describe the construction of the SF2000 VLSI stack-frame RISC computer (a design based on the successful SF1 computer) and discuss the advanced methods, such as random pattern testing and design partitioning aids, used in the construction of the on-chip BIST (built-in self test) hardware in this three-chip computer. The SF2000 CPU chip will contain architectural elements such as a 2-way set of associative instruction cache, a data cache, and on-chip provisions to use the SF2000 as a computing element in a multiprocessing environment. The testability measures included on-chip will emphasize random-pattern testing, design partitioning, and concurrent memory testing with measures of their costs and effectiveness for future applications, such as larger VLSI and WSI circuits. Some methods which reduce the overhead of BIST designs without degradation of the test coverage of faults are also described. A 8*8 mm VLSI circuit in 1.2 micron double-metal CMOS technology and approximately 300000 transistors mounted in a 224 pin grid array package, is envisaged. >

A top-down design of test generation and response analysis for built-in self-test (BIST) is proposed. The design procedure is computationally efficient for test generation, and produces test generation circuitry with low hardware overhead. The effectiveness of the approach is demonstrated by detailed comparisons of the results with those obtained with existing techniques. For response analysis, a delay redundancy check is proposed to improve the failure rate of a vertical and horizontal redundancy check fault-detection scheme. In combination with the two-signature scheme, the frequency of aliasing is reduced to one in 2/sup 4n/ for an n-input, m-output circuit under test, where 2/sup n/>m. >

An ASIC for a wide band (1 GHz) digital monobit receiver designed for processing two simultaneous signals will be described. The receiver consists of three major elements: (1) a nonlinear radio frequency (RF) front-end, (2) a signal sampler and formatting system (analog-to-digital converter (ADC) and demultiplexers), and (3) a monobit algorithm implemented as an ASIC for signal detection and frequency measurement. The receiver uses a two-bit ADC operating at 2.5 GHz whose outputs are collected and formatted by demultiplexers for presentation to the ASIC. The ASIC has two basic functions: (1) perform a fast Fourier transform (FFT) and (2) determine the number of signals and report their frequencies.

In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.

Synthesis for testability ensures that the synthesized circuit is testable by exploring the fundamental relationship between don't care and redundancy. With the exploration of the relationship, redundancy removal can be applied to improve the testability, reduce the area and improve the speed of a synthesized circuit. The test generation problems have been adequately solved, therefore an innovative testability synthesis strategy is necessary for achieving the maximum fault coverage and area reduction for maximum speed. This paper presents a testability synthesis methodology applicable to a top–down design method based on the identification and removal of redundant faults. Emphasis has been placed on the testability synthesis of a high-speed binary jumping carry adder. A synthesized 32-bit testable adder implemented by a 1.2 μm CMOS technology performs addition in 4.09 ns. Comparing with the original synthesized circuit, redundancy removal yields a 100% testable design with a 15% improvement in speed and a 25% reduction in area.

Many IC design houses failed to be market leaders because they miss the market window due to timing closure problems. Compared to half-micron designs, the amount of time spent on timing verification has greatly increased. Cell delays can be accurately estimated during logic synthesis. However, interconnect delays are unknown until the wire geometry is defined in physical design. Logic synthesis using the cell library models for interconnect delay estimates may be statistically accurate, but can not predict the delay of individual nets accurately. Delay estimates for individual nets (global nets, long wires, large fan-outs, buses), which matter most for the critical paths can be inaccurate and cause a design failure. Inaccurate timing verification causes silicon failure in shipped products that results in the loss of millions of dollars spent designing a high-performance product and potentially larger costs due to lost market share. Full-chip, sign-off verification with silicon-accuracy will allow these problems to be discovered and fixed before tape-out.

In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. A synthesis procedure for this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators. The experiment result shows that compared with the non-configurable 2-D LFSR, the average number of flip-flops is reduced by 79% for five benchmark circuits. The average number of faults detected by the configurable 2-D LFSR is 9.27% higher than that of the conventional LFSR and 0.57% higher than that of the non-configurable 2-D LFSR.

The sections in this article are 1 Bicmos Inverter 2 Cmos Parallel Adders 3 Mixed Cmos/Bicomos Area-Time Optimal Adders 4 Conclusions

A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.