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This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

Objectives: To study the use of simulation tool to understand the circuit behavior in presence of faulty component and use of part stress method for failure rate computation. Methods/ statistical analysis: The behavior of circuit under test (CUT) is studied in normal and faulty conditions using MATLAB simulation tool. Diode open circuit and short circuit faults are separately introduced to study the circuit performance. In developed prototype real faulty diode is purposely connected to verify the performance. After that reliability computation, part failure rates of components are estimated using military handbook MIL-HDBK- 217F of the CUT. Findings: In this work, a method is presented in which circuit performance in presence of faulty component is studied and individual component failure rates are estimated for reliability understanding. Close match in results of simulation tool and hardware prototype is observed. Such approach is good choice for understanding the behavior of power electronics circuit. Novelty/Applications: The proposed technique is useful in fault modeling of power supplies and power stations. Semiconductor power electronics devices are prone to failure, therefore reliability oriented designs of power supplies, converters, inverters and other power converting circuits is important issue. The component failure rates and circuit reliability should be estimated by using part stress method or suitable reliability estimating software. Individual component failure rates provide idea about long lasting behavior; fault precursors and fault signatures help to understand the circuit performance in presence of faulty component. Keywords: Component level fault study; simulation based fault diagnosis; simulation based fault signatures; component failure rate estimation; diode fault in rectifier

Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new approach to increase the reliability of digital circuits against soft errors caused by multiple event transients (METs) by taking advantages of circuit partitioning and local logical restructuring techniques. In the proposed approach, the circuit is partitioned into various subcircuits and, then, several structures of each subcircuits which satisfy the area constraints are extracted by using a graph-based procedure. In order to select the suitable alternative between various subcircuit structures, we introduce a novel metric named global failure probability in the presence of METs (GFPM). This parameter provides an evaluation of each subcircuits contribution in the soft error rate (SER) of the given circuit making it possible to estimate the impacts of changing the structure of the subcircuits on the circuit SER. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time-consuming leading to significant improvements in the optimization runtime. Experimental studies on ISCAS benchmark circuits show that the proposed approach, on average, achieves 18.4% SER reduction with 11.9% area overhead and 8.2% delay overhead comparing to the original circuit while the global SET-based SER mitigation approach and the global MET-based SER mitigation approach achieve 8.46% and 21.8% SER reduction, respectively. Besides, the proposed technique is about $580 \times $ faster than the global MET-based method.

Performance failure due to aging is an increasing concern for RF circuits. While most aging studies are focused on the concept of mean-time-to-failure, for analog circuits, aging results in continuous degradation in performance before it causes catastrophic failures. In this paper, we present a methodology for monitoring and recovering the performance of RF circuits in the field at little or no performance penalty. The proposed technique is based on two phases: During the design time, degradation profiles of the aged circuit are obtained through simulations. From these profiles, we identify reliability hotspots and focus on monitoring these components, and recovering from the effects of their aging. After deployment, an on-chip monitor circuit is periodically activated and its results are used to trigger the recovery mechanism if necessary. The recovery mechanism is designed to offset the degradation in the reliability hotspots to enhance the lifetime of the circuit. Lifetime is defined as the point where at least one specification of the circuit fails due to aging degradation. A Low noise amplifier (LNA) is fabricated as a case study to demonstrate that the lifetime can be enhanced by the proposed monitoring and recovery techniques.

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart - when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former's better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

As semiconductor feature size continues to decrease and the density of integration continues to increase, highly reliable circuit design is experiencing many challenges, including reliability evaluation, which is one of the most important steps in circuit design. However, faced with the very large scale of integrated circuits at present, traditional simulation-based methods are slightly inadequate in terms of computational complexity and do not apply to the circuits at the concept stage. To solve this problem, this paper presents a new prediction method for circuit reliability based on deep auto encoder networks. Firstly, we analyze and extract the main features associated with circuit reliability. Next, we construct an efficient method for data collection by combining the characteristics of the feature set with the requirements of deep auto encoder networks. Then, we build a deep auto encoder network model oriented to circuit reliability prediction in a supervised learning manner. Simulation results on 74-series circuits and ISCAS85 benchmark circuits show that although the accuracy of the proposed method is slightly lower than that of both the Monte Carlo (MC) method and the fast probabilistic transfer matrix (F-PTM) model, its time-space consumption is approximately constant on different circuits, and it is 102,458,469 times faster than the MC method, and approximately 4,383 times faster than the F-PTM model. Furthermore, the proposed method could be used to predict circuit reliability at the conceptual stage, and it is a very efficient approximation method that could greatly reduce the power consumption of the calculation.

Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, the aggressive scaling of CMOS devices has significantly affected their reliable operation. Several schemes have been used for mitigating the scaling effects and maintaining the reliability above a certain threshold. Many of these schemes rely on incorporating different types of redundancy at the device, gate, and system level, which inevitably affect the area, power, and delay parameters. To optimize the tradeoff between these conflicting parameters, an accurate and efficient reliability EDA tool is needed. Such a tool would help circuit designers compare different reliability schemes and select the one that achieves the target reliability margins while having minimum impact on the other design parameters. However, the enormous size and the complexity of today's logic circuits make accurate calculation of the circuit's reliability a very challenging and time-consuming process. This paper introduces a novel, accurate, and efficient algorithm for circuit reliability estimation. The algorithm improves accuracy by taking the effect of reconvergent fan-out nodes into consideration, while improving efficiency by implementing a multithreaded approach for node evaluation. Simulation results show that the proposed algorithm is efficient and more accurate than other reliability estimation algorithms currently proposed in the literature.

Copyright IEEE, The characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-Aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples., This work was supported by the VIGILANT Project (PID2019-103869RB / AEI / 10.13039/501100011033) and the TEC2016-75151-C3-R Project (AEI/FEDER, UE).

With the introduction of FinFET transistors, the Self-Heating Effect (SHE) became a major reliability challenge. In this work, we present an automated SHE estimation method integrated within a circuit reliability framework. It allows designers to study SHE in analogue and digital circuits. For accurate analysis, we employ electrically and thermally calibrated 14nm FinFET transistor models. To demonstrate the capabilities of our framework, we study SHE in standard cells and report a considerable dependence on the cell topology. We show how SHE can induce 15% delay increase in AND3 logic gate, highlighting the importance of taking SHE into account. Otherwise, reliability cannot be sustained during the circuit’s operation.

This review paper reports the prerequisites of a monolithic integrated terahertz (THz) technology capable of meeting the network capacity requirements of beyond-5G wireless communications system (WCS). Keeping in mind that the terahertz signal generation for the beyond-5G networks relies on the technology power loss management, we propose a single computationally efficient software design tool featuring cutting-edge optical devices and high speed III–V electronics for the design of optoelectronic integrated circuits (OEICs) monolithically integrated on a single Indium-Phosphide (InP) die. Through the implementation of accurate and SPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact models of uni-traveling carrier photodiodes (UTC-PDs) and InP double heterojunction bipolar transistors (DHBTs), we demonstrated that the next generation of THz technologies for beyond-5G networks requires (i) a multi-physical understanding of their operation described through electrical, photonic and thermal equations, (ii) dedicated test structures for characterization in the frequency range higher than 110 GHz, (iii) a dedicated parameter extraction procedure, along with (iv) a circuit reliability assessment methodology. Developed on the research and development activities achieved in the past two decades, we detailed each part of the multiphysics design optimization approach while ensuring technology power loss management through a holistic procedure compatible with existing software tools and design flow for the timely and cost-effective achievement of THz OEICs., Applied Sciences, 11 (5), ISSN:2076-3417

Printed Circuit Board (PCB) plays an essential role as a basic unit of electronic products to realize certain functions. Therefore, it is necessary to evaluate its reliability in an accurate way to promote the design improvement for electronic products. In this paper, a Physics of Failure (PoF) based reliability simulation on a PCB product is carried out by using the RISA-PofEra software developed by Beihang University, China. During the simulation analysis, thermal and vibration stress profiles over the PCB were exerted to provide inputs of a couple of PoF models for the reliability calculations of semiconductor devices on that PCB. Meanwhile, with the consideration on geometrical uncertainties in semiconductor packages, the Meantime Time to Failure (MTTF) of the PCB is calculated from the lifetimes of its weakest semiconductor device by using a Monte-Carlo method.

With the dimension of transistor scaling down to 3nm, device and circuit reliability attract increasing attentions in digital and analog design. Self-heating effects must be taken into account due to the introduction of FinFET structure, which will be more serious with thinner and higher Fin shape optimization and future GAA device. Self-heating related qualification is also critical, since it may impact the HCI, EM and TDDB. In addition, layout dependent effect is another important issue and is found to be more serious in smaller dimension. Finally, aging induced variation has also been shaving away the design margins, especially in SRAM, this effect is studied systematically in this paper.

The growth in Artificial Intelligence, advanced 5G wireless network, cloud computing, safety-critical automotive electronics and mainstream adoption of FinFET technologies have resulted in significant increase in IC design robustness challenges. IC designers must contend with advanced circuit complexity with stringent requirements on performance, low power, design robustness for safety, and reliability such as electro-migration and device-aging. For safety-critical applications such as Autonomous Driving, ADAS, and Connected Car, IC designers are now looking to adopt rigorous and systematic methodologies to meet functional safety standard. In this paper, we will discuss the models used on circuit reliability verification, and application of these models to assess IC reliability and variability for targeted requirements with latest Synopsys' AMS solution for robust design.

Resynthesis-based fault tolerance technique is a method in which a combinational circuit is restructured to maximize the masking properties of the circuit in the presence of soft errors. This chapter presents an approach to increase the reliability of digital circuits against soft errors by taking advantages of circuit partitioning and local logical restructuring techniques. The main circuit is partitioned into a set of small sub-circuits based on the minimum connection objective. Then, different logical implementations of sub-circuits with the same function as the original sub-circuit are carried out using AND-INV Graph (AIG) scheme. Among the obtained implementations of the sub-circuit, an implementation which provides the most circuit SER reduction and meanwhile does not violate the original circuit timing and area constraints is replaced instead of the current sub-circuit in the circuit. In order to evaluate the effects of manipulating a sub-circuit on circuit reliability, a global failure probability (GFP) metric which provides an estimation of the contribution of a sub-circuit in total circuit SER is introduced. Such reliability evaluation technique significantly reduces the resynthesis process runtime. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time consuming leading to significant improvements in the optimization runtime.

International audience; To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications.

The need for processing the continuously growing amount of data that is produced every day is promoting research for the development of energy-efficient non-von Neumann computing architectures. Over the last decade, resistive RAM (RRAM) devices together with material implication logic (IMPLY) were proposed as a promising solution for the development of low-power logic-in-memory (LIM) circuits. Still, the high design complexity and the low reliability of these circuits are hindering their practical realization. It is only recently that a new smart IMPLY architecture, named SIMPLY, was proposed and shown to drastically improve circuit reliability and energy efficiency of IMPLY-based LIM circuits. In this work, we introduce a new smart operation, called sFALSE, enabled by the SIMPLY architecture, and verify its feasibility using a physicsbased RRAM compact model calibrated on three different technologies. We highlight the significant advantage of the proposed solution vs. ordinary IMPLY architecture in terms of energy reduction, especially for large fan-in logic operations (e.g., n-bits NAND and EXOR).

Ion sensitive field-effect transistor (ISFET) and extended–gate field-effect transistor (EGFET) based biosensors are widely used devices for monitoring biological–processes such as enzymatic and antigen-antibody reactions, as well as nucleic–acid hybridization. Most of the recent field-effect based biosensors reported in the literature, utilize commercial analog front-ends for easier development, even though the continuous miniaturization and the consolidated complementary metal-oxide semiconductors (CMOS) technology allows to work at low-voltage/low-noise maintaining circuit reliability. To improve the performances with respect to commercial electronic interfaces, this paper presents a comprehensive study of the design and fabrication of an EGFET by using transistor association technique, designed in standard 130 nm CMOS process. Simulation and experimental results show that the DC equivalence with a single transistor with an input-referred noise ranging from 352.7 to 176.4 nV rms from 0.1 to 10 Hz. Prototypes are investigated in a real case scenario as a pH sensor which showed a voltage sensitivity of ≈ 58 mV/pH with linearity higher than 99%. A prototype has been tested in clinical settings for the analysis of pH in urine samples in comparison to the standard reactive strips.

Negative bias temperature instability (NBTI) is a major time-dependent reliability concern with the pMOS transistor at elevated temperature. NBTI in pMOS is the severe dominating factor of circuit reliability as it increases the threshold voltage with time. In this paper, an nMOS-only Schmitt trigger with a voltage booster (NST-VB) circuit is proposed. The use of only an nMOS transistor in the critical path of the Schmitt trigger circuit drastically reduces the effect of NBTI on the circuit and, hence, improves performance. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of an nMOS-only structure. Because of NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% compared to 7.2% and 1.47% for the conventional Schmitt trigger and nMOS inverter, respectively, after the stress time of three years. The proposed NST-VB circuit is also validated with an s27 benchmark circuit from the ISCAS’89 benchmark set and found that it has a lower effect of NBTI compared to CMOS and Schmitt trigger inverter circuits. For the viability of the proposed circuit, figure-of-merit (FOM) is used as a performance metric and it is found that the proposed circuit has ${15.11\times }$ improved FOM compared to the conventional Schmitt trigger circuit.

Temperature monitoring and thermal management of CMOS circuits / sensors is often required for long term circuit reliability and sensors temperature compensations. The ideal solution is to co-fabricate the temperature sensors along with the CMOS circuits and other sensors using CMOS materials and the same CMOS processes. In this paper we therefore, report on the fabrication and thermal characterization of such thin film temperature sensors. The thin film Resistance Temperature Detectors (RTDs) are made of single crystal p-type silicon on a silicon substrate using a Silicon on Insulator (SOI) Complementary Metal Oxide Semiconductor (CMOS) process. The influence of thin film length and width on the response of RTDs has been investigated. Furthermore, the effects of aluminum (Al) and tungsten (W) metallization used for power tracks on the response of RTDs have been studied. To assess the performance of the RTDs based on SOI CMOS p-type silicon, in addition to sensitivity and TCR, their power consumption, linearity, hysteresis, repeatability, reproducibility and expected life span have also been evaluated. The p-type silicon RTDs consume very less power (i.e. 0.9 μW only) and demonstrate a sensitivity of 13.88 Ω / oC, which is much higher than the previously reported CMOS RTDs and widely used non-CMOS platinum RTDs. The RTDs also exhibit a linear response (98.9% fsd), an excellent repeatability and significantly low hysteresis with maximum variation of 0.2% between forward and reverse cycle. These RTDs also boast good reproducibility, within the wafer and wafer to wafer, with maximum sensitivity variation of 1.3% between different tested samples. The expected life span of the RTD is > 10 years. These inexpensive RTDs are therefore, good candidates for use as temperature sensors on CMOS circuits / sensors system.

Total ionizing dose tolerance is one of the essential features of the electronic devices used to control and monitor the vital operations in extreme environments. Most of today’s commercial off-the-shelf systems do not have this capability unless they are shielded with at least 10 cm of tungsten. Hence, application-specific integrated circuits (ASICs) are developed to achieve the desired performance in extreme environments. In this paper, a new ASIC structure with self-repair capability has been proposed using the field-programmable nanowire interconnect architecture. Our proposed structure includes a nonprogrammable part as circuit functionality and a reconfigurable part to improve the circuit reliability. The performance of the proposed structure is compared with some static and dynamic fault-tolerant approaches. According to the simulation results, the proposed structure can tolerate several permanent faults during the run time with minimum delay, power consumption, and area overhead.

FinFET technology is one of the most promising candidates in replacing planar MOSFET beyond the 22 nm technology node. However, the complexity of FinFET manufacturing process has caused challenges in reliable device testing. Gate oxide short (GOS) is one of the dominant defects that has significant impact on circuit reliability. In this paper, we present a GOS defect model for FinFETs by introducing the defect as a pinhole in the gate oxide of a triangular fin shape structure. The pinholes are represented by small cuboid cuts of various sizes on the fin top and sidewalls along the channel. The 3D Sentaurus TCAD simulation results in the development of an analytical GOS defect model that can be used in circuit-level fault modeling, which leads to generating more realistic test patterns.

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.

While multiple patterning lithography suffers from considerable and increasing mask manufacturing cost, next generation lithography technologies are urgently required for sub-10 nm technology nodes, where directed self-assembly (DSA) is one of the most promising candidates for contact/via layer fabrication. In addition, redundant via insertion is regarded as an important step in the circuit design flow to improve circuit reliability and yield. In this paper, we propose to adopt wire perturbation to further enhance via manufacturability and redundant via insertion rates. In addition, an improved DSA-compliant and redundant via-aware routing graph model is proposed and a systematic via graph update approach is developed to facilitate the implementation of the router. Experimental results demonstrate that compared with a state-of-the-art work, our wire perturbation approach can averagely increase inserted redundant vias by 6% and reduce unmanufacturable vias by 23% with only 0.9% wirelength overhead, and our routing graph model achieves the same performance as the one proposed in a state-of-the-art work and is much more efficient.

The effects of Hf content on the radiation hardness of Hf–In–Zn–O thin-film transistors (HIZO TFTs) and HIZO TFT-based circuits are systemically examined. The evaluated circuits, including current-starved ring oscillator, energy harvesting, and RF circuits, are essential for space electronic systems. It is shown that HIZO TFTs with low Hf concentration have better initial performance while TFTs with high Hf concentration are more stable against radiation. On the other hand, for circuit application, the stable HIZO TFTs are not necessarily preferred for all circuits. This letter demonstrates that understanding the device-circuit interactions is necessary for device optimization and circuit reliability improvements for harsh electronic systems.

Pulsed latches are gaining increased visibility in low-power ASIC designs. They provide an alternative sequential element with high performance and low area and power consumption, taking advantage of both latch and flip-flop features. While the circuit reliability and robustness against different process, voltage, and temperature variations are considered as critical issues with current technologies, no significant reliability study was proposed for pulsed latch circuits. In this paper, we present a study on the effect of different PVT variations on the behavior of pulsed latches, considering the effect on both the pulser and the latch. In addition, two novel design approaches are presented to enhance the reliability of pulsed latch circuits, while keeping their main advantages of high performance, low power, and small area. Experiments performed using Synopsys 28nm PDK demonstrate the ability of the proposed approaches to keep the same reliability level at different supply voltages and temperatures in the presence of process variations, with a very small area overhead of around 3%. The two proposed designs have negligible power overhead when running at nominal supply voltage, and they have higher yield per unit power when compared with the traditional design at different voltages and temperatures.

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.

With fabrication technology reaching nano levels, systems are exposed to higher susceptibility to soft errors. Thus, development of effective techniques for designing soft error tolerant systems is of high importance. In this work, an integrated soft error tolerance technique based on logical implications and transistor sizing is proposed. In order to reduce implication learning time, a set of source and target nodes with predefined thresholds are selected and implications between these nodes are extracted. Then, the impact of adding a functionally redundant wire (FRW) due to each implication is evaluated. This is done based on identifying an implication path and the gates along the implication path whose detection probabilities will be reduced due to adding the implication FRW. Then, the gain of an implication is estimated in terms of reduction in fault detection probabilities of gates along an implication path. The implication with the highest gain is selected. The process is repeated until the gain is less than a predetermined threshold. The proposed implication-based fault tolerance technique enhances the circuit reliability with minimal area overhead based on enhancing logical masking. However, its effectiveness depends on the existence of such relations in a circuit and can enhance circuit reliability upto a certain level. To enhance circuit reliability to any required level, selective-transistor redundancy (STR) based technique is then applied. This technique is based on providing fault tolerance for individual transistors with high detection probability based on transistor duplication and sizing. Experimental results show that the proposed integrated fault tolerance technique achieves similar reliability in comparison to applying STR alone with lower area overhead.

Resistive switching memories (RRAMs) are one of the most promising alternatives for nonvolatile storage and nonconventional computing systems. However, their behavior, and therefore their reliability, is limited by technology intrinsic constraints. Standard CMOS reliability analyses do not take into account RRAM-related misbehaviors. Consequently, new and more thorough characterization approaches are needed. Even more important, as RRAM is proposed to become a key piece in aerospace solutions, new radiation and temperature analyses should also be considered in reliability-oriented methodologies. This work presents a solution that completely characterizes RRAM and CMOS hybrid circuits under the combined effects of both technology and environmental error sources. The analysis strategy is based on three pillars: the definition of suitable models, the application of user-defined metrics to measure both circuit reliability and performance, and the efficient definition of the design space. These concepts are used by a powerful simulation framework, achieving automatic characterization of RRAM-based circuits by simultaneously considering multiple error sources. As a case of study, a thorough analysis of an RRAM read driver, including RRAM lifetime, circuit temperature, CMOS and RRAM variability, and radiation—both accumulated dose and single particle impacts—highlights the proposed approach capabilities.

Current technology scaling trends aggressively increases the susceptibility of combinational circuit reliability to radiation-induced transient faults (which also known as soft errors). Various gate sizing techniques have been used to reduce soft error rate (SER) in the past, but their main drawback is that they are expensive in term of run time. These methods require changes to adapt to the large scale circuits. In this paper, an efficient circuit partitioning-based gate sizing method is presented, which significantly speeds up the gate sizing optimization process. In the proposed method, the circuit is divided into the topologically levelized small subcircuits by cone structures. Then, the subcircuits which are located in the same level are resized individually and independently. The subcircuit error probability (SEP) metric is introduced to evaluate the contribution of each subcircuit into the total circuit SER. The key idea of the proposed method is to evaluate the effects of each gate sizing on circuit reliability locally using SEP instead of global evaluation by the total circuit SER. Such evaluation results in speeding up the gate sizing optimization process. Experimental results show that the proposed approach is about 280× orders of magnitude faster than the sensitivity-based gate sizing approach [R. R. Rao, D. Blaauw, and D. Sylvester, “Soft error reduction in combinational logic using gate resizing and flipflop selection,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. , 2006, pp. 502–509] while it can achieve up to 45% reduction in circuit SER with less than 17% area overhead. This level of speed and efficiency makes the proposed approach a viable solution to mitigate the SER of very large combinational circuits used in industry.

In sub-10 nm technology nodes, next generation lithography technologies are urgently required, and the diblock copolymer directed self-assembly (DSA) technology has shown its strong potential for contact/via layer fabrication. In addition, post-layout redundant via insertion has become a necessary step to guarantee sufficient yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously deteriorate via manufacturability. In contrast, a sophisticated DSA-aware redundant via insertion algorithm may not only enhance circuit reliability but also improve DSA manufacturability. In this paper, we propose the first work of simultaneous guiding template optimization and redundant via insertion for DSA. Two integer linear programming (ILP)-based algorithms and an efficient graph-based approach are provided. The two ILP-based algorithms optimally maximize via manufacturability and the redundant via insertion rate. In addition, reduction techniques are presented to greatly improve the computational efficiency of ILP. For the graph-based approach, all feasible via patterns composed of original vias and redundant vias are identified. Then, the original problem is transformed into a graph formulation and efficiently optimized. Experimental results show that the ILP-based algorithms can find optimal solutions with reasonable computation time, and the graph-based algorithm can solve the problem much more efficiently and derive near-optimal solutions.

In this study, a single-stage quasi-resonant (QR) AC–DC converter based on buck–boost and flyback circuits is proposed. The forestage buck–boost circuit works in discontinuous conduction mode to achieve a high-input power factor (PF), and the backstage flyback converter, working in QR mode, is responsible for energy transfer. The QR switch mode can improve the efficiency of the converter by decreasing the switch turn-on losses. The single-stage topology can reduce the cost and raise the reliability of the system. The detailed design process is described in this study, and a 50 W prototype was developed that has a maximum PF higher than 0.99 and a maximum efficiency of 90.91% in nominal working conditions.

Reliability mechanisms are undesirable from a product lifetime point of view, but their unique characteristics enable novel applications such as one-time-programmable memory, secure chip odometers, and physical unclonable functions (PUFs). In this invited paper, we will discuss how reliability mechanisms can be leveraged for the aforementioned applications, and then introduce a novel SRAM PUF design where the power up state of the SRAM cell is programmed into a local metal fuse using the electromigration phenomenon for improved stability.

The reliability challenges encountered during the design of radio frequency (RF) and mixed-signal circuits are discussed. RF circuits can operate at voltages greater than twice the nominal supply voltage and thus hot-carrier and off-state aging are key considerations. Mixed-signal circuits also present a reliability challenge due to their stringent matching and offset requirements.

Scan-based testing, though widely used in modern digital designs, causes more power consumption than in functional mode. This excessive power consumption can cause severe hazards such as circuit reliability and yield loss. To solve this problem, a new scan chain reordering method based on care bit density is proposed in this paper. This proposed method helps merging care bits toward the front end of scan chains. Thus, it can reduce scan cell switching activities during scan shift operation. Experimental results on ISCAS’89 benchmark circuits show that the proposed scan chain reordering method reduces test power consumption compared to the previous work.

The embedded temperature sensor which monitors the hot spots of the chip had become an essential circuit for improving the reliability of the system-on-a-chip (SoC). However, most of the temperature sensors cannot resist the influence of voltage variations and results in significant temperature errors. In this paper, the relative reference modeling (RRM)-based temperature sensor is presented. The proposed temperature sensor uses a low-temperature sensitivity voltage classifier and a low-voltage sensitivity proportional to absolute temperature (PTAT) circuit to resist the voltage variations. Addition, the process variations can be eliminated after the three-point calibration. The proposed temperature sensor was fabricated in TSMC 90nm CMOS process. The measured results show that the temperature error of the proposed design is from -1.47°C to 1.40°C with supply voltage 0.9 to 1.1V.

boost circuit has been widely used in photovoltaic generation system and electrolytic capacitor is one of the most vulnerable components in the circuit. Equivalent series resistance (ESR) is an important index to reflect the reliability of capacitor. Real-time online monitoring and evaluation of ESR parameter has great significance to improve the reliability of boost circuit. In this study, a non-invasive online method to monitor and evaluate output capacitor's ESR in boost converter in continuous conduction mode is proposed. The ESR is calculated by sampling two specific periods of output voltage in a switching cycle. The calculation method is verified with the boost circuit model. The experimental results demonstrate the effectiveness of this method.

Among the different multilevel topologies, the modular multilevel converter (MMC) has now become a subject of intense research, where it offers some interesting and useful features. In this project, DC/DC converters are proposed for the HVDC-based systems to reduce the transmission losses. The full-bridge converters and three-level flying capacitor circuits are combined and integrated by employing the phase shift control scheme which can be easily applied to achieve 0-voltage and proposed for the high step-down and HVDC-based systems, and also which has a capability to generate the high-quality power under various conditions. Importantly, in this project the voltage auto-balance ability among the cascaded modules is achieved by the flying capacitor which removes the additional components or control loops, and it also allows the operation at higher frequencies and at higher input voltages without scarifying the efficiency. The neutral point clamped (NPC) converters and flying capacitor-based converters are the major multilevel topologies for the high-power and high-voltage applications. Zero-voltage switching (ZVS) performance for both the leading and lagging switches can be provided to reduce the switching losses by adopting the phase-shift control scheme. The time sequence of the leading leg in the phase-shift-controlled full-bridge converters is kept constant, and only the phase of the lagging leg is shifted to regulate the output voltage. A high DC voltage is required for the DC-based distribution and micro-grid systems to improve the delivery power capability which reduces the transmission losses. The switch voltage stress is reduced, and thus, the circuit reliability is enhanced in this project. The MMC concept can be easily extended to N-stage converter to satisfy the high-voltage applications with low-rated voltage switches. The circuit operation and converter performance are analyzed by simulations. The result of input voltage sharing across the capacitors is of 300 V. Thus, the input voltage auto-balance is achieved excellently. The input voltage is stepped down to 53 V. The modes of operations and converter performance are analyzed and simulated by using P-Sim software. The three-stage converter is designed to increase the step-down ratio when compared to two-stage converter. This operation is similar to the two-stage converter.

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.

This paper presents a single event upset (SEU) resilient, single event transient (SET) filterable and cost effective latch (referred to as RFEL) using 45 nm CMOS commercial technology. By means of triple mutual feedback CMOS structures, one of which is an input-split Schmitt trigger, and two of which are Muller C-elements, the internal nodes and output node of the latch are self-recoverable from single event upset regardless of the energy of a striking particle. The latch filters a much wider spectrum of single event transient on account of hysteresis property of the embedded input-split Schmitt trigger, and temporal redundancy in the grouped inputs of the Muller C-element at output stage. The latch performs with lower overheads regarding area, power, and delay than most of the single event upset and single event transient simultaneously tolerated latches as well. Simulation results show that the area-power-delay-pulse product of the latch is 65.58% saving on average, and Monte Carlo simulation results demonstrate the equivalent or even less sensitivity of the latch to process, and temperature variations, compared with the previous radiation hardened latches.

One of the major challenges in the design of compact microwave structures is the necessity of simultaneous handling of several objectives and the fact that expensive electromagnetic (EM) analysis is required for their reliable evaluation. Design of multi-band circuits where performance requirements are to be satisfied for several frequencies at the same time is even more difficult. In this work, a computationally efficient design of dual-band microstrip couplers is demonstrated by means of an adaptive response scaling (ARS) technique. ARS is a surrogate-assisted method that exploits a fast surrogate of the high-fidelity EM-simulation model of the coupler at hand constructed from its corrected equivalent circuit. ARS identifies nonlinear frequency and amplitude response scaling that accommodates the misalignment between the low- and high-fidelity models. Due to exploiting the knowledge embedded in the low-fidelity model ARS surrogate exhibits excellent generalisation capability. It is demonstrated here by optimisation of a dual-band microstrip coupler with enhanced bandwidth, working at 1 GHz and 2 GHz frequencies. The optimised design has been obtained at the cost of just a few high-fidelity EM simulations of the structure. Numerical comparisons indicate superiority of ARS over competitive surrogate-assisted techniques. Experimental validation is also provided.

Aging effects in advanced technologies produce significant performance degradation as time progresses. In order to guarantee safe operation, aging-delay monitors can be inserted at the output nodes of critical paths (CPs) to allow predictive error detection. However, online monitoring of a large number of CPs that can exist in the state-of-art designs is not feasible. The conventional statistical selection of CPs requires knowledge of the coordinates of each gate in the corresponding layout of the circuit to account for spatial correlation between devices’ process parameters. This paper presents a nonspatial-correlation-dependent methodology to select the CPs for aging-delay monitoring for predictive error detection. Spatial correlation is bounded by a statistical approach maximizing CPs’ coverage. The proposed early selection methodology is validated by comparing the obtained results with those obtained with the availability of spatial correlation information extracted from the circuit layout. The results clearly show that the set of CPs selected with the proposed early selection methodology is in good agreement with the one selected with the availability of layout information. Therefore, our proposed methodology is very attractive to be used in the early design stages, where detailed circuit layout is not available.

In this study, electrical constant stress method which is one of accelerated tests is applied to power vertical double diffused MOSFETs continued up to 6 hours. The stress induced changes of characteristic parameters (threshold voltage, mobility, etc.) of power MOSFETs are extracted. A resistive load NMOS inverter is set up and degraded power MOSFET effects on its static parameters are investigated experimentally. Besides the obtained experimental results, a simple circuit model is proposed to simulate the stress induced changes in NMOS inverter static parameters. In this manner, obtained experimental results are supported by simulation study. Proposed degradation model has ability to help designers to predict circuit reliability in the early stages of design.

CMOS wear-out mechanisms, especially Bias Temperature Instability (BTI), have caused growing concerns about circuit reliability. For cache memories, BTI reduces the static noise margin (SNM), causing unreliable read operations. In practice, error-correction codes (ECCs) are often used to protect data from transient errors in caches, but the limited error correction capabilities are not always enough to overcome BTIinduced read failures. In this paper, we propose a cell flipping technique with distributed refresh phases (CFDR) to minimize cache degradations. The CFDR method flips and refreshes each cache block at different times, minimizing the interruption time and balancing the degradation rate, even for infrequently replaced cache blocks. We evaluate the CFDR technique on an instruction cache in a 32-bit ARM architecture and show our method reduces the number of error bits by 58.86% and 13.59%, compared with an ECC scheme and a traditional cell flipping technique. The cache lifetime can be improved by 125% by using CFDR with less than 1% area overhead, which is not only more effective but also more cost-efficient than the existing techniques.

The monitoring circuit is widely applied in radiation environment and it is of significance to study the circuit reliability with the radiation effects. In this paper, an intelligent analysis method based on Deep Belief Network (DBN) and Support Vector Method is proposed according to the radiation experiments analysis of the monitoring circuit. The Total Ionizing Dose (TID) of the monitoring circuit is used to identify the circuit degradation trend. Firstly, the output waveforms of the monitoring circuit are obtained by radiating with the different TID. Subsequently, the Deep Belief Network Model is trained to extract the features of the circuit signal. Finally, the Support Vector Machine (SVM) and Support Vector Regression (SVR) are applied to classify and predict the remaining useful life (RUL) of the monitoring circuit. According to the experimental results, the performance of DBN-SVM exceeds DBN method for feature extraction and classification, and SVR is effective for predicting the degradation

This paper presents a standard DC bus conditioner circuit and highlights safety issues with a floating electric drive configuration in a low leakage and ground current environment. A novel circuit is developed for automatic discharge of the bus conditioner capacitor during the drive shut down. It uses DC bus voltage as an input and a control relay to discharge the capacitor across a resistor. Functional tests were conducted on a 480/690VAC system to assess the performance of the system and circuit reliability. The circuit is validated and results are presented.

With nowadays nanometer-CMOS technologies, time-zero and time dependent variability effects (like BTI, CHI, RTN, TDDB, EM, etc) have turned into an even more serious threat to the desired performance of analog and digital integrated circuits. Statistical characterization and modelling of these variability effects entail large testing times, which are typically prohibitive, and huge amounts of data, which are complex to post process. This paper describes novel characterization techniques that overcome these limitations, that is, they are capable of statistically testing nanometer CMOS devices with much shorter completion times. To properly handle the massive amounts of data from characterization, new extraction methods, described in this paper as well, have been developed. With these methods, an accurate variability-aware device model is completed, which can subsequently be used in reliability-aware circuit design methodologies.

In current CMOS advanced technology nodes, accurate extraction of transistor parameters affected by time-dependent variability, like threshold voltage (Vth) and mobility (μ), has become a critical issue for both analog and digital circuit simulation. In this work, a precise VTH0 and U0 BSIM parameters extraction methodology is presented, together with a straightforward IDS to VTH0 shift conversion, to allow the complete study of device aging effects for reliability circuit simulation.