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A fully hardware-based real-time digital wide-band quadrature demodulation processor based on the Hilbert transform is described for processing ultrasound radio frequency signals. The results have shown that the implementation by using only slices and dedicated digital multipliers of a low-cost and low-power field-programmable gate array (FPGA) is accurate relative to a comparable software-based system and they are obtained with a piezoelectric transducer without postprocessing.

A back-end processing system involving high-speed signal processing functions to form and exhibit an image is developed for real-time visualization of the mouse heart. The studies have shown that high-speed back-end processing system is capable of providing high spatial resolution images with fast temporal resolution.

We present a channel signal-to-noise ratio (SNR) estimator for M-ary phase shift keying (M-PSK) and differential M-PSK. The estimator is non data aided and is shown to have the following advantages: 1) It does not require prior carrier synchronization; 2) the estimator has a compact fixed-point hardware implementation suitable for field-programmable gate arrays and application-specific integrated circuits; 3) it requires only 1 sample/symbol; 4) accurate estimates can be generated in real rime; and 5) the estimator is resistant to imperfections in the automatic gain control circuit. We investigate the proposed estimator theoretically and through simulations. In particular, we investigate the required quantization necessary to achieve a good estimator performance. General formulas are developed for SNR estimation in the presence of frequency-flat slow fading, and specific results are presented for Nakagami-m fading. The proposed estimator is then compared with other SNR estimators, and it is shown that the proposed method requires less hardware resources while, at the same time, providing comparable or superior performance. Index Terms--Application-specific integrated circuit (ASIC), binary phase-shift keying (BPSK), carrier loop, channel estimation, demodulation, differential phase-shift keying (DPSK), digital communications, efficient, estimation, fading, field-programmable gate array (FPGA), fixed-point, hardware, implementation, M-ary phase-shift keying (MPSK), modulation, Nakagami, phase-locked loop, quaternary phase-shift keying (QPSK), real-time, receivers, signal-to-noise ratio (SNR), synchronization, wireless.

The CDF Run II [1] Level 2 calorimeter trigger is implemented in hardware and is based on a simple algorithm that was used in Run I. This system has worked well for Run II at low luminosity. As the Tevatron instantaneous luminosity increases, the limitation due to this simple algorithm starts to become clear. As a result, some of the most important jet and MET (Missing ET) related triggers have large growth terms in cross section at higher luminosity. In this paper, we present an upgrade of the L2CAL system which makes the full calorimeter trigger tower information directly available to the Level 2 decision CPU. This upgrade is based on the Pulsar [2], a general purpose VME board developed at CDF and already used for upgrading both the Level 2 global decision crate [3] and the Level 2 Silicon Vertex Tracking [4]. The upgrade system allows more sophisticated algorithms to be implemented in software and both Level 2 jets and MET can be made nearly equivalent to offline quality, thus significantly improving the performance and flexibility of the jet and MET related triggers. This is a natural expansion of the already-upgraded Level 2 trigger system, and is a big step forward to improve the CDF triggering capability at Level 2. This paper describes the design, the hardware and software implementation and the performance of the upgrade system. Index Terms--Calorimeter, CDF, FPGA, HEP, trigger.

Bilateral control systems are strongly required to apply to endoscopic surgeries. It is necessary that the system has enough degrees of freedom for applying various operation procedures including endoscopic surgery. When the degrees of freedom of the system are increased, the amount of control calculation is also increased, and it is hard to keep sampling periods short. The bilateral control systems, however, require comparatively shorter sampling periods, particularly the control system based on an acceleration control system. Hence, it is a difficult issue to increase the degrees of freedom of the bilateral control system. In this paper, the sampling period is kept short in the multi-degree of freedom system by using field programmable gate arrays as processors. The bilateral control system based on the acceleration control system is implemented in a robot system, which has 12 DOF, and some experimental results are shown, and the errors between the response of the master and slave robots are discussed. Index Terms--Acceleration control, bilateral control, field-programmable gate array (FPGA), surgical robot.

The 'split ADC' architecture enables continuous digital background calibration by splitting the die area of a single ADC design into two independent halves, each converting the same input signal. The two independent outputs are averaged to produce the ADC output code. The difference of the two outputs provides information for a background-calibration algorithm. Since both ADCs convert the same input, when correctly calibrated, their outputs should be equal, and the difference should be zero. Any nonzero difference provides information to an error-estimation algorithm, which adjusts digital-calibration parameters in an adaptive process similar to a least mean square algorithm. This paper describes the calibration algorithm implemented in the specific realization of a 16-bit 1-MS/s algorithmic cyclic ADC. In addition to correcting ADC linearity, the calibration and estimation algorithms are tolerant of offset error and remove linear scale-factor-error mismatch between the ADC channels. Simulated results are presented confirming self-calibration in approximately 10 000 conversions, which represents an improvement of four orders of magnitude over previous statistically based calibration algorithms. Index Terms--Adaptive systems, analog-digital conversion, calibration, digital background calibration, mixed analog-digital integrated circuits, self-calibrating.

This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs. Index Terms--Barrel shifter, coordinate rotation digital computer (CORDIC), extended range, low area and high throughput implementation.

The novel field-programmable-gate-array (FPGA) technology is able to combine an embedded processor and an application intellectual property to be a system-on-a-programmable-chip developing environment. Therefore, this paper presents a motion control IC for the X-Y table under this novel FPGA technology. The proposed motion control IC has two modules. One module performs the functions of the motion trajectory and two position/speed controllers for the X-Y table. The other module performs the functions of two current vector controllers of permanent-magnet synchronous motor drives. The former is implemented by software using a Nios II embedded processor due to the complicated control algorithm and low-sampling-frequency control (motion trajectory and position control: less than 1 kHz). The latter is implemented by hardware in the FPGA owing to the requirements of high-sampling-frequency control (current loop: 16 kHz; PWM circuit: 4-8 MHz) but simple computation. As a result, the hardware/software codesign technology can make the motion controller of the X-Y table more compact, flexible, perform better, and less costly. Index Terms--AC motor drives, field-programmable gate arrays (FPGAs), fuzzy control, motion control.

In this paper, we examine the potential of applying concatenated low-density parity-check (LDPC) and Bose-Chaudhuri-Hocquenghem (BCH) coding for magnetic recording read channel with a 4 kB sector format. One key observation for such concatenated coding systems is that the overall error correction capability can be improved by exploiting the iteration-by-iteration bit error number oscillation behavior in case of inner LDPC code decoding failures. Moreover, assisted by field programmable gate array (FPGA)-based simulation platforms, empirical error-correcting performance analysis can reach a very low sector error rate (e.g., [10.sup.-10] and below), which is almost infeasible for LDPC-only coding systems. Finally, concatenated coding can further reduce the silicon cost. By implementing a high-speed FPGA-based perpendicular recording read channel simulator, we investigate a 4 kB rate-15/16 concatenated coding system with a 512-byte rate-19/20 inner LDPC code and an outer 4 kB BCH code. We apply a decoding strategy that can fully utilize the bit error number oscillation behavior of inner LDPC code decoding, and show that its sector error rate drops down to [10.sup.-11]. For the purpose of comparison, we use the FPGA-based simulator to empirically observe the performance of 4 kB rate-15/16 LDPC and Reed-Solomon (RS) codes down to [10.sup.-7]-[10.sup.-8]. Finally, we estimate the silicon cost of this concatenated coding system at 65 nm node, and compare it with that of the RS-only and LDPC-only coding systems. Index Terms--Application-specific integrated circuit (ASIC), BCH, concatenated, field programmable gate array (FPGA), low-density parity-check (LDPC).

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex. Index Terms--Field-programmable gate array (FPGA), low-pass (LP) delta-sigma (DS), RF transmitter.

This paper investigates the multisampling techniques applied to the current control in active-power-filter (APF) applications. In APF applications with digital control, the main bandwidth limitation derives from A/D conversion and computational delays and the sampling-related delay of the digital pulsewidth modulation (DPWM). Using field-programmable gate arrays and fast A/D converters for the control implementation, it is possible to minimize the former two; thus, the overall phase lag is dominated by the DPWM, which can strongly be reduced by the multiple-sampling approach, breaking bandwidth limitations of single-sampled solutions. Moreover, as the multisampling approach triggers nonlinear behaviors that can negatively impact the filter-compensating capabilities, a solution based on a simple digital filter is proposed which linearizes the system behavior and does not waste the multisampling advantages. Simulation and experimental results on a 10-kVA prototype confirm the theoretical expectations. Index Terms--Active power filters (APFs), digital control, multisampling.

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost. Index Terms--Aerospace industry, fault injection, fault tolerance, field programmable gate arrays (FPGAs), proton accelerator, radiation effects, reliability, single-event upset (SEU), triple modular redundancy (TMR).

As SRAM-based field-programmable gate arrays (FPGAs) are introduced in safety- or mission-critical applications, the availability of suitable Electronic Design Automation (EDA) tools for predicting systems dependability becomes mandatory for designers. Nowadays designers can opt either for workload-independent EDA tools, which provide information about system's dependability disregarding the workload the system is supposed to elaborate when deployed in the mission, or workload-dependent approaches. In this paper, we compare two tools for predicting the effects of soft errors in circuits implemented using SRAM-based FPGAs, a workload-independent one (STAR) and a workload-dependent one (FLIPPER). Experimental results show that the two tools are complementary and can be used fruitfully for obtaining accurate predictions. Index Terms--Dependability, fault injection, field-programmable gate array (FPGA), single-event effects (SEVs), triple modular redundancy (TMR).