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In this work, we demonstrate a novel In0.52Al0.48As based top-illuminated avalanche photodiode (APD), designed to circumvent the problem of serious bandwidth degradation under high gain (>100) and high power operation and significantly enhance the dynamic range in the established frequency modulated continuous wave (FMCW) lidar system. In our APD design, the carriers transiting through the dual multiplication (M-)layers are subjected to a stepped-up electric field profile, so they can be energized by the first step and propagate to the second step to trigger the avalanche processes. Such a cascade avalanche process leads to an ultra-high gain bandwidth product (460 GHz) with a 1 A/W responsivity at unit gain. Compared to the high-performance and commercial p-i-n PD and photo-receiver (PD + trans-impedance amplifier (TIA)) installed in the same lidar test bed, our demonstrated APD receiver (without TIA) has a larger S/N ratio under high operation gain (33 A/W) with less optical local-oscillator (LO) power required (0.25 vs. 0.5 mW), while exhibiting a wider dynamic range in each pixel. These advantages in turn lead to the construction of a better quality of 3-D lidar image by using the demonstrated APD.

Low-dimensional photodetectors, in particular those in photoconductive mode, often have extraordinarily high photogain. However, high gain always comes along with a slow frequency response. The gain-bandwidth product (GBP) is a figure of merit to evaluate the performance of a photodetector. Whether the high-gain photoconductors can outperform standard PIN photodiodes in terms of GBP remains an open question. In this article, we derived the analytical transient photoresponses of nanowire photoconductors which were validated with the simulations and experiments. Surprisingly, the fall transients do not follow a simple time-dependent exponential function except for some special cases. Given the analytical photogains that were established previously, we derived the theoretical GBP of high-gain nanowire photoconductors. Analysis of the analytical GBP indicates that nanoscale photoconductors, although having extremely high gain, will never outperform typical PIN photodiodes in terms of GBP.

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

The present investigation is focused on the analog/RF performance of ferroelectric (FE) based substrate metal oxide semiconductor field effect transistor (MOSFET) for digital application as an inverter. Short channel effect (SCEs) reduced significantly with improvement in switching ratio (Ion/Ioff). The simulation shows the immunity towards the parameters like transconductance (gm), transconductance generation factor (TGF), early voltage (VEA) and the intrinsic gain (AV) which allows the device to look into digital application. Also, the RF performance parameters come out to be superior for the proposed device structure, as the gain frequency product (GFP) and gain bandwidth product (GBP) enhanced by 100 and 10 folds, respectively. Further, RF investigation shows the enhanced results as attributed with peak values for transconductance frequency product (TFP) and gain transconductance frequency product (GTFP). The transient analysis shows an improvement in the noise margin (NM) for FE-MOSFET structure. Thus, the proposed architecture can be an attractive alternative for the digital application.

This paper examines the effects of temperature variation on Hetero Gate Oxide Dual Work Function Step Channel Tunnel Field-Effect Transistor (HGO-DW-SCTFET). For different temperatures, the proposed device performs better in comparison with conventional Step Channel Tunnel Field-Effect Transistor (SCTFET). This study includes a temperature-based analysis on DC and Analog parameters like drain current, threshold voltage (Vth), Sub-threshold Slope (SS), ION–IOFF ratio, trans-conductance, gate drain capacitance (Cgd), cut off frequency (fT), Trans-conductance-frequency product (TFP), Trans-conductance generation factor (TGF), Gain Bandwidth Product (GBP), Transit Time (TT) to analyze its performance at various temperatures and various models named BT-BT, SRH, and TAT, along with the linearity analysis, and the reliability of the device. The variation in DC and Analog parameters shows that the proposed device can be used for the applications of high temperature. To examine the performance of the device, a wide range of temperatures of 250K to 400K has been taken in the TCAD simulator.

This paper presents the continuous 2D analytical modelling of electrostatic potential, threshold voltage (Vth), subthreshold swing, drain induced barrier lowering (DIBL) and drain current of asymmetric junctionless dual material double gate MOSFET with high K gate stack (AJDMDG Stack MOSFET). The electrostatic potential is achieved by solving Poisson’s equation with the help of the parabolic approximation method. Analytical results are verified by using ATLAS TCAD Device simulator. A comparative study of short channel effects (SCEs) of AJDMDG Stack MOSFET and asymmetric junctionless dual material double gate MOSFET with high K gate stack (SJDMDG Stack MOSFET) has been observed in order to show the efficacy of asymmetry condition such as gate oxide asymmetry, gate work function asymmetry etc. for suppressing SCEs. Further, analog/RF performance parameters such as transconductance (gm), output resistance (rout), intrinsic gain, transconductance generation factor (TGF), cut-off frequency (fT), maximum frequency (fmax), gain bandwidth product (GBW) etc. of AJDMDG Stack MOSFET are observed and compared the results with SJDMDG Stack MOSFET structure. Results reveal that AJDMDG Stack MOSFET has better efficacy for RF applications.

We consider the integrated circuit design and the measurement results of test crystals for the 12-bit sigma-delta analog-to-digital converter (ADC) based on 180 nm silicon-on-insulator (SOI) technology from X-FAB. The ADC processes input signals in the frequency range up to 100 kHz in the temperature range of –40…+175 °C with the supply voltage equal to 3.3 V and the modulator clock frequency equal to 10 MHz. The circuit consists of the 5-th order switched-capacitor low-pass pre-filter to limit the input signal spectrum, the cascade connection of the second order sigma-delta modulators, and the digital decimation filter to reduce the clock frequency by 48 times. The main blocks of cutoff filter and modulator are assembled according to the balanced scheme on integrators based on operational transconductance amplifiers with the unity gain bandwidth of 63 MHz. The dynamic element matching circuit is used to expand the dynamic range of converter. It reduces the level of nonlinear distortions in digital-to-analog converters in the feedback circuits of modulator. The value of the SINAD parameter is not worse than 68 dB for converting the signal with the differential amplitude equal to 500 mV at the frequency of 100 kHz.

A new Ge/SiGe heterojunction double-gate tunnel field effect transistor (DGT) model with hetero dielectric gate and Gaussian doping drain region is investigated for the first time. The introduction of heterojunction with hetero dielectric will reduce band-to-band tunneling (BTBT) leakage current while maintaining high mobility to enhance drain current and transconductance characteristics of the device significantly. Along with that, the combined effect of analytical drain doping profile (Gaussian) and hetero dielectric suppresses the ambipolar behavior. Different DC characteristics of the device like energy band analysis, electric field, drain current and BTBT generation rate are analyzed for the proposed structure. RF figure of merit for the HD-HJDGT-GD is express by analyzing its transconductance (gm), cut off frequency (fT), maximum oscillation frequency (fmax), gain bandwidth product (GBP) and transconductance frequency product (TFP). The outcome of the model under study is compared with conventional DGT. It is apparent from the analysis that the recommended model has better DC and RF performance, which makes this device worth studying to be used in high-frequency applications. TCAD simulation is performed by using Sentaurus 2D device simulator from Synopsys.

A novel raised source and recessed drain dopingless tunneling FET (RSRD-DL-TFET) is proposed in this paper. By using TCAD simulation, the DC electrical characteristics, energy-band diagrams, carrier concentrations and band-to-band tunneling generation rate of RSRD-DL-TFET are analyzed, as compared with planar dopingless tunneling FET (PDL-TFET). Besides, analog/RF and transient performances for both devices are also investigated, including transconductance, parasitic gate capacitance, cut-off frequency, gain bandwidth product and fall propagation delay. Benefiting from the design of raised source and recessed drain, the proposed device not only creates the line tunneling in the source region, but also reduces the ambipolar tunneling distance at drain/channel interface. As a result, the proposed RSRD-DL-TFET could provide higher on-current, steeper subthreshold swing, lower ambipolar current, higher cut-off frequency and better transient performance than PDL-TFET.

Emerging layered semiconductors present multiple advantages for optoelectronic technologies including high carrier mobilities, strong light-matter interactions, and tunable optical absorption and emission. Here, metal-semiconductor-metal avalanche photodiodes (APDs) are fabricated from Bi2O2Se crystals, which consist of electrostatically bound [Bi2O2]2+ and [Se]2− layers. The resulting APDs possess an intrinsic carrier multiplication factor up to 400 at 7 K with a responsivity gain exceeding 3,000 A/W and bandwidth of ~ 400 kHz at a visible wavelength of 515.6 nm, ultimately resulting in a gain bandwidth product exceeding 1 GHz. Due to exceptionally low dark currents, Bi2O2Se APDs also yield high detectivities up to 4.6 × 1014 Jones. A systematic analysis of the photocurrent temperature and bias dependence reveals that the carrier multiplication process in Bi2O2Se APDs is consistent with a reverse biased Schottky diode model with a barrier height of ~ 44 meV, in contrast to the charge trapping extrinsic gain mechanism that dominates most layered semiconductor phototransistors. In this manner, layered Bi2O2Se APDs provide a unique platform that can be exploited in a diverse range of high-performance photodetector applications.

This paper presents a quantum analytical modeling of UTBB SOIMOSFET as lateral dual gate for the first time. In this paper, a 2-dimensional analytical modeling of electric field distribution, threshold voltage (Vth), surface potential and drain current (ID) have been developed and then including Quantum mechanical effects (QMEs)in it. The proposed model provides an expression for Vth shift due to QMEs, which can be used for compact modeling as a quantum correction term. The results of quantum analytical modeling have been verified with the results achieved from numerical TCAD device simulator. Different analog/ radio frequency (RF) performance parameters like transconductance (gm), output resistance (RO), transconductance generation factor (TGF), intrinsic gain (gm*RO), cut-off frequency (fT), gain bandwidth product (GBW), maximum frequency of oscillation (fmax) etc. has been investigated. The effect of negative voltage on the control gate on RF/analog performance parameters has been studied. Result reveals that the potential of UTTB SOI MOSFET with lateral dual gate becomes a choice for analog and mixed signal SOC applications.

This paper reports an unique approach to suppress ambipolarity and enhance drive current in tunnel field effect transistor (TFET) by incorporating vertically extending drain in double gate Si1−xGex source TFET. This structure has dual source extending laterally on both sides of the channel with vertically extended drain over the T-shaped channel (VD-DG-Si1−xGexS-TFET). Our study is based on calibrated exhaustive 2-D TCAD simulations. It advocates that the device performance is not only retained but significantly enhanced even by deploying only double gate instead of quadruple gate with Si1−xGex sources. Further the drive current can be significantly increased by optimizing the mole fraction (x) in Si1−xGex source. Our study reveals that the average subthreshold slope (SSavg) is 23.98 m V/dec (point SS (SSpoint) is 12.7 m V/dec with sub-60 m V/dec point SS for 107 orders of current change), drive current (ION) is 2.73× 10− 4 A/um and 46% improvement in transconductance as compared to the earlier reported drain engineered quardruple gate TFET. Further the device sensitivity analysis with respect to gate oxide dielectric constant, gate metal work-function, temperature and germanium mole fraction variation is also analyzed here. Moreover, in terms of device analog behaviour, the cut off frequency (ft) is reported as 38.93 GHz and 140% increment in gain bandwidth product (GWB) as compared to its quardruple gate alternative. This study proves the potentials of considered device structure as a promising candidate for ultra low power analog/RF and digital logic applications.

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have large gain bandwidth product (GBP) and low excess noise due to the low impact ionization coefficient ratio of silicon. Optical receivers using APDs are able to achieve high-speed and energy efficient optical transceiver systems. We demonstrate a waveguide Si-Ge APD with low breakdown voltage of −10 V, achieving 60 Gb/s PAM4 successfully. A compact APD circuit model was constructed to allow photonic devices and transceiver circuitry co-design. The APD receiver has achieved −16 dBm sensitivity at 50 Gb/s PAM4 with a bit error rate (BER) of 2.4 $\times \,10^{-4}$ . The sensitivity of APD receivers changes with the multiplication gain. In our analysis, compared to a PIN PD receiver the APD receiver operating at optimum gain can obtain $\sim$ 8 dB more sensitivity for NRZ signaling at $ 50 Gb/s and 3–4 dB more sensitivity for PAM4 signaling at 50–100 Gb/s. Also, the APD receiver operating at optimum gain can reduce power consumption by $\sim\!\text{10}\%$ at PAM4 data rates of 50 Gb/s and $\sim\!\text{15}\%$ at 100 Gb/s in a silicon carrier-depletion microring modulator based WDM photonic link.

This study introduces the design of a practical three-stage operational amplifier (op-amp) using nested Miller compensation, particularly for piezoelectric actuators. Driving a piezoelectric actuator represents a challenge in amplifier design due to its large capacitive nature. A stable piezo driver needs to be free of oscillations and phase lag. Direct feedback compensation using a conventional Miller capacitor is an effective method as long as the capacitance of the load is considerably close to the value of the Miller capacitor. However, using a large capacitor causes a decrease in the slew rate and gain bandwidth. To avoid this, our design focused on the utilization of nested Miller compensation technique. A prototype of the design working at 100V peak to peak voltage (Vpp) is implemented using commercial off-the-shelf (COTS) components. The measurements show the successful driving capability and step-response of the op-amp design. In the design, Widlar current source is also utilized for thermal stability and short circuit protection. According to simulation results, the proposed op-amp has a slew rate of 0.5 V/μs, an open loop gain of 90dB with 3MHz Gain Bandwidth Product (GBP) and phase margin of 77°, and a common mode rejection ratio (CMRR) of 62dB.

In this article, we propose an extended-source double-gate tunnel field-effect transistor (ESDG-TFET) to enhance the dc and analog/RF performance. The source of an ESDG-TFET is extended into channel to increase the line and point tunneling in the device at the source–channel junction. 2-D simulations in the TCAD tool (ATLAS) are carried out to analyze and investigate the performance of the proposed device. At optimized device structural parameters, the ESDG-TFET provides a low threshold voltage of 0.42 V, a low subthreshold swing of 12.24 mV/decade, and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ of $2.57\times 10^{{12}}$ . Furthermore, the proposed device achieves a maximum transconductance of 238 $\mu \text{S}/\mu \text{m}$ , a cutoff frequency of 37.7 GHz, and a gain bandwidth product of 3.4 GHz.

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance ( g m ) cut-off frequency ( f T ) , gain bandwidth product and maximum oscillating frequency ( f max ) . Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

Obtaining a photomultiplication-type organic photodiode with a high gain–bandwidth product is challenging. We show that a newly designed regioregular polymer enables the formation of a highly oriented face-on structure with a low trap density, leading to a high EQE and a fast response time. As a result, a gain–bandwidth product of over 4 × 105 Hz is achieved.

This paper presents the design and post-layout simulation of a two-stage operational amplifier (opamp) with Miller compensation, using a third stage that acts as output buffer to drive large loads. The TSMC 0.18μm PDK was used for the design, simulation and implementation in Cadence Virtuoso. The opamp exhibits 20μW power consumption with a 1-V rail-to-rail supply. Post layout simulation shows a unity gain bandwidth (UGBW) of 69.18 MHz $(A_{v}=\mathbf{49.63dB})$ with a phase margin (PM) larger than 86° and a Slew rate of $19.87\mu\mathrm{V}_\mathrm{s}$ ; making our design suitable for small and large signal applications.

The paper presents a dual low voltage chopper offset-stabilized operational amplifier with symmetrical RC notch filters, having a 1.6-5.5 V supply range, and being fabricated in a 0.25 µm CMOS process. The chopping frequency is 100 kHz. A new constant-gm technique is implemented within the input stage of main amp, improving most electrical performances. The amplifier has a typical offset voltage of 1 µV, a minimum PSRR of 128 dB, a minimum CMRR of 120 dB, a noise PSD of 42 nV/√Hz, 1.5 MHz unity gain bandwidth, and THD + noise of 0.001 % at 1 kHz, while consuming 70 µA per channel.

This study presents a systematic review of junctionless tunnel field effect transistor (JLTFET)–based homo- and hetero-based devices/circuits which have gained significant popularity in recent years for their performance. The divergent ranges of JLTFET-based structures are explored, and their DC/AC characteristics are discussed in detail. Basically JLTFET device exploits the advantages of both junctionless FET (JLFET) and tunnel FET (TFET) together to vanquish the major challenges that are faced by contemporary FETs. The hetero JLTFETs studied in this review uses lower band gap materials, silicon and SiXGeX-1 and high band gap material, AlGaAsat source and channel side, respectively. Also dual material gate structure in hetero JLTFET is explored for their performance improvement. Both homo and hetero structures exhibit better performance in terms of DC parameters, subthreshold slope (SS), ON-current, OFF-current and electron tunnelling rate, whereas AC parameters include unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), gain bandwidth product (GBW), transconductance generation factor (TGF) and delay. The silicon-on-nothing (SON) technology–based JLTFET is studied for the performance improvement by using different dielectric materials. With respect to circuit-related study, JLTFET uses SiGeN + pocket under the gate region which act as an inverter circuit with good transient and voltage transfer characteristics (VTC). For memory circuits like SRAM, JLTFET shows better performance in terms of hold static noise margin (SNM), read SNM and write SNM.

Owing to the transition metal dichalcogenides strong light-matter interaction and distinctive materials properties. But low carrier mobilities limited the performance of the device. Here we demonstrate an efficient plasmonic slot photodetector based on integrating MoTe2 in silicon photonics. Narrowing the source-drain distance to tens of nm enables high gain-bandwidth-product detectors.

This paper presents a comparison on Complementary and Recycling FC Amplifier. Complementary folded cascode amplifier is having large O/P swing with high gain of ordinary amplifier in complementary form. This is important to re-circuit again and again for their better slew rate, gain, bandwidth and transconductance. Recycling FC amplifier is similar to complementary FC amplifier and power can be recycled with few input parameters, to make simpler and easy to analyse. The cascode amplifier is connected with common source terminal and common gate terminal. The bandwidth of cascode amplifier is high because of the miller effect, it is eliminated. The system is connected with cascode and overall gain is high, takes few transistors for design of a cascode amplifier. A SR can allow frequency up to the range for that will eliminates unwanted signal. A unity gain bandwidth is applied to eliminate smaller signal. A SR of complementary FC amplifier is good at 3.3V/µs where as 6.3V/µs is for recycling folded cascode amplifier. The power consumption is 690µW and 710µW of complementary folded cascode and recycling folded cascode amplifier respectively. The voltage gain is above 70.7% of is considered as amplification for all ranges of its amplitude.

A time-based operational amplifier (OP-AMP) with high gain and a wide bandwidth is presented in this paper. The proposed OP-AMP utilizes voltage-controlled oscillator (VCO) as an ideal integrator to replace the conventional voltage-based error amplifier which provides infinite DC gain. The OP-AMP is compensated with a feed-forward G m amplifier with capability of driving load capacitance up to 200pF. Proposed OP-AMP uses only 2pF of on-chip capacitor and consumes low quiescent current (70μA at typical corner and temperature). It further utilizes time-based offset cancellation technique to reduce the effect of mismatch between VCOs. The proposed OP-AMP was designed in TSMC 65nm CMOS LP process technology with input/output common mode voltages as 0.3V-0.7V and input power supply of 1.2V; achieving unity gain bandwidth (UGB) of 36MHz. A case study involving reference buffer for a 12-bit SAR ADC and a track and hold circuit are presented to demonstrate the versatility and performance of the proposed OP-AMP.

This work investigates design consideration of Gate Electrode Workfunction Engineered (GEWE) silicon nanowire MOSFET at room temperature. It is perceived from the results that the parasitic capacitances are higher in the deep inversion region, however; the coupling of parasitic capacitance is weak in GEWE-SiNW due to lower gate metal workfunction at the drain end. Moreover, the influence of drain voltage on Cgs is very less owing to constant depletion charges at the source side which results in almost constant value of Cgs with the change in Vds. With tuning of channel length (Lg) and oxide thickness (tox), the effect of capacitances in GEWE-SiNW further reduces significantly due to quantization effect at such scaled dimensions. Furthermore, Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) have also been calculated with an aim to analyze the device DC and switching performance as they are directly or indirectly linked with parasitic capacitance. Calibrated 3D simulations validate that the GEWE-SiNW MOSFET exhibit 2.57, 34.5 and 2.75 times improvement in TFP, EDP and GBP respectively in comparison to SiNW in the linear region.

Silicon-germanium (Si-Ge) avalanche photodiodes (APDs) have superior gain bandwidth product due to the low impact ionization ratio of silicon. To enable efficient optical transceiver systems, cosimulation environments are essential for optimization of optical devices and transceiver circuitry. A compact Si-Ge APD circuit model, which captures both electrical and optical dynamics over a wide range of multiplication gain, is presented. This model includes effects of carrier transit time, avalanche buildup time and electrical parasitics. Model parameters are extracted by small-signal measurement and impulse response measurement where three gain regimes are discussed corresponding to the different mechanisms of carrier transit time and electrical parasitics. Simulated and measured bandwidth versus gain have a good agreement for APD multiplication gains from M = 1 to M = 17. Excellent matching between simulated and measured 25 Gb/s eye diagrams at M = 2 and M = 5.9 is achieved.

This brief presents a novel compact CMOS Fully Differential Difference Amplifier (FDDA) structure suitable for extremely low-voltage low-power applications. Unlike the conventional FB-DDAs that employ two differential pairs, the proposed structure employs one differential pair of multiple-input bulk-driven MOS transistor (MI-BD MOST) that results in reduced count of current branches and, consequently, of power consumption. The proposed FDDA has the simplest CMOS structure presented in the literature so far. Furthermore, while the voltage supply is 0.5 V and the power consumption is 246.6 nW the circuit enjoys rail-to-rail input common mode range (ICMR), high common mode rejection ratio (CMRR) of 100.3 dB @ DC, power supply rejection ratio (PSRR) of 127.8 dB@ DC, voltage gain of 61.4 dB and gain bandwidth product of 6.98 kHz for 30 pF capacitive load. The total harmonic distortion (THD) is less than 0.08% for 500 mV/1 kHz input sine wave signal. The circuit was designed and simulated in Cadence/Spectre environment using 0.18 µm CMOS process from TSMC.

In this work, the authors investigate analogue and radio-frequency (RF) figures-of-merit (FOM) of electrostatically-doped ferroelectric Schottky-barrier tunnel field-effect transistor (FET) (ED-FE-SBTFET) by deploying PZT (lead zirconium titanate) gate stack and dopant-free technology. This PZT gate stack results in negative capacitance behaviour as a result of the positive feedback among the electric dipoles within it. It realises an intrinsic amplifier to amplify the surface potential due to the applied gate bias and enhances the gate controllability significantly. As a result it facilitates lower ambipolar current, considerably high drive current and faster switching transitions. As the structure is realised by using dopant-free technique it ensures simplified fabrication process as it avoids the need of ion implantation and thermal annealing, reduces thermal budget. Here, a detailed comparison is carried-out between charge plasma Schottky-barrier tunnel FET and ED-FE-TFET for their high frequency FOMs such as cut-off frequency ( f T ), gain bandwidth product, transconductance generation factor and so on. The higher I ON / I OFF ratio of ED-FE-SBTFET reduces the static and dynamic both types of powers in digital circuits, while higher g m / I D ratio ensures lower bias power of an amplifier.

This work realises a hetero-dielectric buried oxide vertical tunnel held effect transistor (HDB VTFET) and investigates its radio frequency (RF) and linearity characteristics. First time, the concept of hetero-dielectric buried oxide (BOX) in VTFET is used to obtain the superior improvement in terms of different RF and linearity hgure of merits such as C gs , C gd , C gg , f T , Gain Bandwidth Product (GBP), t, Transconductance Frequency Product (TFP), Transconductance Generation Factor (TGF), g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 and 1-dB compression point. Also, the influence of HfO2 BOX length scaling on these FOMs is analysed. The results reveal that the HDB VTFET can be a promising contender to replace bulk metal-oxide semiconductor held-effect transistors in analogue/mixed signal system-on-chip and high-frequency microwave applications and the accuracy of this device is validated by TCAD Sentaurus simulator.

A voltage-controlled current amplifier/attenuator in a standard 0.35- ${\mu }\text{m}$ CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm2. A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 ${\mu }\text{W}$ with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator.

The opamp in the integrators of a continuous-time delta-sigma modulator (CTDSM) has stringent noise and linearity requirements, which lead to large power dissipation. In this paper, a negative-R assisted integrator is proposed to mitigate the opamp’s requirements including dc gain, unity gain bandwidth, thermal and 1/ ${f}$ noise, and linearity, thus enabling a drastic power reduction. We present two prototype CTDSMs using the negative-R assisted integrators that employ a single-bit and tri-level feedback digital-to-analog converter (DAC), respectively. The prototype CTDSMs were fabricated in 65-nm CMOS technology. The first CTDSM using a single-bit feedback DAC achieves dynamic range (DR)/signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 93.1/88.5/100.5 dB in a 20-kHz bandwidth while dissipating only 55 $\mu \text{W}$ from a 1.2-V supply. The second CTDSM, with a tri-level feedback DAC, achieves DR/SNDR/SFDR of 98.2/94.1/107 dB in a 24-kHz bandwidth while dissipating only 68 $\mu \text{W}$ from a 1.2-V supply. The figures of merit of the two CTDSMs are 178.7 and 183.6 dB, respectively, which are the best energy efficiency among state-of-the-art works.

We have studied the impact of temperature variation on Dual Metal Gate GaSb-Si NWTFET device performance. Variations in DC parameters namely the transfer characteristics, Threshold Voltage, I on /I off Ratio, Subthreshold Swing has been investigated for temperatures from 250K to 400K. Furthermore, variations in RF performance metrics namely trans-conductance g m , Drain Conductance g d , Parasitics Capacitance C gd C gs , Intrinsic Gain g m /g d , Transconductance Frequency Product TFP, Cutoff Frequency f T , Gain Frequency Product GFP, Gain Bandwidth Product GBP, Transit Time τ for different temperatures have also been studied. Lastly, the variations in Linearity performance metrics namely VIP 2 , VIP 3 , IMD 3 and IIP 3 for different temperatures is studied.

The fifth generation (5G) wireless technology will provide the nation’s future telecommunications network, featuring higher bandwidth and data rates with lower delay and power consumption. This shift facilitates the ultra-level of integration, for systems loaded with embedded sensors that are enabled by this technology. A few challenges remain regarding the standards to proper interfacing, security for cellular based services, and ability of portable devices to be employed in this technology. These challenges include high-speed amplifiers and signal processors. Millimeter wave communications with frequencies above 10 GHz for mobile networks may be required to meet the propagation quality demands of this technology. This paper proposes the Graphene Nano Ribbon Field Effect Transistor (GNRFET) device as a potential candidate that fits well in this technology, featuring high frequency amplifiers and high switching speed in digital circuits with ultra-low power consumption. These advantages may be attributed to the high mobility and mean free path of the device, leading to major ballistic carrier transport. The simulation was conducted at a switching speed in the order of 10GHz and 0.7V supply. The device was also employed for high frequency amplifiers, achieving as much as 5.1 THz gain bandwidth product (70GHz at a gain of 75), with very clean output signals. Near 115 dBs attenuation losses for harmonics was determined within the operating bandwidth. This paper details the device model, circuit design, and power consumption, suitable for the 5-G communication system. The nanoscale size of the device provides the ultra-level of integration, incorporating the embedded and IoT devices supporting this technology.

In this paper, the performance of FinFET has been examined by changing the fin width which affects the device performance. The fin width has been changed by keeping the device width fixed and varying the width of the oxide layer by electrical characterization and simulation. The device width is fixed at 50nm and the oxide layer width is varied from 10nm to 3nm. Here five different parameters such as drain current (ID), transconductance (g m ), cutoff frequency (f T ), gain bandwidth product (GBW), and power (P) are computed to study the effect of oxide layer width of the device. It has been observed from the simulation that at lower oxide layer width ID and g m show maximum value, and at medium value of oxide layer width f T and GBW give better performance. The power consumption of FinFET is lesser when the oxide layer width reduces.

In this work, we demonstrate In0.52Al0.48As top/backside-illuminated avalanche photodiodes (APD) with dual multiplication layers for high-speed and wide dynamic range performances. Our fabricated top-illuminated APDs, with a partially depleted p-type In0.53Ga0.47As absorber layer and thin In0.52Al0.48As dual multiplication (M-) layer (60 and 88 nm), exhibit a wide optical-to-electrical bandwidth (16 GHz) with high responsivity (2.5 A/W) under strong light illumination (around 1 mW). The measured bias dependent 3-dB O-E bandwidth was pinned at 16 GHz without any serious degradation near the saturation current output. To further increase the speed, we downscaled the active diameter and adopted a back-side illuminated structure with flip-chip bonding for batter optical alignment tolerance. A significant improvement in maximum bandwidth was demonstrated (25 versus 18 GHz). On the other hand, we adopted a thick dual M-layer (200 and 300 nm) and 2 μm absorber layer in the APD design to circumvent the problem of serious bandwidth degradation under high gain (&gt, 100) and high-power operation which significantly enhanced the dynamic range. Due to dual M-layer, the carriers could be energized in the first M-layer then propagate to the second M-layer to trigger the avalanche process. In both cases, despite variation in thickness of the absorber and M-layer, the cascade avalanche process leads to values close to the ultra-high gain bandwidth product (GBP) of around 460 GHz with a responsivity of 0.4 and 1 A/W at unit gain for the thin and thick M-layer devices, respectively. We successfully achieved a good sensitivity of around −20.6 dBm optical modulation amplitude (OMA) at a data rate of 25.78 Gb/s, by packaging the fabricated APDs (thin dual M-layer (60 and 88 nm) version) with a 25 Gb/s trans-impedance amplifier in a 100 Gb/s ROSA package. The results show that, the incorporation of a dual multiplication (M) layer structure in the APD opens a new window to obtaining the higher GBP in order to meet the requirements for high-speed transmission without the need of further downscaling the multiplication layer.

Microelectromechanical System (MEMS) Sensor technology has revolutionized the electronics industry with its wide array of applications from wearable electronics to precision instrument for biomedical applications. However, two of the most inherent problems with these sensors are low capacitance-to-voltage conversion of sensors and its high susceptibility to noise. Since MEMS sensors have been developed over the years, and as to meet the surging market demands of interface circuits, the need for upgrading its features has led to the integration of more complex designs This paper presents an integrated approach for MEMS switched capacitor-based interface which is implemented using a Low Noise Operational Transconductance Amplifier (OTA) design and a digital clock control block implemented in 65nm CMOS Process. The OTA design composes of a noise buffer preamplifier cascaded to a conventional folded cascode amplifier topology. The OTA design obtained parameters values with an open loop gain of 65.5 dB, Unity gain bandwidth of 8.48 MHz, PSRR+ of 65.2 dB and PSRR-of 93.3 dB and a CMRR of 115 dB. Input referred Noise is at 18.369 nV/√Hz. MEMS sensors signal are initialized at the input as MEMS sensors are beyond the scope of this study. With a MEMS noise model, the obtained noise cancellation ability of the proposed amplification and noise cancellation network is known to be 88.765%. The overall circuit covers a chip area of $242\ \mathbf{um}\times 705\ \mathbf{um}$

In this paper we unveil of a new structure in which a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is paralleled with a Tunneling Field Effect Transistor (TFET) to increase on-state current. In order to enhance tunneling current injection rate in the device, workfunction engineering in gate and substrate electrodes and doping engineering in channel (source pocket) are utilized. For further on-state current enhancement of device, thermionic injection mechanism is used by incorporating a MOSFET in the structure. In addition, hetero gate dielectric is used to reduce parasitic capacitances. Our analysis show PTM-FET transistor has several excellences in comparison to DW HGD SP TFET in terms of transconductance, Ion/Ioff current ratio, short channel effects like DIBL, Early voltage, maximum transducer power gain, unilateral power gain, gain bandwidth product, unity gain frequency and parasitic capacitances. The mentioned advantages for PTM-FET transistor can be a window of utilizing this device in both low power and high performance integrated circuit applications.

In this paper, the direct bonding InGaAs/Si avalanche photodiode (APD) with certain gain is developed. This structure separates the optical absorption region (InGaAs) from the multiplication region (Si). Avalanche multiplication takes place in the Si layer after the carriers injected from the absorption region. InGaAs and Si wafer are connected together by wafer bonding technology. The interface quality of InGaAs / Si material is good through optimizing the physical and chemical cleaning methods and bonding conditions of InGaAs/InP and Si epitaxial wafers. The InGaAs / Si APD is fabricated by conventional semiconductor process. The gain of InGaAs / Si APD is 43 at 38V. Further optimization of the process can obtain lower dark current and higher gain bandwidth product. This kind of device can be used for long-distance optical fiber communication.

This paper has proposed a new architecture for variable gain amplifier (VGA) built in the 0.1S$\mu$m CMOS technology. In this paper, a new definitive approach is proposed for achieving a large band range of DC gain, acceptable bandwidth (-3dB) with low power consumption and high linearity. This proposed VGA was designed on the Cadence Virtuoso tool for receiver system used in RF, consisting of trans-impedance amplifier and trans-conductor amplifier which are in linear mode. This VGA also attains DC gain range from -35 to 19 dB, and bandwidth is around 25.8 MHz (-3dB). Meanwhile, the proposed VGA, Unity Gain Bandwidth of is nearly 3.32GHz with noise Figure nearly 20dB. Overall circuit consumes total power approximately 2.3mW.

Differential amplifier is an analog component. which is used as an amplifier whenever a circuit contains more than one input. A differential amplifier is a basic primitive component in an operational amplifier. Differential amplifier contains three legs. In which two legs for the input signal to be amplified, the third leg used as output. The differential amplifier can be configured by bipolar technology or with Metal oxide semiconductor technology also. When the input non-inverted leg which acts as a comparator is applied as input, if any signal applied to invert leg of the differential amplifier it will be used as an amplifier. In this proposed article, the operational amplifier with high gain of 72dB is implemented, the Slew rate of 122 V/µs, Gain bandwidth product of 4.60 MHz Dual-stage operational amplifier will enhance the amplification in a better way when the single-stage amplifier is compared In this article, a dual-stage operational amplifier using CMOS 45nm Technology is implemented.

This paper presents a novel high speed operational amplifier using a-IGZO TFTs for a given technology, without changing device structure, processing conditions and materials. In the proposed design, a negative capacitance generator (NCG) is employed, using a-IGZO TFTs, which is connected to the output of a positive feedback operational amplifier. This technique helps to move the output pole of the amplifier to very high frequency by reducing the overall equivalent capacitance (C eq ) at the output node, as the negative capacitance is in parallel with C eq . By using this technique, the unity gain bandwidth (GB) of the opamp is increased from 486 kHz to 1.474 MHz without compromising other performance metrics, such as, gain and stability (phase margin). However power consumption is increased from 0.3mW to 0.6 mW, when the simulations took place with in-house IGZO TFT models. Both NCG and the amplifier were designed with a minimum feature size of 10 μm and a power supply of 10V and 15V, respectively.

The article presents the results of the development and measurements of a specialized integrated circuit of an instrumentation amplifier (IA) with indirect negative current feedback. The schematic and the measurement results of the main characteristics for a silicon-on-insulator metal-oxide-semiconductor instrumentation amplifier are presented. The amplifier is intended for use as a part of a sensor network for monitoring the state of high-temperature objects. The temperature range of the instrumentation amplifier is up to 200 °C. Instrumentation amplifier has 11.8 MHz gain bandwidth product with a 3.3 V supply voltage. The measured gain is 27.50 dB and the error in setting the gain was 0.27 dB, the 3 dB bandwidth is 500 kHz.

In various signal processing applications, the performance of the data acquisition circuits is depended upon the performance of the amplifier. On the other hand, the noise signal may saturate the system. The operational amplifier is found to be the most efficient amplifier for signal processing circuits. In literature, several operational amplifiers were designed using Bipolar junction transistors, Field effect transistors and CMOS devices. But the power consumption has limitations on design with BJT and CMOS devices. To overcome this, new alternative devices are required. The minimum parasitic interconnection elements and low supply voltage will enhance the performance. To enhance these requirements, this paper presents a FinFET-based OP-AMP and OTA design with low power, very high unity gain bandwidth (UGB) and high open-loop gain (DC gain). The FinFET-based circuit is designed using 32 nm technology. The proposed circuit has higher driving capacity and is highly stable.

In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

This paper proposes a novel operational amplifier (OPA) voltage-controlled oscillator (VCO) circuits on the basis of impedance converters. The VCO can operate over a frequency range exceeding unity-gain bandwidth due to the location of the tank circuit, not at the output of the OPA, but at the noninverting input. The paper presents the mathematical modeling of oscillated amplitude and start-up conditions. The simulation results confirm the theoretical achievements. The designed and simulated VCO uses an ultra-low noise wideband OPA LMH6629MF, covers a frequency band between 0.830 GHz and 1.429 GHz, and exhibits a maximum in-band total harmonic distortion (THD) of 1.7%. It has a maximum in-band phase noise of &minus, 139.3 dBc/Hz at 100 kHz offset frequency and has an outstanding value of a standard figure of merit (FoM) of &minus, 198.6 dBc/Hz. The zero-peak amplitude of output voltage is from 3.2 V to 4 V for all generated frequencies at a supply voltage of &plusmn, 5 V. The fabricated prototype-oscillator based on OPA LMH6624 operates at a frequency of 583.1 MHz with a power level of 0 dBm.

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/&mu, m to 0.1 fF/&mu, m. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits.

This work represents a novel low noise amplifier, designed for biomedical front-end applications. The proposed circuit is designed using 180 nm CMOS technology. The simulation results exhibit very good performance showing a gain of 57.9 dB and unity gain bandwidth of 330 KHz. The proposed design shows enhanced phase margin of 84 degree due to its sub-threshold region of operation for the devices. The circuit performs under the supply voltage of 1.8 V and consumes only 400 nW of DC Power. The input-referred noise voltage of the designed circuit is obtained as$0.6\mu V/\sqrt {HZ} $ at 5 KHz, which makes it suitable for biomedical applications. Also, the CMRR of the designed circuit is obtained as 82.6 dB.

A super class AB recycling folded cascode amplifier in 130 nm CMOS is presented. It combines for the first time adaptive biasing of the differential input pair, nonlinear current mirrors with current starving and dynamic biasing of the cascode transistors in the output branch. Measurements using a ±0.5V supply show slew rate and gain bandwidth product improvement factors of 26 and 112 versus the conventional topology for the same bias currents, yielding the highest combined FoM to date. This work has been supported in part by grant TEC2016-80396-C2 (AEI/FEDER).

Here we demonstrate an efficient (0.8 AW-1) plasmonic slot photodetector based on monolithically integrating MoTe2 in silicon photonics. Shrinking the source-drain distance (L) to 10 nm enables high gain-bandwidth-product detectors scaling with L^-2.

Nowadays, low power operational amplifiers (op-amp) are highly demand for most of the applications such as in medical and communication system. In this project, two stage op-amp is designed and operated at 1.8 V supply voltage. The supply voltage is scaled down to reduce the power dissipation of the op-amp. This is because the power will be high when there is a large supply voltage. The design is simulated and analysed using Mentor Graphic Pyxis software. This two stage op-amp is designed using the Silterra 0.13 µm process technology. The operational amplifier provides a Direct Current (DC) gain of 21.18 dB and a unity gain bandwidth of 6.31 MHz. The gain margin obtained from the op-amp is 14.07 dB and the phase margin of the op-amp is 94.26 ° for 3 pF compensation capacitor and 10 pF load capacitor. The result shows that circuit able to work at 1.8 V power supply voltage and the total power dissipation for the op-amp is 5.35 mW.

This brief presents the principle and the first experimental results of the multiple-input bulk-driven (MIBD) MOS transistor (MOST) suitable for extremely low-voltage low-power integrated circuits. The MIBD MOST offers significant reduction in circuit complexity, power consumption and extension of the input common-mode range (ICMR). To confirm the benefits of the MIBD MOST, a differential difference amplifier (DDA) with very simple CMOS topology has been designed and fabricated in a standard n-well 0.18 µm CMOS process from TSMC with total chip area 226 µm × 78 µm. The DDA is supplied with 0.5 V and consumed only 1.23 µW, while the ICMR is rail-to-rail. The measured open-loop dc gain is 62 dB, the gain bandwidth product is 56.4 kHz, and the total harmonic distortion is 0.2% @ 1 kHz for 400 mV peak-to-peak input sine wave.