16 results on '"Nouredine Rassoul"'
Search Results
2. Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling
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S. Paolillo, Guillaume Boccardi, N. Jourdan, Manoj Jaysankar, Zheng Tao, Sylvain Baudot, Geert Mannaert, Juergen Boemmels, T. Hopf, E. Capogreco, Shouhua Wang, Efrain Altamirano, E. Dupuy, Olalla Varela Pedreira, B. Briggs, Thomas Chiarella, Joris Cousserier, Sofie Mertens, Romain Ritzenthaler, Frank Holsteyns, C. Lorant, Goutham Arutchelvan, Ingrid Demonie, Steven Demuynck, K. Kenis, Xiuju Zhou, Anshul Gupta, F. Sebai, D. Radisic, Zsolt Tokei, Erik Rosseel, A. Sepulveda, Naoto Horiguchi, Christel Drijbooms, Antony Premkumar Peter, Haroen Debruyn, Nouredine Rassoul, Bilal Chehab, P. Morin, Boon Teik Chan, Christopher J. Wilson, Katia Devriendt, Noemie Bontemps, Frederic Lazzarino, Paola Favia, Lieve Teugels, D. Yakimets, F. Schleicher, Houman Zahedmanesh, Jerome Mitard, Min-Soo Kim, An De Keersgieter, Sujith Subramanian, Kevin Vandersmissen, Hans Mertens, Eugenio Dentoni Litta, and Yong Kong Siew
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010302 applied physics ,Materials science ,business.industry ,chemistry.chemical_element ,Dielectric ,Tungsten ,01 natural sciences ,Electromigration ,Electronic, Optical and Magnetic Materials ,law.invention ,chemistry ,CMOS ,law ,0103 physical sciences ,Optoelectronics ,Electrical and Electronic Engineering ,Tin ,business ,Spark plug ,Critical dimension ,Scaling - Abstract
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.
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- 2020
3. (Invited) Sub-40mV Sigma VTH Igzo nFETs in 300mm Fab
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Zsolt Tokei, Harold Dekkers, Michiel van Setten, Nouredine Rassoul, Attilio Belmonte, Soeren Steudel, Luka Kljucar, Manoj Nag, Jose Ignacio del Agua Borniquel, Adrian Chasin, G. L. Donadio, Gouri Sankar Kar, Jerome Mitard, Geoffrey Pourtois, Romain Delhougne, Christopher J. Wilson, and Ludovic Goux
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Materials science ,business.industry ,Optoelectronics ,Sigma ,business - Abstract
In this work, IGZO device integration is reported leveraging our 300mm-fab facilities. Our objective is mainly to gain insights into the process and material elements which drive the control of the performance parameters of IGZO nFETs. To control the final doping of the IGZO channel, it is well reported in literature that a final oxygen anneal can be applied to passivate the oxygen vacancies which are formed during the device fabrication. This technique is also used in our 300mm flow. As it might be expected, in front gate IGZO nFETs, the passivation efficiency is limited by the presence of the top metal gate stack. Therefore, it seems important to limit the formation of the oxygen vacancies during the deposition of the gate dielectrics. Three oxides were studied: SiO2, Al2O3 and HfO2 on top of the IGZO channel. After oxygen annealing, only PECVD-SiO2 shows a large recovery while for Al2O3 and HfO2, it remains low. This result challenges the implementation of conventional water-based high-K materials in gate first IGZO integration. Contrary to the use of undoped IGZO in the channel for IOFF control, contacts can rely on maximizing the oxygen vacancies to increase the dopant concentration in the S/D regions. When not done locally, it could be an extra source of variability. This doping is made through oxygen scavenging from IGZO by a thin metal contact barrier. Low specific contact resistivity down to 1x107 Ohm.cm2 is demonstrated when Ti is thinner than 5nm. With thicker barrier, the formation of TiO2 and specific alloys is taking place at the IGZO/Contact barrier interface. This is both confirmed by ab initio simulations and by advanced physical characterization techniques. Regarding the channel, X-ray diffraction techniques are extensively here since this is a nondestructive in-fab technique that provides detailed information about the crystallographic structure of the IGZO material. We show a typical spectrum where clear peaks/humps are seen and attributed to: 1. amorphous IGZO, 2. CAAC-IGZO and 3. a previously not reported, to the best of our knowledge, phase called here s-IGZO. The s-phase is only formed under certain conditions of power, temperature and oxygen flow during material deposition. Thick IGZO (>12nm) back-gated nFETs with active layers submitted to final O2 anneal are used to study the different phases of IGZO and their electrical impact on device parameters. In this configuration, the carrier transport preferentially occurs in the bottom half of the IGZO channel while the top half (SiO2/IGZO interface) mostly drives the electrostatic control of BG transistors. The amorphous IGZO has much reduced spread in VTH-ON and higher ID,LIN (~mobility) than that of CAAC-IGZO. Reliability tests have also been carried out to compare the two phases and the results show the existence of two competing PBTI degradation mechanisms for CAAC-IGZO. It is important to report the degradation over time and different VG stress because a cut line at a specific value could have shown no BTI degradation of CAAC-IGZO and then attributing an unfair benefit of this phase over the a-IGZO phase. Combining these findings to some other results where the sheet resistance of IGZO under hydrogen exposure depends on the phases, we can reasonably conclude that CAAC owns different doping levels in comparison to a-IGZO. Based on the previous learning about n-type dopant location in IGZO, we show that the performance of transistors keeps increasing when the channel length is reduced and scales with the channel width. A measure of the VTH-ON variation has been performed at the 300mm wafer scale from long to ~120nm LCH and down to 200nm WCH dimensions. The figure in attachement shows the Id-Vg curves of >100 Back Gated IGZO-nFETs with no failed devices detected. The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV. In conclusion, we have demonstrated in this study scaled IGZO nFETs with excellent VTH_ON control using an industry compatible 300mm process flow. This has been achieved thanks to a careful mapping of n-type doping in the three dimensions of the IGZO channel. While semi-crystalline IGZO seems to be more robust against hydrogen than that of amorphous-IGZO, a new IGZO phase is found to help boost ION at short channel. The demonstration of back-gate IGZO nFETs with low variability and relatively high drive will benefit to the top-gate architecture development. This will provide new opportunities for the IGZO-based devices like an “on-the-fly” VTH setting for the performance control of advanced applications. Figure 1
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- 2020
4. 3-D Sequential Stacked Planar Devices Featuring Low-Temperature Replacement Metal Gate Junctionless Top Devices With Improved Reliability
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Amey Mahadev Walke, Anne Vandooren, F. M. Bufler, Nancy Heylen, J. Franco, Bich-Yen Nguyen, Gweltaz Gaudin, Lieve Teugels, Veeresh Deshpande, Boon Teik Chan, Dan Mocuta, Walter Schwarzenbach, T. Zheng, W. Li, Z. Wu, Erik Rosseel, Niamh Waldron, Nadine Collaert, E. Vecchio, Nouredine Rassoul, Romain Ritzenthaler, V. De Heyn, Bertrand Parvais, W. Vanherle, Liesbeth Witters, Iuliana Radu, G. Verbinnen, Lan Peng, Fumihiro Inoue, Andriy Hikavyy, Geert Hellings, Katia Devriendt, G. Jamieson, and G. Besnard
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010302 applied physics ,Materials science ,Wafer bonding ,business.industry ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,PMOS logic ,CMOS ,Logic gate ,0103 physical sciences ,Optoelectronics ,Wafer ,Electrical and Electronic Engineering ,0210 nano-technology ,Metal gate ,business ,NMOS logic ,High-κ dielectric - Abstract
3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.
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- 2018
5. Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
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Lieve Teugels, Attilio Belmonte, H. Oh, Ludovic Goux, Ming Mao, Harinarayanan Puliyalil, Zsolt Tokei, Luka Kljucar, G. L. Donadio, Jerome Mitard, Diana Tsvetanova, Nouredine Rassoul, Harold Dekkers, K. Banerjee, Gouri Sankar Kar, Adrian Chasin, Romain Delhougne, M. J. van Setten, M. Pak, Subhali Subhechha, and Laurent Souriau
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010302 applied physics ,Reproducibility ,Materials science ,business.industry ,Transistor ,Dielectric ,01 natural sciences ,Power (physics) ,law.invention ,Capacitor ,law ,Logic gate ,0103 physical sciences ,Optoelectronics ,Wafer ,business ,Dram - Abstract
We report for the first time a fully 300-mm stacking-compatible capacitor-less DRAM cell with >400s retention time by integrating two IGZO-TFTs in a 2T0C configuration. We optimize the single IGZO-TFT performances by engineering the materials surrounding the IGZO layer and the transistor layout parameters. We thus introduce a novel IGZO-TFT device and demonstrate a scaled transistor (W = 70 nm, L = 45 nm) with optimal V th reproducibility on 300-mm wafers. By integrating the IGZO-TFTs in a 2T0C configuration, we systematically assess reproducible long retention time for different transistor dimensions, thanks to the extremely low extracted IGZO-TFT off-current (~3x10-19A/µm).
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- 2020
6. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
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N. Jourdan, Katia Devriendt, E. Dupuy, Hans Mertens, S. Paolillo, Guillaume Boccardi, F. Schleicher, E. Sanchez, Romain Ritzenthaler, Frank Holsteyns, Z. Tao, Sylvain Baudot, Sofie Mertens, Haroen Debruyn, Kevin Vandersmissen, Thomas Chiarella, P. Morin, Antony Premkumar Peter, Anshul Gupta, Erik Rosseel, Min-Soo Kim, Nouredine Rassoul, Boon Teik Chan, Christopher J. Wilson, D. Radisic, Lieve Teugels, A. De Keersgieter, D. Yakimets, I. Demonie, N. Bontemps, C. Drijbooms, Sujith Subramanian, Bilal Chehab, Paola Favia, C. Lorant, Farid Sebaai, Steven Demuynck, Frederic Lazzarino, E. Dentoni Litta, G. Mannaert, Houman Zahedmanesh, Yong Kong Siew, J. Cousserier, T. Hopf, B. Briggs, Manoj Jaysankar, Jerome Mitard, K. Kenis, A. Sepúlveda, S. Wang, Naoto Horiguchi, Goutham Arutchelvan, E. Capogreco, O. Varela Pedreira, D. Zhou, Jürgen Bömmels, and Zsolt Tokei
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010302 applied physics ,Materials science ,business.industry ,chemistry.chemical_element ,02 engineering and technology ,Tungsten ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electromigration ,Cmos scaling ,CMOS ,chemistry ,Booster (electric power) ,Logic gate ,0103 physical sciences ,Optoelectronics ,0210 nano-technology ,business ,Low resistance ,Scaling - Abstract
Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.
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- 2020
7. RIE dynamics for extreme wafer thinning applications
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Andy Miller, Nina Tutunjyan, Janet Hopkins, Nouredine Rassoul, Joeri De Vos, Fumihiro Inoue, Oliver Ansel, Eric Beyne, Daniele Piumi, Huma Ashraf, Gerald Beyer, Dave Thomas, Jash Patel, Stefano Sardo, Anne Jourdain, and Edward Walsby
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0209 industrial biotechnology ,Materials science ,business.industry ,Flatness (systems theory) ,02 engineering and technology ,Edge (geometry) ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,Atomic and Molecular Physics, and Optics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,Grinding ,020901 industrial engineering & automation ,Etching (microfabrication) ,visual_art ,visual_art.visual_art_medium ,Optoelectronics ,Wafer ,Ceramic ,Electrical and Electronic Engineering ,Reactive-ion etching ,0210 nano-technology ,business ,Reflectometry - Abstract
Over the past few years, extreme wafer thinning has acquired more interest due to its importance in 3D stacked system architecture. This technique facilitates multi-wafer stacking for via last advanced packaging. From a cost and wafer integrity point of view, it has been demonstrated that the best process flow combines grinding with fast Si removal using Reactive Ion Etching (RIE). For this integration scheme, final thickness, and global flatness are key for subsequent steps. The wafer thinning performances are driven by several steps and can lead to lot, wafer to wafer and within wafer variations especially at the extreme edge. The first part of this study is to demonstrate stable wafer thinning with good control of the remaining Si (up to 5 μm) during the RIE process. This uses an innovative in-situ endpoint system (Near Infra-Red reflectometry) where the Si thickness is monitored whilst etching. The second part will focus on adjustment of the etch profile to compensate for incoming non-uniformity. This has been investigated from three different perspectives: Hardware modification where the ceramic ring surrounding the wafer is modified, process modification to change the etch front through changing the gas flow and plasma shape and changing the edge trim to introduce additional loading at the edge.
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- 2018
8. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
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B. Parvais, G. Besnard, T. Zheng, Anne Vandooren, W. Li, Erik Rosseel, Julien Ryckaert, Nadine Collaert, Boon Teik Chan, Dan Mocuta, Nancy Heylen, E. Vecchio, Lan Peng, Juergen Boemmels, Liesbeth Witters, Steven Demuynck, Iuliana Radu, A. Khaled, G. Jamieson, Niamh Waldron, Philippe Matagne, Nouredine Rassoul, V. De Heyn, Amey Mahadev Walke, Gweltaz Gaudin, Walter Schwarzenbach, D. Radisic, Z. Wu, Katia Devriendt, Haroen Debruyn, Fumihiro Inoue, Bich-Yen Nguyen, Andriy Hikavyy, W. Vanherle, J. Franco, Lieve Teugels, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Faculty of Engineering, Faculty of Medicine and Pharmacy, Human Physiology and Special Physiology of Physical Education, and Vriendenkring VUB
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010302 applied physics ,Materials science ,business.industry ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Line (electrical engineering) ,Threshold voltage ,Reduction (complexity) ,Reliability (semiconductor) ,Planar ,0103 physical sciences ,Thermal ,Electromagnetic shielding ,Optoelectronics ,Electrical and Electronic Engineering ,0210 nano-technology ,business ,NMOS logic - Abstract
3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.
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- 2019
9. Patterning challenges for beyond 3nm logic devices: example of an interconnected magnetic tunnel junction
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N. A. Thiam, Johan Swerts, Laurent Souriau, Darko Trivkovic, Christopher J. Wilson, Monique Ercken, Eline Raymenants, K. Babaei Gavan, Nouredine Rassoul, J. Jussot, Iuliana Radu, Danny Wan, and Sebastien Couet
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Fabrication ,Materials science ,business.industry ,Transistor ,Copper interconnect ,law.invention ,Tunnel magnetoresistance ,CMOS ,Etching (microfabrication) ,law ,Optoelectronics ,business ,Lithography ,Electron-beam lithography - Abstract
In this paper, patterning challenges that led to the fabrication of a first Spin Torque Majority Gate (STMG) device are explored. We have highlighted key process module developments from the Magnetic Tunnel Junctions (MTJs) pillar patterning to dual damascene scheme wiring module. Spin devices such as STMG have already been proposed as a replacement for conventional CMOS transistors. The main challenge to their experimental demonstration remains the successful fabrication of connected MTJs through a ferromagnetic layer, allowing spin transport across the gate. We propose a new etching approach utilizing Ion Beam Etching (IBE), to be able to pattern the MTJs with high precision and with less damage to the magnetic layers. Furthermore, we have introduced Electron-beam lithography to further scale down the device geometries. This development paves the way towards a fully integrated STMG device for Spin Logic applications.
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- 2019
10. Staggered pillar patterning using 0.33NA EUV lithography
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Chan-Ha Park, Jeroen Van de Kerkhove, Nouredine Rassoul, Anne-Laure Charley, Pieter Vanelderen, Frederic Lazzarino, Lieve Van Look, Amir-Hossein Tamaddon, Romuald Blanc, Frieda Van Roey, Geert Vandenberghe, Danilo De Simone, Kurt G. Ronse, Chang-Moon Lim, Junghyung Lee, Sarohan Park, Kilyoung Lee, Nadia Vandenbroeck, Roberto Fallica, and Gian Lorusso
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Materials science ,Optics ,Resist ,business.industry ,Extreme ultraviolet lithography ,Reticle ,Wafer ,Process window ,business ,Lithography ,Critical dimension ,Aerial image - Abstract
Extreme ultraviolet (EUV) materials are deemed as critical to enable and extend the EUV lithography technology. Currently both chemically amplified resist (CAR) and metal-oxide resist (MOR) platforms are candidates to print tight features on wafer, however patterning requirements, process tonality (positive or negative), illumination settings and reticle tonality (dark or bright) play a fundamental role on the material performance and in consequence on the material choice. In this work we focus on the patterning of staggered pillars using a single EUV exposure, and this by looking at the lithographic and etching performance of CAR and MOR platforms, using metrics as process window, local critical dimension uniformity (LCDU), pillar edge roughness (PER), pillar placement error (PPE) and (stochastic) nano-failures. As a bright field reticle shows a lower aerial image contrast to print pillars compared to the aerial image of contact holes using a dark field reticle, we also investigate alternative patterning solutions such as the tone reversal process (TRP) to pattern pillars from contact holes.
- Published
- 2019
11. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
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Liesbeth Witters, Z. Wu, Anne Vandooren, G. Mannaert, Nadine Collaert, E. Vecchio, Lars-Ake Ragnarsson, Romain Ritzenthaler, Niamh Waldron, V. De Heyn, Jerome Mitard, Nouredine Rassoul, Boon Teik Chan, Dan Mocuta, Bertrand Parvais, Veeresh Deshpande, Fumihiro Inoue, Lan Peng, Andriy Hikavyy, G. Jamieson, J. Franco, W. Vanherle, Lieve Teugels, T. Zheng, W. Li, Amey Mahadev Walke, Katia Devriendt, Erik Rosseel, Julien Ryckaert, Nancy Heylen, Steven Demuynck, Geert Hellings, Juergen Boemmels, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Faculty of Engineering, Faculty of Medicine and Pharmacy, Human Physiology and Special Physiology of Physical Education, and Vriendenkring VUB
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010302 applied physics ,Materials science ,Silicon ,business.industry ,Stacking ,chemistry.chemical_element ,02 engineering and technology ,Dielectric ,Condensed Matter Physics ,021001 nanoscience & nanotechnology ,01 natural sciences ,Electronic, Optical and Magnetic Materials ,Threshold voltage ,Dipole ,chemistry ,0103 physical sciences ,Materials Chemistry ,Optoelectronics ,Wafer ,Electrical and Electronic Engineering ,0210 nano-technology ,Tin ,business ,Immersion lithography - Abstract
3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.
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- 2018
12. 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability
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Iuliana Radu, Anne Vandooren, T. Zheng, W. Li, Fumihiro Inoue, Niamh Waldron, J. Franco, Andriy Hikavyy, Liesbeth Witters, Nouredine Rassoul, Lieve Teugels, W. Vanherle, E. Vecchio, Nadine Collaert, G. Verbinnen, Bertrand Parvais, V. De Heyn, G. Besnard, F. M. Bufler, B.-Y. Nguyen, Lan Peng, Boon Teik Chan, Dan Mocuta, W. Schwarzenbach, Katia Devriendt, Romain Ritzenthaler, G. Jamieson, Erik Rosseel, Geert Hellings, G. Gaudin, V. Desphande, Nancy Heylen, Amey Mahadev Walke, Z. Wu, Electronics and Informatics, Faculty of Economic and Social Sciences and Solvay Business School, Faculty of Engineering, Faculty of Medicine and Pharmacy, Human Physiology and Special Physiology of Physical Education, and Vriendenkring VUB
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010302 applied physics ,Materials science ,business.industry ,Wafer bonding ,02 engineering and technology ,01 natural sciences ,020202 computer hardware & architecture ,PMOS logic ,CMOS ,Logic gate ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Optoelectronics ,Wafer ,Electrical and Electronic Engineering ,business ,Metal gate ,NMOS logic ,High-κ dielectric - Abstract
3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.
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- 2018
13. Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling
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Nancy Heylen, G. Verbinnen, Amey Mahadev Walke, Anne Vandooren, T. Zheng, Erik Rosseel, W. Li, Fumihiro Inoue, E. Vecchio, V. De Heyn, Andriy Hikavyy, Z. Wu, Bertrand Parvais, Dan Mocuta, Lan Peng, Liesbeth Witters, J. Franco, Lieve Teugels, Arindam Mallik, Niamh Waldron, Nouredine Rassoul, G. Jamieson, Katia Devriendt, Veeresh Deshpande, Nadine Collaert, Faculty of Economic and Social Sciences and Solvay Business School, Electronics and Informatics, Work and Organisational Psychology, Faculty of Engineering, Faculty of Medicine and Pharmacy, and Human Physiology and Special Physiology of Physical Education
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Computer science ,Stacking ,wafer bonding ,Silicon on insulator ,02 engineering and technology ,law.invention ,law ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Electrical and Electronic Engineering ,Safety, Risk, Reliability and Quality ,Scaling ,Electronic circuit ,business.industry ,020208 electrical & electronic engineering ,Transistor ,020206 networking & telecommunications ,silicon-on-insulator ,Semiconductor ,CMOS ,Hardware and Architecture ,Logic gate ,Systems engineering ,thermal budget ,junctionless ,business ,3D sequential - Abstract
In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.
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- 2018
14. Subtractive Etch of Ruthenium for Sub-5nm Interconnect
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Victor Blanco, Gayle Murdoch, S. Paolillo, Danny Wan, Christoph Adelmann, Bogumila Kutrzeba Kotowska, Nouredine Rassoul, Frederic Lazzarino, Christopher J. Wilson, Jürgen Bömmels, Zsolt Tokei, and M. Ercken
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010302 applied physics ,Interconnection ,Materials science ,Annealing (metallurgy) ,business.industry ,Extreme ultraviolet lithography ,Copper interconnect ,chemistry.chemical_element ,02 engineering and technology ,021001 nanoscience & nanotechnology ,01 natural sciences ,Copper ,Ruthenium ,chemistry ,Electrical resistivity and conductivity ,0103 physical sciences ,Optoelectronics ,0210 nano-technology ,business ,Critical dimension - Abstract
Ruthenium has been recently considered as a promising candidate to replace copper as the BEOL interconnect material for sub-5nm technology nodes. In this work, single level Ru interconnects were fabricated in imec's 300-mm pilot line using EUV lithography and the subtractive etch of Ru films. Lines with critical dimension smaller than 10.5 nm were formed and electrically tested to assess the line resistance of patterned Ru. Using the TCR method, structures with resistivity of 15 μΩ.cm and cross-sectional area of 200 nm2 were obtained and benchmarked against analogous Ru and Cu damascene processes. Ru lines with aspect ratio up to 3.8 were fabricated and measured having line resistance below 500 Ω/μ $m$ at 12 nm CD. Ru is expected to outperform damascene Cu at this scale, supporting the potential insertion of Ru metal patterning for advanced technology nodes.
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- 2018
15. Fabrication of magnetic tunnel junctions connected through a continuous free layer to enable spin logic devices
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Adrien Vaysset, Eline Raymenants, Khashayar Babaei Gavan, Iuliana Radu, Kristof Paredis, Danny Wan, Cedric Huyghebaert, Dan Mocuta, A. Thiam, Christopher J. Wilson, Johan Swerts, Nouredine Rassoul, J. Jussot, Lennaert Wouters, Safak Sayan, Mauricio Manfrini, Sebastien Couet, M. Ercken, and Laurent Souriau
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Materials science ,Fabrication ,Physics and Astronomy (miscellaneous) ,General Physics and Astronomy ,FOS: Physical sciences ,02 engineering and technology ,Applied Physics (physics.app-ph) ,01 natural sciences ,0103 physical sciences ,Torque ,Spin-½ ,010302 applied physics ,Interconnection ,Condensed Matter - Materials Science ,business.industry ,General Engineering ,Spin-transfer torque ,Materials Science (cond-mat.mtrl-sci) ,Physics - Applied Physics ,021001 nanoscience & nanotechnology ,Domain wall (magnetism) ,Ferromagnetism ,Optoelectronics ,0210 nano-technology ,business ,Realization (systems) - Abstract
Magnetic tunnel junctions (MTJs) interconnected via a continuous ferromagnetic free layer were fabricated for Spin Torque Majority Gate (STMG) logic. The MTJs are biased independently and show magnetoelectric response under spin transfer torque. The electrical control of these devices paves the way to future spin logic devices based on domain wall (DW) motion. In particular, it is a significant step toward the realization of a majority gate, even though further downscaling may be required. To our knowledge, this is the first fabrication of a cross-shaped free layer shared by several perpendicular MTJs. The fabrication process can be generalized to any geometry and any number of MTJs. Thus, this framework can be applied to other spin logic concepts based on magnetic interconnect. Moreover, it allows exploration of spin dynamics for logic applications, Comment: submitted to Japanese Journal of Applied Physics
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- 2017
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16. Direct metal etch of ruthenium for advanced interconnect
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Nouredine Rassoul, Frederic Lazzarino, Daniele Piumi, Danny Wan, Sara Paolillo, and Zsolt Tőkei
- Subjects
010302 applied physics ,Plasma etching ,Materials science ,business.industry ,Process Chemistry and Technology ,Biasing ,02 engineering and technology ,Chemical vapor deposition ,Sputter deposition ,021001 nanoscience & nanotechnology ,01 natural sciences ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,Atomic layer deposition ,Etching (microfabrication) ,0103 physical sciences ,Materials Chemistry ,Optoelectronics ,Deposition (phase transition) ,Wafer ,Electrical and Electronic Engineering ,0210 nano-technology ,business ,Instrumentation - Abstract
In this work, Ru wires patterning by direct etch are evaluated for a potential 5 nm technology node. The characteristics of Ru etching by varying the bias voltage, total flow rate and Cl2/(O2+Cl2) gas flow ratio are studied in an inductively couple plasma etching chamber. Ru sidewalls profile with a tapering angle of 90° and Ru to SiO2 hard mask etch selectivity of 6 are achieved. The authors show the feasibility of patterning lines with an aspect ratio up to 3.5 and lines with a critical dimension down to 10.5 nm (with a 3σ line width roughness of 4.2 nm), which paves the way to further scaling of this approach. Finally, the authors present a study on Ru line roughness after patterning on 300 mm wafers. Here, they compare line roughness results of wafers where Ru is deposited with different deposition techniques, such as atomic layer deposition and plasma vapor deposition, and it is annealed after deposition at various temperatures.In this work, Ru wires patterning by direct etch are evaluated for a potential 5 nm technology node. The characteristics of Ru etching by varying the bias voltage, total flow rate and Cl2/(O2+Cl2) gas flow ratio are studied in an inductively couple plasma etching chamber. Ru sidewalls profile with a tapering angle of 90° and Ru to SiO2 hard mask etch selectivity of 6 are achieved. The authors show the feasibility of patterning lines with an aspect ratio up to 3.5 and lines with a critical dimension down to 10.5 nm (with a 3σ line width roughness of 4.2 nm), which paves the way to further scaling of this approach. Finally, the authors present a study on Ru line roughness after patterning on 300 mm wafers. Here, they compare line roughness results of wafers where Ru is deposited with different deposition techniques, such as atomic layer deposition and plasma vapor deposition, and it is annealed after deposition at various temperatures.
- Published
- 2018
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