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An advanced active load-pull pulse profiling (ALPPP) system is presented to identify and track, for the first time, the optimum impedances along different sections of an RF pulse. Optimum impedance variations of a 10W GaN device within the RF pulse, and the resulting performance variations are quantified over an output power range of 25 dB showing a significant variation at power back-off. Furthermore, the nature of optimum load variations is probed through the addition of a pulsed IV capability. Pre-bias is utilized to investigate the impact of traps on device behavior over a range of temperature and drive power levels. It is demonstrated that pre-filling the traps provides for an almost constant load optimum across the RF pulse while maintaining device performance. Moreover, the identified optimum pre-bias condition, shows improved device linearity over the duration of the RF pulse, hence, suggesting a new method for compensating impedance mismatches and improving device linearity within an RF pulse.

Intrinsic limits to temperature-dependent substrate loss for GaN-on-Si technology, due to the change in resistivity of the substrate with temperature, are evaluated using an experimentally validated device simulation framework. Effect of room temperature substrate resistivity on temperature-dependent CPW line loss at various operating frequency bands are then presented. CPW lines for GaN-on-high resistivity Si are shown to have a pronounced temperature-dependence for temperatures above 150{\deg}C and have lower substrate losses for frequencies above the X-band. On the other hand, GaN-on-low resistivity Si is shown to be more temperature-insensitive and have lower substrate losses than even HR-Si for lower operating frequencies. The effect of various CPW geometries on substrate loss is also presented to generalize the discussion. These results are expected to act as a benchmark for temperature dependent substrate loss in GaN-on-Si RF technology., Comment: 7 pages (double-column), 10 figures

This paper evaluates the applicability of pulsed I – V measurements as a tool for accurately extracting nonlinear gallium nitride (GaN)-based heterojunction field-effect transistor (HFET) models. Two wafers with the identical layer structure but different growth conditions have been investigated. A series of I – V measurements was performed under dc and pulsed conditions demonstrating a dramatic difference in the kink effect and current collapse (knee walkout) suggesting different trapping behaviors. However, when radio frequency (RF) I – V waveform measurements, utilizing active harmonic load–pull, were used to study the impact of these traps on the RF performance, both wafers gave good overall RF performance with no significant difference observed. This absence of correlation between pulsed I – V measurement results and RF performance raises a question about the applicability of pulsed I – V measurements alone as a tool for extracting nonlinear device models in the case of GaN HFETs.

We demonstrate that the highly-resistive Si substrate in GaN-on-Si RF HEMTs does not act as an insulator, but instead behaves as a conductive ground plane for static operation and can cause significant back-gate induced current collapse. Substrate ramp characterization of the buffer shows good agreement with device simulations and indicates that the current collapse is caused by charge-redistribution within the GaN layer. Potential solutions which alter charge storage and leakage in the epitaxy to counter this effect are then presented.

Envelope tracking power amplifiers (ET PAs) are one of the main contenders for future communication systems. Their operation over a wide range of supply voltages ($V_{\text{D}})$ leads to an extended set of requirements, this paper investigates a number of technologies, including Si LDMOS, GaAs pHEMT and GaN HEMT and how they behave in broadband ET PAs. The increased impact of the feedback capacitance $C_{\text{GD}}$ on broadband PA design in HEMT devices caused by a reduced $V_{\text{D}}$ is described for the first time. Analysis of the $V_{\text{D}}$ dependent characteristics show that GaN HEMTs can exhibit the most promising behaviour for broadband ET PAs due to their favourable output voltage dependent gain variationand their low capacitance to power ratio, so long as field plate designs are used to guarantee a favourable knee walkout.

This paper discusses, for the first time, the continuity\ud of optimum load for power and efficiency in saturated GaN\ud devices. Continuous modes are defined originally on the zerograzing\ud voltage assumption. In this paper we show that a\ud continuous behaviour can also be observed in saturated devices\ud without imposing any limitation on clipping. Simulations using a\ud simplified knee-model for the device and source-load pull experimental\ud characterization are critically analysed and compared to\ud describe the discovered continuum.

It has been established that the terminal radio frequency (RF) current and voltage (IV) waveforms are the unifying theoretical link between transistor technologies, circuit design, and system performance, and therefore, greatly influence the radio frequency power amplifier’s (RFPAs) performance [1]. Thus, it has become necessary to carry out detailed analysis of the time-varying RF voltage V(t) and current I(t) waveforms present on the device terminals for optimizing the output power and dc to RF power conversion efficiency of RFPAs. Alternatively, it can also be said that it has become a standard practice to identify the mode of operations of RFPAs by analyzing the V(t) and I(t) waveforms measured or simulated at the intrinsic terminals of the transistor. For example, Class A and Class F power amplifiers are represented by their respective current and voltage waveforms, as depicted in Fig. 1. It is apparent that in Class A, both the current and voltage waveforms are sinusoidal about the bias point, whereas in Class F, the current waveform is a half-wave rectified sinusoid, and the voltage waveform is a square wave [2], [3]. To experimentally support these established theoretical postulations with regard to current and voltage waveforms, there is a need for Waveform Engineering systems. In principle, waveform engineering is the ability to modify, in a quantified manner, the time-varying current and voltage waveforms present at the terminals of the transistor devices by changing the fundamental and harmonic impedances seen by the intrinsic transistor‘s access points. Effectively, the waveform engineering systems consist of two aspects, namely a waveform measurement component [1], [4], [5] and impedance tuning elements called the load-pull systems [6]–[8].

A load independent X-parameters-based heterojunction bipolar transistor (HBT) model has been used for the first time in the design and behaviour prediction of injection-locked oscillator circuits. This model has been extracted from load-pull measurements with a large-signal network analyser and, in order to obtain a high oscillator RF power, targeting a load impedance close to the optimum one for HBT maximum output power. A methodology is given to obtain robust injection-locked oscillator circuits with a high-synchronisation bandwidth. Several injection-locked oscillator prototypes have been designed and fabricated, and their measurements compared with the simulations obtained using the X-parameters model. Satisfactory results were obtained when the prototypes were operated as free-running and synchronised oscillators. Ministerio de Ciencia e Innovación | Ref. TEC2011-29264-C03-03 Xunta de Galicia | Ref. 2012/260

Look-up table behavioral models (i.e. X-parameters, Cardiff model), input drive ‘|A 11 |’ referenced, extracted directly from measurement data, provide an accurate non-linear CAD modeling solution. Typically, formulated, like s-parameters, in the travelling wave (A-B) domain, since these waves can be directly measured and controlled in the high frequency domain. However, if formulated in the admittance (I-V) domain they would provide a more robust MMIC design modelling solution supporting the capability of width and frequency scaling. Presently, no technique has been presented that allows for the extraction of admittance behavioral models directly from load-pull measurements. Previous solutions have all involved complex indirect procedures based on using an extracted (A-B) domain behavioral model and CAD simulations using voltage sources. In this paper, a new extraction approach is presented which, by including the influence of variable ‘Vii’, allows for direct extraction of admittance behavioral models. This approach has been validated on GaN devices. Ministerio de Economía y Competitividad | Ref. TEC2014-60283-C3-3-R

Electroluminescence microscopy and spectroscopy are used to compare the average hot-electron concentration and temperature under radio frequency (RF) operation class A, class B, and class F modes. From the results obtained, class A results, on average, in the highest hot-electron concentration, while class F is the mode with the lowest concentration due to its 'L'-shaped load line. The electron temperature extracted from the electroluminescence spectra is reduced with increasing RF power, reflecting the dominance of electroluminescence from the portion of the load line in the semi-on region. The electroluminescence method is not able to give substantial information on the portion of the load line with high field and low current density which will be responsible for the potentially damaging hottest electrons present in the channel.

info:eu-repo/grantAgreement/MINECO//TEC2014-60283-C3-3-R/ES/NUEVOS MODELOS NO LINEALES COMPORTAMENTALES DE TRANSISTORES Y TECNOLOGIAS DE DISEÑO PARA AMPLIFICADORES DE POTENCIA DE BANDA DUAL PARA DRONES MULTICOPTERO LIGEROS To meet state-of-the-art specs in nonlinear circuit design for high frequency transceivers, we need computational efficient and reliable active device nonlinear models. Frequencydomain behavioral formulations, like X-parameters, have proven successful in this context. In this paper these formulations are exploited, through simplifications and transformations to the admittance/impedance domains, to algebraically guide the complex nonlinear design flow, in particular, in oscillator design. In addition, analytically the transistor behavioral model bandwidth can be extended, through the enhanced frequency scalability provided by the admittance domain. Simulations and measurements, HEMT and HBT devices will be used to validate the described approaches. Ministerio de Economía y Competitividad | Ref. TEC2014-60283-C3-3-R

A novel graphical power amplifier (PA) design tool, the “clipping contour,” is introduced and described. Using the now well-publicized continuous Class-B/J voltage waveform formulation as a starting point, a process is derived that allows contours to be constructed on a Smith chart that define the “zero-grazing” fundamental and harmonic impedance conditions. Theoretical equations are defined and solved whereby the contours can be drawn in real time in a computer-added design environment. A key and novel result from this theory is the definition of a 2-D harmonic design space that opens up rapidly as small concessions from optimum power and efficiency matching conditions are made. A design example is described and fabricated, which demonstrates the utility of using the second harmonic clipping contour during the PA design process. A 10-W GaN demonstrator gives measured continuous wave power > 8.5 W, efficiency > 60%, and better than -30-dB adjacent channel power ratio over a bandwidth of 1-2.9 GHz.

The morphology and impact on leakage currents of two different ohmic metal stacks for GaN based transistor devices is investigated in this work. The results have implications for the performance and reliability of a GaN transistor device. A low temperature Ta based and a higher temperature anneal Ti based metallization are compared. The low temperature process shows a smoother metal semiconductor interface together with several orders of magnitude lower vertical and lateral leakage compared to the conventional higher temperature process. In addition to the leakage tests, back bias ramping experiments are performed unveiling potential advantages of the conventional approach in mitigating current collapse. However the low leakage will enable higher voltage operation making the low temperature process the preferable choice for high power RF applications, if simultaneously current collapse can be controlled.

This paper presents the robust characterization of nonlinear microwave devices driven by broadband modulated multi-sine stimuli by using a refined multi-tone waveform measurement system. The substantial contribution comes from the capability of the measurement system to measure and average the time domain waveforms of adjacently modulated signals on a similar time scale for different modulation frequencies. The enhanced system demonstrates the ability of presenting the constant baseband (IF) loads across wide modulation bandwidth which is extremely imperative for the precise evaluation of inherent nonlinearity of microwave devices. The measurement system is later applied for the experimental investigations of baseband impedance variation effects on 10W GaN HEMT through the optimization scheme based on the simultaneously engineering of significant baseband components(IF1 and IF2) and higher baseband components(IF3 and IF4).

Este artículo describe un ejemplo de setup, para la medición de las formas de onda durante la caracterización load-pull de un dispositivo de microondas con alta capacidad de potencia. La significancia de está característica de la medición, se resalta al estudiar la forma en la cual puede ser utilizada, en el diseño de amplificadores de microndas con altas potencias de salida y alta eficiencia.

The intrinsic performance of the devices is of great meaning during power amplifiers design. A method to update de-embedding network at 5.8 GHz for packaged power devices is put forward based on physical modeling idea. The de-embedding network of a packaged GaN HEMT is presented and its errors are analyzed based on waveform engineering. The results may well lead to optimization of the de-embedding network.

The intrinsic performance of the devices is of great meaning during power amplifiers design. A method to update de-embedding network at higher frequency for packaged power devices is put forward based on physical modeling idea. The de-embedding network at 5.8 GHz of a packaged GaN HEMT is presented and its practicability is verified through error analysis. This method is prospected to be applied to other packaged microwave devices.

This paper reports on the development of an RF IV waveform based stress test procedure. DC and low-voltage RF characterisation was carried out before and after high power RF stress. RF waveform measurements showed that the exact change in the RF load line induced during RF degradation cannot be directly inferred from the DC or low power RF measurement. The RF degradation takes the form of a knee-walkout, a small pinch-off shift consistent with charge trapping and defect generation, and in addition gate leakage occurs once the RF voltage exceeds a critical voltage. (C) 2012 Elsevier Ltd. All rights reserved.

In this paper, an extended version of the continuous class-F-1 mode power amplifier (PA) design approach is presented. A new formulation describing the current waveform in terms of just two additional parameters, while maintaining a constant half-wave rectified sinusoidal voltage waveform, allows multiple solutions of fundamental and second-harmonic impedances that provide optimum performance to be computed. By varying only the imaginary parts of fundamental and second-harmonic impedances, it is shown that output performance in terms of power and efficiency is maintained constant and equal to that achievable from the standard class-F-1 . Indeed, when presenting resistive second-harmonic impedances, it will be demonstrated that the fundamental load can be adjusted to maintain satisfactory output performances greater than a certain predetermined target value. The measurements, conducted on a GaAs pHEMT device at 1 GHz, show a good agreement with the theoretical analysis, revealing drain efficiencies greater than 70% for a very large range of load solutions, which can translate to an ability to accommodate reactive impedance variations with frequency when designing broadband PAs.

Mathematical analysis of Doherty amplifiers have assumed many simplifications. Most notably, the peaking amplifier does not contribute power into the load and the peaking stage has an observed impedance of infinity. This paper will show that these simplifications impair the performance of a single-input Doherty amplifier and that phase tuning for compensation is needed to improve the overall system performance. The dual-input Doherty amplifier is capable of overcoming the limitations of power-dependent phase imbalance and phase compensation lines at the input of the peaking stage; however, the characterization of such an architecture is not straightforward. A new measurement technique is proposed to measure dc current, dc voltage, and output power levels to allow unique characterization of a dual-input Doherty amplifier. Phase compensation lines at the input of the peaking amplifier will be shown to be not required, as long as correct offset lines are calculated for both the carrier and peaking stage and that the λ/4 transmission-line length is not necessarily required for active load-pull. Results of a dual-input inverse load modulated Doherty amplifier are presented where the peaking stage delivers 10 dB less of maximum output power than the carrier, while still maintaining Doherty behavior. The peaking stage can therefore be implemented with a smaller device than the carrier.

This article presented a review of the most common load-pull approaches adopted in the measurement and characterization of large-periphery microwave transistor devices. Although the quarterwave transformer technique is simple and very cost-effective, it has serious limitations in terms of scalability, thereby necessitating a separate quarterwave transformer for each device and frequency. Furthermore, due to the limited bandwidth of the quarterwave transformer, its usage in harmonic load-pull applications is severely limited.

The extended continuous class-F mode RF power amplifier (PA) is presented for the first time. The introduction and experimental validation of this novel PA mode demonstrates a new design space over a wide band of frequencies. This paper will show that high output power and drain efficiency, equivalent to the class-F mode, can be maintained by varying the reactive components of fundamental and second harmonic impedances in accordance with the new formulation of the voltage waveform. Additionally it will be shown that, by varying both phase and magnitude of the fundamental and second harmonic impedances, a yet wider design space can be achieved, where the efficiency is maintained at a level greater than a certain target value. For the validation of this new theory, an experimental investigation was carried out on GaAs pseudomorphic HEMT devices and demonstrates that high output power and drain efficiency between 75%-83% can be achieved over a wide range of fundamental and second harmonic loads.

The paper presents the power amplifier design. The introduction of a practical harmonic balance capability at the device measurement stage brings a number of advantages and challenges. Breaking down this traditional barrier means that the test-bench engineer needs to become more aware of the design process and requirements. The inverse is also true, as the measurement specifications for a harmonically tuned amplifier are a bit more complex than just the measurement of load-pull contours. We hope that the new level of integration between both will also result in better exchanges between both sides and go beyond showing either very accurate, highly tuned device models, or using the device model as the traditional scapegoat for unsuccessful PA designs. A nonlinear model and its quality can now be diagnosed through direct comparison of simulated and measured wave forms. The quality of a PA design can be verified by placing the device within the measurement system, practical harmonic balance emulator into the same impedance state in which it will operate in the actual realized design.

After calibration, since the systematic imperfections of the envelop load-pull (ELP) components were now fully accounted for, the user is able to rapidly set accurate terminations with full Smith chart coverage. This functionality has been achieved by optimizing the hardware configuration of the envelop load-pull concept. Development of a system whose systematic errors could be described by a magnitude invariant error flow model was critical. As a consequence, a robust calibration mechanism, that is analogous to the one-port error correction of a vector network analyzer, was exploited and comprehensively verified. After calibration, since the systematic imperfections of the ELP components were now fully accounted for, the user is able to set accurately terminations with full Smith chart coverage. Finally, measurements on commercially available transistor devices are presented that verify the rapid nature, accuracy, flexibility, reliability, and ease of calibration of the multiharmonic load-pull system.

The design and implementation of a class-J mode RF power amplifier is described. The experimental results indicate the class-J mode's potential in achieving high efficiency across extensive bandwidth, while maintaining predistortable levels of linearity. A commercially available 10 W GaN (gallium nitride) high electron mobility transistor device was used in this investigation, together with a combination of high power waveform measurements, active harmonic load-pull and theoretical analysis of the class-J mode. Targeting a working bandwidth of 1.5-2.5 GHz an initial power amplifier (PA) design was based on basic class-J theory and computer-aided design simulation. This realized a 50% bandwidth with measured drain efficiency of 60%-70%. A second PA design iteration has realized near-rated output power of 39 dBm and improved efficiency beyond the original 2.5 GHz target, hence extending efficient PA operation across a bandwidth of 1.4-2.6 GHz, centered at 2 GHz. This second iteration made extensive use of active harmonic load-pull and waveform measurements, and incorporated a novel design methodology for achieving predistortable linearity. The class-J amplifier has been found to be more realizable than conventional class-AB modes, with a better compromise between power and efficiency tradeoffs over a substantial RF bandwidth.

RF I-V waveform measurement and engineering systems are now finally enabling practical waveform engineering to be directly undertaken with systems capable of supporting continuous wave stimulus reaching a high level of maturity. On-going research and development activities are presently addressing the multitone requirement. The availability of RF I-V measurement and engineering capability extends the characterization opportunities for both high-frequency/speed transistor technology developers and circuit/system designers; terminal waveforms are the unifying theoretical link between transistor technology, circuit design, and system performance. Design support can involve the direct utilization of such a measurement system in the design investigation/evaluation loop of either power transistor technology or PAs. This eliminates the black box design processes and allows for the development of new intelligent design processes that are completely founded on theoretical waveform analysis. Alternatively, it can also indirectly support the amplifier investigation/evaluation loop by supporting the development or improving the accuracy of nonlinear transistor models or by providing CAD-accessible behavioral or behavioral model parameter datasets. W can now only hope that, triggered by the availability of RF waveform measurement and engineering systems, we will see a renaissance in theoretical waveform mathematical analysis addressing not only power and efficiency but also design sensitivity and linearity.

This paper presents a comprehensive study on the effective utilization of large-signal measurement data in the nonlinear computer-aided design (CAD) process. To achieve this goal two distinctive, yet mutually complementary, approaches have been integrated. Measured nonlinear data was, in the first instance, directly integrated into a nonlinear CAD simulator, and in the second instance, utilized for a direct extraction of behavioral model parameters. The formulation of the developed model is based on the polyharmonic distortion approach. The combination of both the direct utilization of nonlinear data and the subsequent model generation into an integrated nonlinear design procedure offers rapid, yet reliable, deployment of the CAD-based design environment for complex large-signal simulations.

There are many applications where the operational environment of the antenna is challenging, which means its impedance can be highly variable, so the RF PA needs to be able to operate over a wide variety of loads without stress or failure. Assessing this is a key requirement of reliability testing, with VSWR sweeps being a typical way to test this durability. It is important to make sure the amount of information gained from these sweeps is maximized, so adding RF I-V waveform information can help give a more accurate view of what is occurring at the current generator plane. Also if the fundamental and second harmonic loads are systematically swept significant voltage stress, possibly not seen during the current conventional VSWR tests, is observed, which has implications in both the output matching network design and the current method of testing.

This paper presents a powerful new method that generates a frequency-scalable nonlinear simulation model from single-frequency large-signal transistor X-parameter data. The method is based on a novel orthogonal identification (direct extraction) of current source and charge source contributions to the spectrally rich port currents under large-signal conditions. Explicit decomposition formulae, applied entirely in the frequency domain, are derived in terms of sensitivity functions at pairs of large-signal operating points related to one-another by time-reversal transformation. The method is applied and validated with respect to data from a measurement-based model of a pHEMT transistor. It is demonstrated that the scalable model can predict the nonlinear performance of the transistor over several orders of magnitude in frequency, all from X-parameters at a single fundamental frequency.

This paper presents an enhanced time-domain modulated waveform measurement and engineering system. The measurement system is based around a standard sampling oscilloscope and consists of a test set which integrates both RF and IF measurement and engineering, merging the capabilities of DC, CW, and multi-tone measurement system. The aim of the system is to extend the design role of waveform measurement and engineering into the multi-tone domain allowing optimization of power amplifiers under more realistic operating conditions akin to those found in modern day wireless systems. A GaN transistor has been measured, and results are presented that highlight the capabilities and applications of the system.

Electroluminescence microscopy and spectroscopy have been used to investigate hot electron concentration and electron temperature during RF operation. Two modes of operation were chosen, Class B and Class J, and compared with DC conditions. Hot electron concentration and temperature were on average lower for both RF modes than under comparative DC conditions. While these average values suggest that degradation due exclusively to hot electrons may be lower for RF than for DC conditions, the peak values in EL intensity and electric field along dynamic load lines have also to be taken into account and these are higher under Class J than Class B.

Envelope tracking (ET) power amplifiers achieve wideband efficiency over dynamic range by modulating supply voltage in response to the input envelope signal magnitude. Shaping functions relate input envelope magnitude to dynamic supply voltage and can be defined to achieve optimum performance in terms of not only efficiency and power, but also linearity. Using an active harmonic load-pull measurement system, this paper explores the trade-off between linearity and efficiency in terms of the intrinsic current and voltage behavior within an emulated ET environment, and as determined by different envelope shaping functions. The analysis compares the behavior of conventional class-AB and high-efficiency class-F modes in an ET architecture, using a 50V LDMOS device. Experimental results at 900MHz show that simple shaping functions with only second order terms are able to generate linear relationships between the fundamental output current and input voltage envelopes. In the case of class-F, this is achieved while maintaining high-efficiency, and thus raises the attractive prospect of using an ET architecture to reduce required linearizer complexity - an important factor in small-cell base station power amplifier (PA) design.

Hot electrons in AlGaN/GaN high electron mobility transistors are studied during radio frequency (RF) and DC operation by means of electroluminescence (EL) microscopy and spectroscopy. The measured EL intensity is decreased under RF operation compared to DC at the same average current, indicating a lower hot electron density. This is explained by averaging the DC EL intensity over the measured load line used in RF measurements, giving reasonable agreement. In addition, the hot electron temperature is lower by up to 15% under RF compared to DC, again at least partially explainable by the weighted averaging along the specific load line. However, peak electron temperature under RF occurs at high VDS and low IDS where EL is insignificant suggesting that any wear-out differences between RF and DC stress of the devices will depend on the balance between hot-carrier and field driven degradation mechanisms.

Here we present a comparison of the Large Signal Measurements provided by both a VNA based and a sampler based LSNA system. In this study, in order to achieve a robust and reliable relative phase calibration a dual frequency phase differential method was used. Significantly this work compares measurements performed under both CW and pulse mode operation. Very similar RF I-V waveforms are achieved in both cases, verifying that both architectures can provide comparable measurements not only in CW but also under pulsed operation. The test device was a GaN on silicon carbide HFET.

An active load pull waveform measurement system has been utilized to investigate, by drain current waveform analysis, the effect of short circuits at the second and higher harmonics on the gate of a 750 μm Gallium Arsenide transistor. It is confirmed that the half wave rectified sinusoidal current waveform necessary for modes of operation such as class B, J and F is not optimally generated at X-Band frequencies for transistors controlled purely by bias. The disrupting effect of the nonlinear device gate capacitance must be accounted for to take full advantage of these high efficiency modes. The addition of a simple wide band filter circuit at the input of a MMIC test cell to “short” the gate higher harmonics is shown to force the drain current waveform towards the ideal case and hence yield a significant increase in drain efficiency of up to 10 percent.

Push-pull power amplifiers (PAs) operating at HF through to GHz frequencies typically employ a transmission line balun structure. This letter demonstrates that their performance characteristics in high efficiency PA applications are critically different from conventional transformers. For the first time, the effect of the even-mode open-circuit termination on the output waveforms is measured. A novel mathematical formulation is proposed to describe the time-domain waveforms by defining the harmonic impedance environment in terms of odd and even mode excitation rather than tuned harmonics. Experimental verification using harmonic load-pull measurements showed good agreement with the theoretical waveforms generated from factorized waveform expressions.

Achieving optimal efficiency in FET-based power amplifiers used in envelope tracking (ET) architectures can be difficult, mainly due to the dynamic variation of drain-to-source capacitance (C ds ) with applied drain voltage. If, for example class-F or inverse class-F high-efficiency modes are used, there is clearly a motivation to maintain devices in high-efficient states, over as much of the dynamic range as possible, where the operating supply voltage varies quite dramatically. In order to identify optimal matching solutions, the optimum fundamental and harmonic impedances need to be determined and understood at different drain voltages (V ds ). Using time-domain waveform measurements and active harmonic load-pull at the device current generator plane, this paper analyzes the behavior of the current and voltage waveforms present at the output of a 10W high-voltage laterally diffused metal oxide semiconductor (HVLDMOS) device in an emulated ET setting. The measurement system is used to robustly engineer optimized class-F operation at different drain voltages at an operating frequency of 900MHz. A design methodology is then discussed that allows optimized power amplifier performance for different average V ds , within the operational ET supply voltage range, and the impact this has on overall efficiency.

In [1] a new formulation for quantifying the linearizing baseband voltage signal, injected at the output bias port, to linearize a device behaviour was introduced. A key feature of this approach is that since it is formulated in the envelope domain the number of linearization coefficient required is independent of the envelope shape, complexity. This property is validated by performing baseband linearization investigations on a 10W Cree GaN HEMT device. Modulated signals with increasing complexity 3, 5, and 9-tone modulated stimulus, at 1.5dB of compression, were utilized. In all cases just two-linearization coefficients needed to be determined in order to compute the output baseband signal envelope necessary. Intermodulation distortion was reduced to around -50dBc, a value very close to the dynamic range limit of the measurement system.

Baseband injection provides a useful approach for use in linearizing power amplifiers. The challenge is the determination of the required baseband signal. In [6] a generalized formulation quantifying the baseband voltage signal, injected at the output bias port, to linearize the device behavior was introduced. This envelope domain based solution requires the determination of only a small number of linearizing coefficients. More importantly these coefficients should be stimulus, hence bandwidth independent. This property has been experimentally investigated using a 10W Cree GaN HEMT device under a 3-tone modulated stimulus at 1.5dB of compression. It will be shown that the linearization coefficients were invariant when varying the modulation bandwidth from 2MHz to 20MHz.

This paper investigates the performance of a class-F mode power amplifier (PA) integrated in an envelope tracking (ET) environment, compared to the conventional class-AB mode of operation in the same setting. A 10W high voltage laterally diffused metal oxide semiconductor (HVLDMOS) device is used to perform the comparison at 900MHz using an active load pull system in an emulated ET environment at 900MHz. The analysis looks at three scenario of optimization: when the class-F and class-AB PA's are optimized at individual drain voltage within the ET range, optimized at peak drain voltage, and optimized at the average drain voltage. The challenges of maintaining the device in class-AB and class-F modes throughout the ET range due to the variation of the device output capacitance are also presented in terms of the trajectory of the fundamental and harmonic loads, as well as the degradation in drain efficiency.

This paper presents a case study of performance comparison between a passive load pull system that uses a vector network analyzer (VNA) as its receiver, and an active load pull system that uses a sampling oscilloscope. The objective of the comparison was to enable parallel research activities between two sites. The two systems are independently used to measure the same device under test, a packaged high-voltage laterally diffused metal oxide semiconductor (HVLDMOS) device at a fundamental frequency of 900MHz and under the same bias and drive settings. A simulation of the device performance is also performed using Agilent ADS to accompany the measurement results and to verify the accuracy of the device model. Results show that both load pull systems are well correlated within two times the measurement uncertainty and that the device model gives a good performance prediction. A further investigation is performed by manipulating the harmonic loads using the active load pull system to demonstrate its advantages over the passive system in discovering the true capability of the device under test in terms of drain efficiency.

This paper introduces the first formulation and approach that enables measurement based non-linear behavioral look-up table transistor models to be frequency scalable. The experimental results on a M/A-COM GaN HFET from 2 GHz to 8 GHz, support theoretical analysis that frequency domain behavioral models defined in the admittance domain have frequency scalable model coefficients. Load-pull results indicate that the model can accurately predict non-linear behavior at frequencies where the large signal measurements were not performed.

This paper presents an alternative approach to improving the vector measurement accuracy, especially near the edge of the Smith Chart, of load-pull measurement systems. Improved measurement accuracy, after vector calibration, is achieved by exploiting the load-pull capability during calibration to minimize the impact of measurement errors on the raw data of the calibration standards before it is utilized in the traditionally implemented LRL/TRL calibration algorithm. This approach eliminates the need to utilize complex optimization algorithms post calibration. The proposed method has been tested and applied to actual measurement data.

This paper presents the design, implementation, and experimental evaluation of a high efficiency continuous Class BJ mode power amplifier, using a compact defected ground structure (DGS) to provide the necessary output matching and harmonic termination for broadband operation. Detailed consideration has been given to the DGS microstrip line impedance and corresponding equalization network, in order to achieve the required fundamental and harmonic matching. The method is demonstrated through design and realization of an amplifier using a commercially available 10W GaN HEMT transistor that achieves efficiencies above 70% over a 600MHz bandwidth with an output power of at least 40 dBm.

Baseband injection is a technique that can provide a cost-effective linearizing solution that can be combined with supply modulation techniques such as envelope tracking (ET), to minimize AM/AM distortion and potentially simplify the DSP linearization requirement and associated cost. Recently [8], a new approach for computing the baseband injection stimulus, formulated in the envelope domain, was introduced. The concept was originally demonstrated using a 10W Cree GaN-on-SiC HFET device. In this work its robustness with respect to alternative device technology is investigated using 25W Nitronex NPTB00025 GaN-on-SiC HEMT depletion-mode and a 10W, high-voltage LD-MOS, enhancement-mode devices. Its effectiveness in dealing with AM/AM distortion is confirmed.

A measurement system combining vector corrected waveform measurements with active harmonic load-pull extends, for the first time, real-time experimental waveform engineering up to the 30-W power level. The vector correction procedure is presented in this paper. A novel harmonic load-pull approach based on the real-time measurement capability of the system is demonstrated on a 4-W LDMOS device. A 20% increase in maximum output power to 4.7 W without degrading gain and efficiency is realized. Waveform analysis at various drive and load conditions directly identifies nonlinear capacitance effects being a key design issue for the design of highly efficient power amplifier.

A novel formulation for the voltage waveforms in high efficiency linear power amplifiers is described. This formulation demonstrates that a constant optimum efficiency and output power can be obtained over a continuum of solutions by utilizing appropriate harmonic reactive impedance terminations. A specific example is confirmed experimentally. This new formulation has some important implications for the possibility of realizing broadband >10% high efficiency linear RF power amplifiers.

This paper compares two popular high power, high efficiency modes of operation, class F and inverse class F, and assesses the peak obtainable drain efficiencies when using Si LDMOS devices in a limited bandwidth design. Optimum class F and inverse class F conditions are presented using active harmonic load-pull measurements, and it was found that a higher drain efficiency was achieved in the class F configuration. This result is due to the limitations imposed by the soft voltage breakdown occurring due to the extended voltage swings inherent to inverse class F, as a consequence generating unwanted current content during the off cycle. This significantly reduces the peak measured efficiency using Si LDMOS devices when implementing an inverse class F design with a drain bias of 28 V. By reducing the drain bias to 18 V, to accommodate the voltage extension of inverse class F, it became possible to achieve peak measured efficiencies much closer to what theory predicted.

A novel FET concept, using low temperature grown GaAs as surface passivation and buffer layer material, has been developed to tolerate high levels of input overdrive and to improve electrostatic discharge (ESD) resistance. It is shown that high input levels 17 dB beyond the 1 dB compression point, do not lead to the burnout of the device and that, at the same time, the ESD failure voltage can be increased compared to conventional GaAs based MESFETs.

The inter-modulation distortion products vary in amplitude and asymmetry due to the effects of baseband and 2nd harmonic impedance. This paper presents an investigation into the relationship between the IMD asymmetries caused by baseband impedance variations and looping or hysteresis that can sometimes appear in the dynamic transfer characteristics of microwave power devices when subjected to modulated excitation. Here, the investigations are carried out on 2W GaN HFET bare die device characterized at 2.1GHz, and using IF active load-pull to quantify the role of baseband impedances on observed hysteresis in the dynamic transfer characteristics. Analysis is performed in envelope domain in order to more effectively reveal the DDT's sensitivity to electrical baseband memory effects.