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The rapid growth of data center, ubiquitous cloud computing, and mobile gadgets has made flash memory one of the major semiconductor markets. The booming request of flash memory has not only brought substantial economic and societal benefit but led to growing power consumption. The operation voltage of existent flash memory is in the range of 15–17 V which still has much room to be reduced to save power while ensuring environmental sustainability. To enable flash memory at lower voltage, developing innovative materials and structures is a prerequisite. Recently, crystalline oxide is extensively developed as a novel charge trapping layer (CTL) and holds the prospect of becoming a promising candidate for memory applications by demonstrating operation voltage lower than 10 V. In this paper, how crystalline oxide in the form of high-k dielectric and semiconductor material can be employed in flash memory as the CTL to reduce the operation voltage and the mechanism to achieve this goal are reviewed. From the good memory performance in terms of a large memory window of 1.5 V by programming/erasing at voltage lower than 10 V for 1 ms, endurance more than $10^{5}$ operation cycles, desirable retention at 85 °C, employing crystalline oxide as the CTL has ushered in a new field to implement green flash memory devices.

In this paper, we demonstrate that a low power flash FPGA based micro-system can provide a low power programmable interface for closed-loop brain implant inter- faces. The proposed micro-system receives recording local field potential (LFP) signals from an implanted probe, performs closed-loop control using a first order control system, then converts the signal into an optogenetic control stimulus pattern. Stimulus can be implemented through optoelectronic probes. The long term target is for both fundamental neuroscience applications and for clinical use in treating epilepsy. Utilizing our device, closed-loop processing consumes only 14nJ of power per PID cycle compared to 1.52µJ per cycle for a micro-controller implementation. Compared to an application specific digital integrated circuit, flash FPGA's are inherently programmable.

The flash memory technology meets physical and technical obstacles in further scaling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell benefits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications.

In this work we present a modeling study of a conceptual low power non-volatile memory cell based on inorganic molecular metal oxide clusters (polyoxometalates (POM)) as a storage media embedded in the gate dielectric of a Fully Depleted SOI (FD SOI) with reduced statistical variability. The simulations were carried out using a multi-physics simulation framework, which allows us to evaluate the variability in the programming window of the molecular based flash cell with an 18 nm gate length. We have focused our study on the threshold voltage variability influenced by random dopant fluctuations and random special fluctuations of the molecules in the floating gate of the flash-cell. Our simulation framework and conclusions can be applied not only to POM-based flash cell but also to flash cells based on alternative molecules used as a storage media.

A high energy high peak power flash-lamp pumped pulsed Nd:YAG solid-state laser is reported in this paper. The symmetrical resonator laser is developed and rated at single pulse energy 60 J, peak power 30 Kw with beam parameter product 2 mm·mrad. The total system electro-optics efficiency of the lamp-pumped YAG laser is as high as 3.1 % with pulse width tunable between 0.05 ∼ 2 ms. The results are consistent with the theoretical analysis and simulation.A high energy high peak power flash-lamp pumped pulsed Nd:YAG solid-state laser is reported in this paper. The symmetrical resonator laser is developed and rated at single pulse energy 60 J, peak power 30 Kw with beam parameter product 2 mm·mrad. The total system electro-optics efficiency of the lamp-pumped YAG laser is as high as 3.1 % with pulse width tunable between 0.05 ∼ 2 ms. The results are consistent with the theoretical analysis and simulation.

A novel erasing method utilizing avalanche hot-electron injection for low power flash memory applications is proposed and investigated. In this new bias scheme, a single internally pumped voltage (

A multiple-stage simulation procedure identifies, for the first time, the location of secondary electrons that very efficiently produce gate currents in flash EEPROMs. The simulation method incorporates both electron and hole Monte Carlo analysis to calculate this secondary electron gate current without introducing additional fitting parameters. (I/sub g//I/sub d/) continues to increase for smaller channel length (50/spl times/ from L/sub g/-03.39 to 0.12 /spl mu/m) and higher substrate doping (more than 6/spl times/ when doubled) in scaled, low-power flash memory.

Pump‐induced thermal lensing and bifocusing have been measured for flash‐pumped CaLaSOAP:Nd, together with long‐pulse and Q‐switched laser efficiencies. The results show that CaLaSOAP:Nd maintains its high efficiency in the Q‐switched mode, that it is capable of average power operation exceeding 1 J at 30 pps, and that bifocusing is less severe in CaLaSOAP:Nd than in YAG:Nd.