Search

Gate inversion current in metal-oxide semiconductor (MOS) tunneling diodes with different substrate doping is examined.

Synthesis of a high-quality graded oxide is described. Grading is accomplished by growing a high-temperature oxide above the silicon dioxide viscoeleastic temperature under a pregrown lower-temperature silicon dioxide layer.

Electrical properties of silicon oxide films grown by oxygen radical generated in Kr/O[sub 2] mixed high-density, microwave-excited plasma at 400 degrees centigrade are investigated. Such films have excellent electrical properties, even in ultra-regions.

A new study investigates the degradation of the dielectric breakdown field of thermal SiO2 film caused by voids in Si wafers.

Leakage currents and dielectric breakdown have been studied in MIS capacitors of metal-aluminum oxide-silicon. Thermal oxidation, which was studied, gave Al(sub.2)O(sub.3) with thickness and structure dependent on process time and temperature. Best electrical properties were seen when AlN was oxidized fully leaving no residue. For reliability of circuits working under extreme conditions it may be important that temperature dependence of the current vs electric field showed the conduction mechanism to be Frenkel-Poole emission and that higher temperatures were seen to reduce current.

A new Nb/Al-AlO(sub x)/Nb integrated circuit process with very small critical current spread was developed. It was designed to precisely control critical parameters for large scale integration. Several improvements such as the use of Electron Cyclotron Resonance Plasma Enhanced Chemical Vapor Deposition were made to reduce critical current and other parameter spreads. The new process is reviewed as well as its fabrication.

Metal alkoxides as the starting precursor materials were used as the metal deposition technique to grow metal oxide films on single crystal oxide substrates and deformation textured metal substrates. The grain alignment, morphology and crystallinity of the oxide films depended on the process conditions and the substrate properties. A range of oxygen partial pressures and temperatures were used in growing epitaxial oxide films on technologically important metal substrates.

A study was conducted on the characteristics of electron capture after hot-hole injection into a 131-A silicon dioxide, which was then compared with those after Fowler-Nordheim electron injection. Positive charges were accumulated in the oxide after hole injection from the silicon substrate into the oxide. The low-field electron capture observed may be explained based on the electron tunnelling from the substrate into the positive charge and neutral trap centers created near the substrate-SiO2 interface.

Soft breakdown properties in thin gate oxide films were examined using constant current stress measurements with different bias conditions. Two modes of the soft breakdown were identified from the current conduction characteristics of post breakdown oxides, namely, analog mode and digital mode. The stress current determined the generation probabilities of these two modes as well as the hard breakdown. The implications of the experimental results are discussed.

Stress-induced leakage current in ultrathin metal oxide semiconductor SiO2 films are modeled and simulated to interpret the main features of low-field conductivity of virgin as well as stressed oxides and to accurately represent experimental data obtained from devices fabricated with different technologies. Results showed that the device characteristics are essentially independent of technology and thickness depending on insulator thickness and stress conditions.

The total dose response of Si/Si[O.sub.2] structures with ultrathin (20-40 [Angstrom]) thermal oxide layers grown on porous silicon substrates has been studied by Electron Paramagnetic Resonance (EPR) spectroscopy. The modification of the interface defect passivation and the generation of oxide defects have been analysed as a function of dose for three series of samples with different initial hydrogen passivation states.

Charge trapping on several energy levels and thermally activated detrapping phenomena in Si[O.sub.2] have been determined by finite elements simulation. The results obtained agree well with experimental charge detrapping measurements, and enable the simulation of post-irradiation effects in Si/Si[O.sub.2] structures.

This paper presents characteristics of microwave transmission in coplanar waveguides (CPW's) on silicon (Si) substrates fabricated through commercial CMOS foundries. Due to the CMOS fabrication, the metal strips of the CPW are encapsulated in thin films of Si dioxide. Many test sets were fabricated with different line dimensions, all on p-type substrates with resistivities in the range from 0.4 [Omega] [center dot] cm to 12.5 [Omega] [center dot]. cm. Propagation constant and characteristic impedance measurements were performed at frequencies from 0.1 to 40 GHz, using a vector-network analyzer and the through-reflect-line (TRL) deembedding technique. A quasi-TEM equivalent circuit model was developed from the available process parameters, which accounts for the effects of the electromagnetic fields in the CPW structure over a broad frequency range. The analysis was based on the conformal mapping of the CPW multilayer dielectric cross section to obtain accurate circuit representation for the effects of the transverse fields. Index Terms - CMOS, coplanar waveguide, deembedding, microwave propagation on silicon substrate, on-wafer measurement.

A study was conducted to examine the characteristics of polysilicon oxides which are thermally grown and deposited in polysilicon films. Chemical mechanical polishing technique was utilized to enhance the surface roughness of polysilicon films wherein polyoxides are set. Study revealed that the polyoxides deposited in polysilicon films exhibited lower current leakage, lower density of trapped charges, lower electron trapping but higher dielectric breakdown and higher electron barrier height.

We have performed current-voltage, capacitance-voltage and electron-paramagnetic-resonance (EPR) characterization of silicon-on-insulator (SOI) samples, subjected to a wide variety of irradiation and anneal treatments. By comparing transport properties and interfacial reaction mechanisms, we provide evidence for an intrinsic difference in the response of mobile protons in these oxides, depending on whether they are generated by irradiation or by [H.sub.2] annealing. A radiation effects study of SOI buried oxides containing annealing induced mobile protons is presented to gain insight into the mechanisms behind these fundamental differences. Electrical characterization shows that, for these devices, the initial interface trap and mobile proton densities are largely unaffected by the irradiation. However, if the irradiation is carried out in the presence of positive bias applied to the top Si, the protons become trapped in shallow levels. These proton traps are activated by the irradiation and are located near the oxide/substrate interface. These results may lead to improved radiation hardness of buried oxides for nonvolatile memory and other applications.

Silicon oxide (Si[O.sub.2]) films have extensive applications in integrated circuit fabrication technology, including passivation layers for integrated circuits, diffusion or photolithographic masks, and interlayer dielectrics for metal-insulator structures such as MOS transistors or multichip modules. The properties of Si[O.sub.2] films deposited by plasma enhanced chemical vapor deposition (PECVD) are determined by the nature and composition of the plasma, which is in turn controlled by the deposition variables involved in the PECVD process. The complex nature of particle dynamics within a plasma makes it very difficult to quantify the exact relationship between deposition conditions and critical output parameters reflecting film quality. In this study, the synthesis and optimization of process recipes using genetic algorithms is introduced. In order to characterize the PECVD of Si[O.sub.2] films deposited under varying conditions, a central composite designed experiment has been performed. Data from this experiment was then used to develop neural network based process models. A recipe synthesis procedure was then performed using the optimized neural network models to generate the necessary deposition conditions to obtain several novel film qualities, including zero stress, 100% uniformity, low permittivity, and minimal impurity concentration. This synthesis procedure utilized genetic algorithms, Powell's algorithm, the simplex method, and hybrid combinations thereof. Recipes predicted by these techniques were verified by experiment, and the performance of each synthesis method are compared. It was found that the genetic algorithm-based recipes generally produced films of superior quality. Deposition was carried out in a Plasma Therm 700 series PECVD system.

The breakdown of a thin silicon dioxide Metal Oxide Semiconductor (MOS) capacitor is related to its earlier degradation under dynamic electrical stress. Degradation at low frequencies is found to be faster and higher as compared to the degradation at high frequencies. However, the differences in response at high and low frequencies vanish with ultrathin oxides, because the difference between bulk and interfaces vanishes. The re-distribution of the breakdown species from the anodic interface toward the oxide bulk explains the frequency dependence of time-to-breakdown distribution.

We find that annealing oxides in a [H.sub.2] containing ambient creates positive charge in the dielectric of Si/Si[O.sub.2]/Si structures. The H-induced positive oxide charge is shown to be very different from-radiation-induced oxygen vacancy hole traps (E' centers) in Si[O.sub.2]. We find that three factors strongly influence the ability to create H-induced positive charge: temperature, hydrogen concentration in the ambient, and the density of hydrogen cracking centers. We suggest that over-coordinated O centers are responsible for this charge. The proposed over-coordinated oxygen centers may also account for the equivocal nature of several forms of positive charge that have escaped detection by electron paramagnetic resonance, such as the fixed oxide charge that forms during the thermal oxidation of Si.

Thin silicon dioxide films show a low-level leakage current (LLLC) that is induced by the stress of hot hole injection at the gate oxide. Its voltage dependence is steeper than that of the conventional FN stress-induced LLLC. Hot electron injection and UV irradiation deactivate the leak sites at gate oxides to reduce the hot hole-induced LLLC. The generation ratio of this type of LLLC with respect to injected charge is nearly 1000 times higher than that of FN stress-induced LLLC. Sequential tunneling via trapped positive holes is its likely conduction mechanism.

Thermal conductivity measurements of thin silicon dioxide (SiO2) films used in integrated circuits indicate that thermal conductivity increases with rising temperature. The test structures comprise 0.57 micro-m to 2.28 micro-m thick films sandwiched between parallel plate-electrodes. The measured value for the tested films is 20% lower than that of the bulk fused SiO2. Simulations confirm the accuracy of the measurement method. There is a minor impact of thermal resistances at the boundaries between SiO2 and metallization, while film thickness has no effect.

Tunneling of electrons into and out of traps explains trap generation inside thin silicon oxides during high voltage stressing. An uniform relative decrease in the low-tunneling current indicates an even spatial distribution of traps across the entire oxide thickness. Properties of traps with 2.5-22 nm thicknesses and the Coulombic scattering cross section of the negatively charged traps are determined.

The charging and discharging of high-voltage, stress-generated oxide traps near oxide interfaces produces excess low-level leakage currents in 10 nanometer thin silicon oxides. The traps can be positive, negative or neutral and their charge state can be changed. The transient charging and discharging of certain traps inside the oxide produce an additional current component on measurement with voltage pulses having opposite polarity than the stress voltage. A study presents the relationship of excess low-level currents to time and voltage polarity.

A reactive ion etching system uses a back-propagation neural network-based system for predicting the etch endpoint of a silicon dioxide film in a CHF3/O2 plasma. The neural network correlates the etch rate with the dc bias to determine the remaining time necessary to etch a known thickness of silicon dioxide. Monitoring of the dc bias is done using a real time data acquisition system, where process conditions are sent from a Plasma Therm 700 series reactive ion etching system. Results obtained using the network are discussed.

We show that enhanced hole-, electron-, interface-, and border-trap generation in irradiated Si/Si[O.sub.2]/Si systems that have received a high-temperature anneal during device fabrication is related either directly, or indirectly, to the presence of anneal-created oxygen vacancies. The high-temperature anneal results are shown to be relevant to understanding defect creation in zone-melt-recrystallized silicon on insulator materials. We observe the electron paramagnetic resonance (EPR) of trap-assisted hole transfer between two different oxygen vacancy-type defects (E [prime] [Delta] [approches] E [prime] [Gamma] precursor) in hole injected thermal Si[O.sub.2] films. Upon annealing the hole injected Si/Si[O.sub.2] structures at room temperature, the E [prime] [Delta] center transfers its hole to a previously neutral oxygen vacancy ([O.sub.3] [is equivalent to] Si-S [is equivalent to] [O.sub.3]) site forming an E [prime] [Gamma] center. This process, also monitored electrically, shows a concomitant increase in the border-trap density that mimics the growth kinetics of the transfer-activated E [prime] [Gamma] centers. This suggests that both effects are correlated and that some of the transfer-created E [prime] [Gamma] centers are the entities responsible for the border traps in these devices. One implication of these results is that delayed defect growth processes can occur via slow trap-assisted hole motion in Si[O.sub.2].

An experiment was carried out to investigate the effect of CaO and Si[O.sub.2] additives on the magnetic and physical properties of Sr-Zn W-type hexagonal ferrite. The specimens were prepared by the conventional manufacturing method without atmosphere control. It was found that the magnetic properties of SrO[center dot]2ZnO[center dot]8[Fe.sub.2][O.sub.3] are considerably improved on adding 1 wt% CaO and Si[O.sub.2] together. The optimum condition of making magnet with suitable properties are as follows: chemical analysis composition: [Mathematical Expression Omitted]; semisintering condition: 1275 [degrees] C x 1 h in air; sintering condition: 1225 [degrees] C x 0.5 h in air. The magnetic properties are [J.sub.m] = 0.438 T, [J.sub.r] = 0.402 T, [H.sub.c]J = 92.4 kA/m, [H.sub.c]B = 88.8 kA/m, [(BH).sub.max] = 20.3 kJ/[m.sup.3], [T.sub.c] = 393 [degrees] C, HA = 968 kA/m, [K.sub.A] = 2.11 x [10.sup.5] J/[m.sup.3], and [n.sub.B] = 32.8[[Mu].sub.B].

Sol-gel silica electret films were coated on silicon substrates by a spin coating technique. The process of preparing the films is described and the electret behavior of the films is discussed. The films were corona charged at room temperature. Then, isothermal decay of the surface potential at room temperature and open-circuit thermally stimulated discharge (TSD) experiments were carried out. The results showed that the main peak of the TSD current spectra was situated at approximately 250 degrees C and charge deposited in the film indicated good stability for the negative charged sample. After storage at room temperature for 50 days, the surface potential of the sample still retained at approximately 90% of the initial value. We found activation energies of 1.3 and 0.7 eV for negative and positive corona charged samples. Our experimental results suggest that the sol-gel process could be useful in electret and electronic technique applications.

Acoustic proximity sensors efficiently utilize microresonators that are inexpensive and agreeable with CMOS technology. CMOS technology was employed to obtain piezoresistive measurement structures and bridge resonators, silicon oxide beams with thermal excitation. Subsequent micromachining was also employed with this technology. The bridge resonator had a vibration amplitude of a maximum of 290 nanometers, while that of the cantilever beam was 1.7 micrometers. Sensitivity of the bridge resonators was 1.3 microvolts per nanometer when polysilicon resistors were employed to trace the piezoresistivity of the vibrations. The cantilever demonstrated 1.0 millivolts per nanometer under the same conditions at a 1 milliampere constant current.

The hot carrier degradation phenomena inherent in n-channelcomplementary metal oxide semiconductor devices with lightly-doped drains is experimentally examined. The field-induced- and thermal emission of trapped electrons within the gate oxide, which only occur during ac stress conditions, are proven to cause the saturation in the drain-to-source current degradation through a unified injection and thermal re-emission model. The study clarifies the differing mechanisms present during dc stress and ac stress.

A silicon dioxide film is formed on the contact surface when it is exposed to a silicon vapor at raised temperatures. SiO2 on contact surfaces causes contact failure, depending on the type and thickness of the film. Various electrical and thermal parameters for the SiO2 film are calculated experimentally. The film grows because of the temperature and silicone vapor concentration.

A variation of the rapid thermal process (RTP) is introduced to develop highly reliable thin-gate silicon dioxide (SiO2) films. The rapid thermal oxynitridization technique uses oxygen and nitrous oxide as reactants in forming highly nitrided SiO2 films. These films exhibit greater charge-to-breakdown values and long-term reliability as compared to those fabricated using single-step RTP oxidation and furnace processes.

Research using gate line delay modeling demonstrates that resistance capacitance (RC) delay can be reduced by almost ten-fold in very large active matrix liquid crystal displays. A minimal number of holes per line and a low-resistance back line cause reduced delay. Gate line models featuring standard inverted-staggered amorphous silicon based thin-film transistors are described.