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To counteract logic-testing methods and trust verification methods for hardware Trojan (HT) detection, two HT design strategies based on high-low probability and partitioned combinational logic with a malicious reset signal are proposed. Using these two strategies, a power consumption HT and a forced reset HT are designed in a self-developed RISC-V processor. The processor is implemented using SMIC 55nm CMOS technology. Experiments show that, compared to the HTs designed with low-probability nets, the HTs designed with high-low probability strategy can reduce the triggering probability by 87.5%. The HT designed by partitioning combinational logic strategy can increase the false positive rate of HT to 40%. The result can defeat FANCI effectively. In order to enhance the stealth of the HTs, we partitioned combinational logic by using flip-flops with a malicious reset signal. The reset signal participates as a part of the trigger condition, which significantly reduces the trigger probability of HTs.

The network switches and routers require both high-speed and large-capacity packet buffers. However, existing packet buffer architectures have the problems of speed scaling and flow number scaling limitations. To address the two problems simultaneously, this paper proposes a parallel hybrid SRAM/DRAM architecture for per-flow buffering in high-speed switches and routers. Tail SRAM and head SRAM are used to apply per-flow buffering for packet aggregation, so that the middle DRAM is accessed in a larger granularity and the DRAM's bandwidth utilization is improved. To mitigate the flow number scaling limitation, a dynamic memory allocation with hard timeout (DMA-HT) memory management algorithm is designed. The key idea of DMA-HT is that the memory space is dynamically allocated for the newly arrived flows, and a hard timeout is assigned for each queue. After a specific period of time, the memory space is freed, so that the SRAM space is efficiently utilized by the most recently active flows. A queuing system is used to model the proposed method, and theoretical analysis is performed to optimize the timeout value. With the derived formulas, multiple performance parameters are quantitatively analyzed, and the optimal timeout can be obtained. Both numerical results and simulations show that the proposed architecture can and reduce packet loss rate and average delay significantly compared with previous solutions with the same SRAM capacity.

Based on the research of the standard AS6802 protocol standard [1] and the interpretation of the existing Ethernet time synchronization solution on the FPGA hardware design platform, we designed and implemented a set of Ethernet clock synchronization system that supports the AS6802 standard. The system has been tested in a network environment, and the synchronization accuracy is less than 60 nanoseconds. Use FPGA to record the transparent clock, replacing the MAC IP core time stamping method in the previous Ethernet time synchronization solution. Therefore, this system is more flexible for the reception and transmission of Ethernet frame data, and reduces the dynamic delay introduced by the MAC IP core, which makes the synchronization accuracy higher, and has the characteristics of low cost and easy transplantation.

Time-triggered Ethernet (TTE) technology introduces the concept of time-triggered on the basis of traditional Ethernet, so that it can achieve conflict-free and deterministic service forwarding without sacrificing compatibility. However, storage resources in industrial, aviation, aerospace and other equipment are limited. Therefore, it is important for TTEthernet to develop switching technologies with high storage efficiency and scalability. This paper proposes a dual plane switching (DPS) architecture for TTEthernet, which divides time-triggered services and event-triggered services into two planes for data forwarding. Experimental results show that using the TTE switch of this architecture has the advantages of high clock synchronization accuracy, high throughout, low transmission delay and small jitter of TTE service.

Packet classification is a key function in network security systems in SDN, which detect potential threats by matching the packet header bits and a given rule set. It needs to support multi-dimensional fields, large rule sets, and high throughput. Bit Vector-based packet classification methods can support multi-field matching and achieve a very high throughput, However, the range matching is still challenging. To address issue, this paper proposes a Range Supported Bit Vector (RSBV) algorithm for processing the range fields. RSBV uses specially designed codes to store the pre-computed results in memory, and the result of range matching is derived through pipelined Boolean operations. Through a two-dimensional modular architecture, the RSBV can operate at a high clock frequency and line-rate processing can be guaranteed. Experimental results show that for a 1K and 512-bit OpenFlow rule set, the RSBV can sustain a throughput of 520 Million Packets Per Second.

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions encounter the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with small and constant resource utilization. The experimental results show that the resource utilization of the proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than that of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has lower resource utilization, by 81.7%-85.9% and 2.9%-20.8%, than two state-of-the-art architectures. Furthermore, throughput and programmability are guaranteed. The source code has been made available on -1.5mm]Please cite reference [1] in the text of the paper. It was removed from the abstract as having references in an abstract is contrary to IEEE journal style. GitHub.

The development of the space–air–ground integration has put higher demands on satellite network. It needs to support high-bandwidth, large-capacity and various quality of service guarantees. However, the satellite onboard switching is facing the problem of resource constraints and special requirements of hardware complexity and scheduling efficiency. For this, this paper proposes a novel memory architecture for high-bandwidth onboard switching fabric. To reduce hardware complexity, multiplexer is used in the input side to merge k input ports into one internal bus, while the output demultiplexer splits an internal bus into k output links. Shared memory architecture is adopted in the input module to improve the memory efficiency, and a buffered crossbar is used to interconnect the input modules to the output modules. A discrete-time queuing model is formulated, and an iterative approach is used to quantitatively analyze the performance of the proposed architecture. The throughput and delay are calculated under different switch size, input load, and buffer capacity. The numerical results can serve as a guidance on deciding the required buffer size and appropriate speedup ratio. This work is validated by both simulations and FPGA implementations. Synthesize result show that using the state-of-the-art Xilinx VU13P FPGA, a switching fabric with 48 ports can be implemented and the peak throughput of the proposed architecture can reach 480 Gbps. Compared with existing combined input-crosspoint queuing, the proposed architecture can significantly reduce the packet delay and the memory resource cost.

Today’s switches and routers require high-speed and large-capacity packet buffers to guarantee a line rate up to 100 Gbps as well as more fine-grained quality of service. For this, this paper proposes an efficient parallel hybrid SRAM/DRAM architecture for high-bandwidth switches and routers. Tail SRAM and head SRAM are used for guaranteeing the middle DRAMs are accessed in a larger granularity to improve the bandwidth utilization. Then, a simple yet efficient memory management algorithm is designed. The memory space is dynamically allocated when a flow arrives, and a hard timeout is assigned for each queue. Hence, the SRAM space is utilized more efficiently. A queueing system is used to model the proposed method, and theoretical analysis is performed to optimize the timeout value. Simulation shows that the proposed architecture can reduce packet loss rate significantly compared with previous solutions with the same SRAM capacity.

Ahstract- With the rapid development of network equipment, single-port capacity becomes larger. The traditional Quality of Service applications based on single level queue and single level port become the bottleneck of the development of Software Defined Network switching equipment. Therefore, a five-level queue scheduling model based on Software Defined Network is proposed. Through five-level pipeline scheduling, this model can reduce the number of queue which every level scheduler maintenance. By choosing the appropriate scheduling algorithm and flow control algorithm, the multiple users, various flows and different types of network traffic can be uniformly managed and hierarchically scheduled. The simulation result shows that the five-level queue scheduling model reduces the weighted packet loss rate on the premise of guaranteeing the output bandwidth. It can support multiple types of traffic scheduling and flow control, and can ensure the Quality of Service of different business to some extent.

Burst traffic is a common traffic pattern in modern communication networks, and this traffic is the main cause of the unfairness problem in shared memory switch. In this paper, a shared-private buffer management (SPBM) scheme is proposed, which can efficiently utilize the switch buffer and reduce overall packet loss rate under burst traffic. The key idea of SPBM is to partition the total memory space into shared area and private area. Each output port has a private memory area that cannot be used by other ports. The shared area is completely shared among all output ports. A theoretical queuing model of the proposed scheme is formulated and closed-form formula for the overall packet loss rate is derived. By analyzing the numerical results, the optimal partition of the switch buffer is obtained. Besides, simulation result shows that the proposed scheme can reduce the overall packet loss rate by about 20% on average compared with existing buffer management schemes.

IEEE 1588 is a standard for a precision clock synchronization protocol for networked measurement and control systems. IEEE 1588 protocol can provide sub-microsecond accuracy. However, most synchronous systems generate timestamps using software-generated methods or proprietary chips. Thus, the accuracy and portability of synchronous systems cannot be balanced. Based on the analysis of IEEE 1588 standard and current Ethernet time synchronization scheme, this study presented a scheme using FPGA and ARM. In order to improve the universality and portability of synchronous system, this research adopted the method of generating hardware timestamps in Media Access Control(MAC) layer. Verified by experiment in Gigabit Ethernet environments, this design is correct and the marking accuracy is better than 20ns. The portability of synchronous system is improved on the premise of ensuring the accuracy of synchronization.

Network flow classification is a key function in high-speed switches and routers. It directly determines the performance of network devices. With the development of the Internet and various kinds of applications, the flow classification needs to support multi-dimensional fields, large rule sets, and sustain a high throughput. Software-based classification cannot meet the performance requirement as high as 100 Gbps. FPGA-based flow classification methods can achieve a very high throughput. However, the range matching is still challenging. For this, this paper proposes a range supported bit vector (RSBV) method. First, the characteristic of range matching is analyzed, then the rules are pre-encoded and stored in memory. Second, the fields of an input packet header are used as addresses to read the memory, and the result of range matching is derived through pipelined Boolean operations. On this basis, bit vector for any types of fields (AFBV) is further proposed, which supports the flow classification for multi-dimensional fields efficiently, including exact matching, longest prefix matching, range matching, and arbitrary wildcard matching. The proposed methods are implemented in FPGA platform. Through a two-dimensional pipeline architecture, the AFBV can operate at a high clock frequency and can achieve a processing speed of more than 100 Gbps. Simulation results show that for a rule set of 512-bit width and 1[Formula: see text]k rules, the AFBV can achieve a throughput of 520 million packets per second (MPPS). The performance is improved by 44% compared with FSBV and 30% compared with Stride BV. The power consumption is reduced by about 43% compared with TCAM solution.