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1. Eliminating back-gate bias effects in novel SOI high-voltage device structure

Author

Xiarong Luo, Daping Fu, Lei Lei, Bo Zhang, Zhaoji Li, Shengdong Hu, Zhengyuan Zhang, Zhicheng Feng, and Bin Yan

Subjects
Electric fields -- Analysis, Voltage -- Measurement, Gates (Electronics) -- Analysis, Silicon-on-isolator -- Design and construction, Business, Electronics, Electronics and electrical industries
Abstract

A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are described and the structure is characterized by a compound buried layer (CBL) made of two layers and a polysilicon layer between them. The maximal temperature of CBL SOI is reduced by 25 K because of a window in upper buried oxide (UBO) when compared with the conventional SOI.

Published
2009

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