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Eliminating back-gate bias effects in novel SOI high-voltage device structure
- Source :
- IEEE Transactions on Electron Devices. August, 2009, Vol. 56 Issue 8, p1659, 8 p.
- Publication Year :
- 2009
-
Abstract
- A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are described and the structure is characterized by a compound buried layer (CBL) made of two layers and a polysilicon layer between them. The maximal temperature of CBL SOI is reduced by 25 K because of a window in upper buried oxide (UBO) when compared with the conventional SOI.
Details
- Language :
- English
- ISSN :
- 00189383
- Volume :
- 56
- Issue :
- 8
- Database :
- Gale General OneFile
- Journal :
- IEEE Transactions on Electron Devices
- Publication Type :
- Academic Journal
- Accession number :
- edsgcl.207027249