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The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). The combined effect of LCDU and centroid jittering will be discussed and compared to a hole shrink process using atomic layer deposition and spacer formation. The learning from this case study can provide perspectives that may not have been investigated thoroughly in the past. By including more important elements during DSA process development, such as metal cut, the DSA maturit y can be further advanced and move DSA closer to HVM adoption.

In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.

Recently there has been a great deal of effort focused on increasing EUV scanner source power; which is correlated to increased wafer throughput of production systems. Another way of increasing throughput would be to increase the photospeed of the photoresist used. However increasing the photospeed without improving the overall lithographic performance, such as local critical dimension uniformity (L-CDU) and process window, does not deliver the overall improvements required for a high volume manufacturing (HVM). This paper continues a discussion started in prior publications [Ref 3,4,6], which focused on using readily available process tooling (currently in use for 193 nm double patterning applications) and the existing EUV photoresists to increase photospeed (lower dose requirement) for line and space applications. Techniques to improve L-CDU for contact hole applications will also be described.

A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.

With current progress in exposure source power, novel resist materials, and post processing techniques, EUV is getting closer to the production environment. As reported continuously, SEMATECH established cycles of learning program. The data generated from the program has been utilized to measure current state of the art of EUV photoresist for production or pilot line use. Thanks to SEMATECH core and associate members’ attention to the project, numerous EUV samples have been tested and they were based on the best performing EUV resists from associate members. This year we completed the evaluations for under-layers, lines and spaces, and contact holes. We also applied track based techniques to drive both low line edge roughness control and enlarge the process window with techniques such as FIRM TM and track based smoothing process. In this paper we will discuss about the results from cycles of learning test and show post-processing results of the three best line and space resists when combined with different FIRM TM materials.

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy guiding pattern was created by the IBM Almaden approach using brush materials in combination with an optional chemical slimming of the resist lines. Critical dimension (CD) uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of the DSA process were characterized. CD rectification and LWR reduction were observed. The chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly improving the DSA PW under over-dose conditions. However, the overall PW was found to be smaller than without using the slimming, due to a new failure mode at under-dose region.

The fundamental limits of optical lithography have driven semiconductor processing research to push the envelope. Double patterning (DP) techniques including litho-etch litho-etch (LELE), litho-litho etch (LLE), and self-aligned double patterning (SADP) have become standard vernacular for near term semiconductor processing as EUV is not yet ready for high volume production. The challenge, even with techniques like LLE and SADP, remains that printing small lines on tight pitches (for LLE) or even small lines on relaxed pitches for mandrel/spacer combinations is not trivial. We have demonstrated a track-based slimming technique that can produce sub-25 nm resist lines for either SADP or LLE DP processes. Our work includes results for varying shrink amounts at different target critical dimensions (CD) and for multiple pitches. We also investigated CD uniformity (CDU) and defectivity. In particular, optimization of the amount of slimming is critical as it allows for much greater process latitude at the lithography step. In addition to the lithography work, we have continued the processing for both integration schemes to include oxide deposition and etch for SADP and through etch performance for DP. We have demonstrated sub 45 nm pitch structures. The wide variety of process uses, as well as the ability to achieve a large range of shrink amounts shows that track based slimming is a viable solution to achieve target CD and pitch values for sub 22 nm technology node.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for

The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized (DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11 nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor, to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

Advanced DRAM manufacturing demands rigorous and tight process control using high measurement precision, accurate, traceable and high throughput metrology solutions. Scatterometry is one of the advanced metrology techniques which satisfies all of these requirements. Scatterometry has been implemented in semiconductor manufacturing for monitoring and controlling critical dimensions and other important structural parameters. One of the major contributing factors to the acceptance and implementation of scatterometry systems is the ability to match to reference metrology. Failure to understand the optimum matching conditions, can lead to wrong conclusions with respect to hardware stability and/or incorrect analysis of production data. This paper shows the use of the integrated scatterometry system to control the lithography processes in a real production environment. In the control system, the scatterometry Optical Digital Profilometry (ODP™) data is referenced to sampled CD‐SEM data. A significant improvement in matching between the two metrology systems was achieved following the implementation of a new ODP‐function. The results also reveal a clearer roadmap for the implementation of an integrated scatterometry based control loop system. The results also pointed to how to achieve a reduced setup time as well as a deeper understanding of the relationship between test data and production data. It has been clearly shown that to achieve the desired sub‐nanometer matching in scatterometry measurements for advanced process control, we need to pay scrupulous attention to matching data not only from test wafers but from production data in order to derive functions that will produce the optimum matching conditions.