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This poster provides an overview of IEEE P1581, for those not familiar with this standardization effort, and gives a status update of the IEEE P1581 specification development. We will also provide examples for the implementation of IEEE P1581 capabilities in SRAM, DRAM, and FLASH devices.

Boundary Scan (often also referred to as JTAG) as defined in IEEE Std. 1149.1 has been adopted by many design and test engineers as test methodology for prototype verification and for production testing. This successful and powerful technology has a few limitations, though, some of which can be overcome with newer test standards, such as IEEE 1149.4 and IEEE 1149.6. Still, practically all electronic products need to undergo a functional test before they leave the manufacturing floor. Functional tests, however, require manual, labor intensive and costly test development and often times ad-hoc test equipment configurations. This paper discusses the benefits of combining boundary scan tools with functional test equipment, with a focus on extended boundary scan applications based on reconfigurable tester hardware.

This paper highlights various challenges test engineers face when they attempt to test pin connectivity on memory devices at board and system level. IEEE P1581 was presented as an elegant solution to these challenges. Furthermore, this paper provide an update on the latest developments in the IEEE PI581 specification.

Being well established as a valuable test and debug access methodology in the commercial electronics business, JTAG/ boundary scan as defined in IEEE Std. 1149.1 continues to advance into government and military applications as well. This test technology can be implemented in test systems based on various hardware platforms. This paper presents benefits a high speed tester platform such as PXI express provides for structural test and in-system programming applications based on JTAG / boundary scan access.

Boundary scan tools in a PXI form factor allow a powerful combination with other test methodologies. This paper discusses possibilities of integrating boundary scan tools in a PXI based ATE system as well as outline test and in-system programming applications based on boundary scan at the device, board and system level. An introduction to boundary scan related design-for-testability is provided.