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In the current work, we study the process variability of logic, interconnect, and arithmetic/DSP resources in commercial 16-nm FPGAs. We create multiple, soft-macro sensors for each distinct resource under evaluation, and we deploy them across the FPGA fabric to measure intra-die variation, as well as across multiple FPGAs to measure inter-die variation. The derived results are used to create device-signature variability maps characterizing the distribution of variability across the die. Our study includes decoupling of variability to systematic and stochastic parts, exploration of variability under various voltage and temperature conditions and correlation analysis between the variability maps of the different resources. Furthermore, we scrutinize the impact of variability on the performance of actual test circuits and correlate the retrieved results with the sensor-based maps. Our experimental results on four Zynq XCZU7EV FPGAs showed significant intra- and inter-die variability, up to 7.8% and 8.9%, respectively, with a small increase under certain operating conditions. The correlation analysis demonstrated a strong correlation between the logic and arithmetic resources, whereas the interconnects showed a slightly weaker correlation in specific devices. Finally, a relatively moderate correlation was calculated between the variability maps and performance of test circuits due their dissimilar operating behavior versus our sensors.

Background To-follow surgeons suffer from tardiness of start times due to preceding surgical cases in operating rooms (OR) taking longer than scheduled. Preceding cases take longer than their expected (mean) time not only because of process variability (e.g., different surgical first assist) but parameter uncertainty (e.g., surgeon has not previously performed the procedure at the hospital). Uncommon combinations of scheduled procedures occur frequently. We quantified Bayesian methods’ mitigation of the effect of parameter uncertainty on tardiness at a hospital. Methods There were N = 7361 pairs of first and second cases of the day of different surgeons performed in the same OR and with the same sequence as that assigned as of 7 P.M. the day before surgery. For each pair, random OR times for the first case were generated from the posterior distribution incorporating surgical suite, year, estimated OR time from the surgeon and scheduler, and historical OR times, classified by combination of surgeon and scheduled procedure(s). Results The cases of a second surgeon that followed a preceding case with 0–3 historical OR times accounted for 21.1% (SE 1.2%) of the total tardiness and 17.1% (SE 0.9%) of cases. The pairwise ratios of total tardiness to cases equaled 1.233 (95% confidence interval 1.203–1.263). The calculations were repeated for cases with no historical data. The pairwise ratios averaged 1.223, not significantly different (P = 0.35). Conclusions Without using a Bayesian method, instead of 21% of tardiness attributable to cases with few data, it would be nearly 100%. Therefore, the results predict the value of using a Bayesian method for estimating OR times at hospitals with case scheduled of uncommon procedures. Bayesian methods can be implemented with a spreadsheet (e.g., Excel worksheet) or a database table updated annually.

Production cycle times (throughput rates) are a primary aspect of semiconductor manufacturing efficiency. The cycle time's dependence on the logistics of manufacturing is overwhelming. Process variability excludes “just in time” WIP delivery. And not able to deal with the inherent variability of fabrication processes, the manufacturing logistics compensates by stuffing the fab full of waiting WIP. The results are long cycle times and retarded throughput. Research indicates improvements in cycle times through the importing of hybrid logistics infrastructures into existing material handling systems. The method is demonstrated, via dynamic high-resolution simulation, by comparing full 300 mm fabs having standard or hybrid logistics. Cycle time and throughput gains are realized via the import of hybrid infrastructures.

In the absence of evidence-based laboratory guidelines, the workup and interpretation of tracheal aspirate (TA) cultures remains controversial and confusing within the fields of clinical microbiology, infectious diseases, and critical care. Between 22 January and 24 February 2020, we conducted a national, web-based survey of microbiology laboratory personnel in free-standing pediatric hospitals and adult hospitals containing pediatric facilities regarding the laboratory practices used for TA specimens. We hypothesized there would be substantial center-level variability in laboratory processing of TA cultures. The response rate for the survey was 48% (73/153). There was a high level of variability in the criteria used for all processes, including specimen receipt, Gram staining, and culture reporting. Most respondents (77%) reported they do not reject TA specimens based on Gram stain criteria, and 44% of labs do not require that a minimum number of Gram stain fields be reviewed prior to reporting results. Overall, nonacademic hospital laboratories and pediatric-only laboratories are more likely to identify, report, and perform susceptibility testing on organisms from TA cultures, regardless of organism quantity or predominance. There is a substantial amount of process variability among pediatric microbiology laboratories that affects TA culture reporting, and which guides treatment decisions. This variation within and among labs makes clinical outcome studies related to TA cultures difficult to interpret. This study serves as a pragmatic step in informing the development of robust clinical guidelines. Clinical outcome and implementation studies are necessary to determine the effectiveness of guidelines for TA cultures.

This work has been partially funded by the CNRS INS2I PUF2IOT 2020 projet and the UC3M program: Ayudas para la Movilidad del Programa Propio de Investigacion; International audience; Hardware device identification has become an im- portant feature for enhancing the security and the trust of interconnected objects. In this paper, we present a device iden- tification method based on measuring physical and electrical properties of the device, while controlling its switching activity. The method is general an applicable to a large range of devices from FPGAs to processors, as long as they embed sensors (such as temperature and voltage) and their measurements are available. The method is enabled by the fact that both the sensors and the effects of the switching activity on the circuit are uniquely affected by manufacturing-induced process variability. The device identification based on this method is made possible by the use of machine learning. The efficiency of the method has been evaluated by a preliminary study conducted on eleven FPGAs.

The new generation Manufacturing Executions System (MES) is considered as one of the most important solutions supporting the idea of Industry 4.0. This is confirmed by research conducted among companies interested in the implementation of the Industry 4.0 concept, as well as the publications of researchers who study this issue. However, if MES software is a link that connects the world of machines and business systems, it must take into account the specifics of the supported production systems. This is especially true in case of production systems with a high level of automation, which are characterised by flexibility and agility at the operational level. Therefore, personalization of the MES software is proposed for this class of production systems. The aim of the article is to present the MES system personalization method for a selected production system. The proposed approach uses the rules of Bayesian inference and the area of customisation is the technological structure of production, taking into account the required flexibility of the processes. As part of the developed approach, the variability index was proposed as a parameter evaluating the effectiveness of the production system. Then, the results of evaluation of the current system effectiveness by use of this index are presented. The authors also present the assumptions for the developed MES personalization algorithm. The algorithm uses the rules of Bayesian inference, which enable multiple adjustments of the model to the existing environmental conditions without the need to formulate a new description of reality. The application of the presented solution in a real facility allowed for determining production areas which are the determinants of system instability. The implementation of the developed algorithm enabled control of the generated variability in real time. The proposed approach to personalization of MES software for a selected class of production systems is the main novelty of the presented research and contributes to the development of the described area of research.

In the framework of High Performance Computing and Datacom, silicon photonics interposers propose an interesting approach, while providing new challenges. This paper demonstrates such an integration and focuses on TSV Mid integration impact on sensitive photonic structures such as ring modulators, focusing on two specific technological aspects: substrate thinning and TSV integration. It is shown that thinning down to 100 microns and integrating TSV do not impact photonic performances more than wafer level process variability. Finally, thanks to these results, 3D Si photonics design opportunities will be discussed.

In this paper we study the threshold voltage variability using the Pelgrom plot. The measurement data consists of drain current, output characteristics and threshold voltage for 14-nm FinFETs depending on their location on the silicon wafer. The results showed that the technology is mature with small mismatch and parameter variability.

International audience; Transistor arrangement influences the performance of logic cells. Complex logic cells can be used to minimize area, delay, and power. However, with the increasing relevance of nanometer challenges such as process variability and radiation effects, it is also necessary to consider these factors at logic level design. The main contribution of this work is to evaluate the advantages of adopting a multi-level logic design instead of using complex gates to mitigate process variability and radiation effects. A justification for choosing the parameter that will characterize process variability is presented. Also, the analysis with different transistor arrangements and sizing is carried out to provide a basis for a better understanding of the obtained results. The experimental evaluation considers two topologies: complex gates and multi-level using basic gates, for a set of logic gates using the 7nm FinFET technology at the layout level. As expected, at nominal conditions, the best choice is to adopt complex gate topology to optimize area, power consumption, and performance. However, the logic multi-level arrangements became the functions up to 50% less sensitive to the transient faults and at least 30% more robust to the process variability effects. A trade-off needs to be done, considering the area and power constraints.

Fouling in refining applications reduces the energy recovery in the pre heat train, increasing the overall cost of the operation. To mitigate fouling, cleanings of the exchangers are scheduled, and the flow distribution in the network modified. Usually, these two decisions are considered independently, and the dynamic behavior and disturbances affecting the network are ignored. Without considering process variability, fouling mitigation alternatives will become suboptimal or infeasible over time. This work builds on our previous research where an online NMPC-MHE multiloop approach was developed for fouling mitigation and tested under nominal model mismatch. Here, the performance of the framework for simultaneous optimal online flow control and cleaning scheduling is demonstrated for large and realistic disturbances found in refining operations (+/- 50% inlet temperatures and flow changes, and processing different types of crudes). A realistic case is used to demonstrate the advantages of the framework, and results show its effectiveness to react to disturbances over various time scales while minimizing the total operating cost.

The aggressive technology and voltage scaling which modern digital circuits are facing introduce a higher influence in metrics, as performance and power consumption, due to process variability. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7 nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 64.74% and 66.6% improvement in average delay and energy variability robustness, respectively.

International audience; This paper evaluates the potential of using the sleep transistor in FinFET logic cells to mitigate the process variability effects and the soft error susceptibility. The insertion of a sleep transistor improves up to 40.6% the delay variability and up to 12.4% the power variability. Moreover, the design with a sleep transistor became all logic cells investigated free of faults, independently of the supply voltage applied in the design.

Graded-index-core multimode fibers can be appropriately rescaled in diameters and adjusted in alphas to exhibit low differential mode group delays for 15, 21, and 28 spatial modes (five-, six-, and seven-mode groups, respectively). The fibers are actually designed to support six-, seven-, and eight-mode groups but their last mode group is neglected, which reduces the impact of cladding and the sensitivity to process variability, and, thus, allows to dramatically decrease the differential mode group delays. An eight-mode-group rescaled multimode fiber is fabricated. Differential-mode-group delays

This paper analyzes and compensates for process and temperature dependency among a (Complementary Metal Oxide Semiconductor) CMOS image sensor (CIS) array. Both the analysis and compensation are supported with experimental results on the CIS&rsquo, s dark current, dark signal non-uniformity (DSNU), and conversion gain (CG). To model and to compensate for process variations, process sensors based on pixel source follower (SF)&rsquo, s transconductance gm,SF have been proposed to model and to be compared against the measurement results of SF gain ASF. In addition, ASF&rsquo, s thermal dependency has been analyzed in detail. To provide thermal information required for temperature compensation, six scattered bipolar junction transistor (BJT)-based temperature sensors replace six image pixels inside the array. They are measured to have an untrimmed inaccuracy within &plusmn, 0.5 ⁰C. Dark signal and CG&rsquo, s thermal dependencies are compensated using the on-chip temperature sensors by at least 79% and 87%, respectively.

In high-dimensional processes, monitoring process variability is considerably difficult due to the large number of variables and the limited number of samples. Monitoring changes in the covariance matrix of a multivariate process is often used for monitoring process variability under the assumption that only a few elements in the covariance matrix are changed simultaneously from the in-control values. The existing LASSO-based covariance monitoring charts in the high-dimensional settings provide good performance in detecting some shift patterns depending on the prespecified tuning parameter. In practice, control charts that perform reasonably well over various shift patterns are desired when shift patterns are unknown. In this article, we propose a control chart based on an adaptive LASSO-thresholding for monitoring changes in the covariance matrix. The performance of the proposed chart, which is called the ALT-norm chart, is evaluated for various shift patterns and compared with the existing penalized likelihood-based methods. The results show the effectiveness of the proposed chart. Finally, we illustrate the advantages of the ALT-norm chart through simulated and real data from both the semiconductor industry and a high-dimensional milling process. - 2019 American Society for Quality. This publication was made possible by the NPRP award [NPRP 05-563-2-142] and [NPRP-7 - 1040 - 2 - 393] from the Qatar National Research Fund (a member of The Qatar Foundation). Scopus

This paper introduces a fully digital pulse-width-modulation (PWM) based calibration technique intended to dynamically compensate the input offset voltage due to process and mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTA). Post-layout simulations on a DB-OTA circuit in 180nm featuring the proposed calibration technique demonstrate that process and mismatch related offset voltage can be effectively compensated by varying the duty cycle of a square wave signal with minimum performance overhead. The proposed OTA consumes just 7.34nW while driving a capacitive load of 80pF with a Total Harmonic Distortion lower than 2.26% at 100mV input signal swing. The total silicon area is $1,700\mu \mathrm{m}^{2}$ .

Binary inspection systems such as those based on ideal templates, neural networks, fuzzy logic, and genetic algorithms are trained by presenting them with exemplars of acceptable work. The system inspects new work by comparing it to the exemplars. The o..

Control charts are important statistical tool used to monitor fluctuations in the process location and dispersion parameters. The issues relating to the appropriate choice of control charts for the effective detection of process variability are addressed, and different control chart structures, such as Shewhart-type, exponentially weighted moving average and cumulative sum are explored under ideal assumption of normality and contaminated normal environments, and hence, those control charts structures are identified which are more capable to detect aberrant changes in the process dispersion. Copyright © 2015 John Wiley & Sons, Ltd.

Made available in DSpace on 2020-12-12T02:27:32Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-12-15 The mechanical planting and harvesting of sugarcane have experienced great technological transformations in Brazil. A pre-sprouted seedling system launched in 2012 is being used widely throughout the country, and new inter-row spacing configurations have been proposed due to the introduction of new multi-row harvesters. The aim of the present study was to evaluate the quality of the mechanical harvesting of sugarcane as performed by a multi-row harvester in three different planting systems, using statistical process control as a tool. The experiment was performed in an agricultural area located in Guariba, in the state of São Paulo, Brazil. The quality of harvesting performed by a multi-row harvester was evaluated in three different planting systems: PSS1, pre-sprouted seedlings with row spacing of 1.25 m; PSS2, pre-sprouted seedlings spaced 1.50 m; and BIL, billets with spaced 1.50 m. The planting material (billet or seedling) and spacing between rows affected the harvesting process. PSS1 presented the lowest process variability for all the evaluated quality indicators except for the damage index. The harvesting process was stable for the cutting height, damage index and soil penetration resistance. BIL presented the highest process variability, and its harvesting process was only stable for the loss index and soil penetration resistance. Farroupilha Federal Institute of Education Science and Technology (IFFar) São Paulo State University (Unesp) School of Agricultural and Veterinarian Sciences, Jaboticabal Federal Institute of Education Science and Technology of Rondônia (IFRO) Mato Grosso State University (UNEMAT) São Paulo State University (Unesp) School of Agricultural and Veterinarian Sciences, Jaboticabal

Combinatory Process Synthesis (CPS) is a special case of software synthesis that can be used to manage variability by synthetizing target-specific processes from a repository of components. While conducted CPS research mainly addresses formal aspects of algorithm engineering, no structured methodology is available that enables the broader industrial application. This study addresses this gap and proposes a procedural model for CPS. The presented research bases on the Design Science Research principles. A case study in the healthcare sector shows the successful applicability of the elaborated procedure.

Typical manufacturing bio-processes operate as multi-step batch operations. Abnormal variations are often experienced in commercial manufacturing which affects the ability to maintain the product supply to the patients. The low titer is usually highly correlated with high lactate in recombinant Chinese hamster ovary (CHO) cells producing immunoglobulin G, but there are limited means to analyze the vast amount of process data archived from manufacturing sites and understand the causes of the multiple sources of process variability. In this study, we investigate diverse data from a cell culture process, from historical runs of a multi-step manufacturing process for a recombinant antibody. Data includes intra-batch measurements, batch conditions and media preparation measurements. Cell culture process stages from inoculum train to production runs. To analyze manufacturing variability in multiple stages with various sources of data sets, we first adopt principal component analysis (PCA) based monitoring to find in which space high lactate and low lactate batches can be separated, and apply clustering to identify fault directions for intra-batch data from production runs. We then predict final lactate using data from inoculum stages with a nonlinear support vector machine (SVM) classifier. These models are used to uncover potential causes of high lactate. This data-driven modelling can provide new insights on process characteristics to understand the sources of process variability and thus mitigation procedures can be implemented.

Stormwater quality modeling remains one of the most challenging issues in urban hydrology today. The processes involved in contaminant generation and transport are very complex, with many associated uncertainties, including uncertainty arising from process variability. In this study, the spatio-temporal variability of build-up/wash-off processes in a heterogeneous urban catchment within the Parisian region is assessed based on three stochastic modeling approaches integrated into the physically based distributed hydrological model, the Urban Runoff Branching Structure (URBS) model. Results demonstrate that accounting for process variability at the scale of a hydrological element is important for analyzing the contamination recorded at the catchment outlet. The intra-event dynamics of total suspended solids (TSS) were most accurately selected for the stochastic exponential SWMM model, as this model succeeded not only in simulating the general trend of TSS concentrations fluctuations but also in replicating multiple peaks observed in pollutographs. The advantage of this approach is that it captures the stochastic nature of the processes with minimal prior knowledge and without extensive calibration, though further enhancement is necessary for it to become a useful tool to support decision making.

In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips.

The cloud is at the centre of attention in various fields, including that of BPM. However, all BPM systems in the cloud seem to be nothing more than an installation in the cloud with a web-interface for a single organisation, while cloud technology offers an excellent platform for cooperation on an intra- and inter-organisational level. In this paper, we show how cloud technology can be used for supporting different variants of the same process (due to “couleur locale”), and how these organisations can aid each other in achieving the completion of a running case. In this paper we describe how we have brought a BPM system (YAWL) into the cloud that supports variants.

Critical to the biopharmaceutical industrial objectives are robust, reproducible processes which result in consistent product quality and yields. These parameters support the product safety and efficacy as well as control over the process and supply chain. To have a consistent cell culture process, process inputs must be reliable. Historically cell culture media have been a source of variability through the inclusion of complex components such as hydrolysates and sera. Industry has shifted to chemically defined basal and feed media and seen reduced variability but chemically defined media have not eliminated process variability. This review will consequently focus on media variability, the subsequent outputs of lactate and ammonia production and product quality, and the possible routes to eliminate process inconsistency.

International audience; The challenges of the Internet of Things (IoT) in an urban environment are driven by smart vehicles which need to be able to efficiently sense and communicate with other nearby vehicles. System-on-chip (SoC) applications in the automotive market have strict circuit performances and reliability requirements for a temperature range of up to 175 °C. This work proposes an analysis of latched-comparators performance considering process variability and temperature variation. State-of-the-art StrongArm and Double-Tail comparators are designed using an XH018 technology. Post-layout simulation results are drawn in order to validate the proposed temperature-aware analysis. Besides the known advantages of the Double-Tail comparator, this work demonstrates that such a comparator has a serious drawback under harsh environments. At 175 °C, the Double-Tail presents a 3.1 ns worst case delay and 1.4 mV offset, while StrongArm shows 2.7 ns and 2.7 mV respectively. Moreover, the Double-Tail's input-referred noise achieves worst-case levels of 0.89 mV, the StrongArm's noise is below 0.4 mV. Therefore, the Double-Tail proved to be less reliable than the StrongArm and also foretells critical failure conditions in harsh environments.

A development of the VeSTIC technology is reported. The manufacturing of the test structures with different types of transistors is described. The electrical 1-V characteristics of the MOS and junction field effect transistors and of the bipolar junction transistors produced in VeSTIC technology were measured. Basic parameters of the test devices were extracted using the simple device compact models. The technology was assessed taking into consideration the process variability issues.

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.

This work provides a detailed set of predictive data about FinFET and Trigate devices behavior considering process variability effects in ON and OFF currents. These evaluations help to understand the impact of variability sources identifying relevant behavior standards with respect to the use of FinFET and Trigate devices. The IOFF suffers the higher impact of geometric variability, mainly on FinFET devices. PFET devices and the LSTP model are also more sensitive than NFET devices and high performance models. Results highlights that Trigate devices are up to 10% less sensitive to gate length variations.

This paper reviews the main differentiating features of planar FDSOI devices vs planar bulk and 3D FinFETs for ultra-low power and IoT (Internet of Things) applications. The interest of using back-bias, the specific FDSOI device/design feature, to maximize the performance/power efficiency, to mitigate the process variability and to suppress the leakage is highlighted in this paper. Low parasitic gate capacitance, low V T mismatch associated with its undoped channel, and low gate resistance linked to the gate-first integration also bring some competitive advantages to FDSOI over FinFETs for Analog and RF devices.

The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced V th drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.

Today’s CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper [1] that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.

This work provides a predictive evaluation of the impact that PVT variability causes on ON and OFF currents of FinFET transistors in technologies sub-22nm. Results show that the OFF current is the most impacted by all sources of variability. In terms of process variability effects, the LG and WFF variations cause the worst values to IOFF, especially for PFET and NFET devices, respectively. Voltage and temperature variations effects damage more the PFET devices.

"27th International Conference on Flexible Automation and Intelligent Manufacturing, FAIM2017, 27-30 June 2017, Modena, Italy", This work presents a case study on the application of quality tools to improve product quality. One component was selected as object study because it presented higher percentage of nonconformities and was increasing over time. Before mass production, at pre-production, Statistical Process Control (SPC) was performed and it was concluded that the process was capable. No further SPC was done during production. After defective units were detected at increasing levels it was apparent that process variability had increased and the process was no longer capable. The study ends with the development of process improvement activities., This work has been supported by COMPETE: POCI-01-0145-FEDER-007043 and FCT - Fundacao para a Ciencia e Tecnologia within the Project Scope: UID/CEC/00319/2013., info:eu-repo/semantics/publishedVersion

Unavoidable statistical variations in fabrication processes can have a strong effect on the functionality of fabricated photonic circuits and on fabrication yield. It is hence essential to consider these uncertainties during design in order to predict and control the statistical behavior of the circuits. In this paper, we exploit elementary effect test and variance-based sensitivity analysis to investigate the behavior of a photonic circuit under fabrication uncertainties, with the aim to identify the most critical parameters affecting circuit performances. As an example, we perform the sensitivity analysis on the 3-dB bandwidth of two different filter designs considering random deviations of the waveguides width and couplers’ gap. The information obtained from the analysis is then used to isolate the most critical parameters of the circuits and to estimate and reduce the cost of postfabrication correction of the process variability.

Published in Camarinha-Matos L., Afsarmanesh H., Fornasiero R. (eds), Collaboration in a Data-Rich World. PRO-VE 2017. IFIP Advances in Information and Communication Technology, vol 506, pp 333-340. Springer, Cham; International audience; Managing process variability enable the process model adaptability according changes in the application environment. In the healthcare area, flexibility is essential to provide a quality treatment because, even patients with the same diagnostic, may follow different paths and suffer different proceedings. Besides, there are many aspects to be considered for the selection of a path, as patient’s symptoms, and clinical guidelines, among others. In this context, this research presents a framework for the management of the process variants through semantic reasoning. The enrichment of the business process with semantics enables the automation of the configuration, thus promoting more flexible and adaptive solutions. The proposed framework helps selecting the appropriate process variant according the patient’s symptoms by reasoning on ontologies based known expertise. In our specific use case, we will use the expertise of the Brazilian guideline for acute ischemic stroke.

Today’s technology nodes contain more and more complex designs bringing increasing challenges to chip manufacturing process steps. It is necessary to have an efficient metrology to assess process variability of these complex patterns and thus extract relevant data to generate process aware design rules and to improve OPC models. Today process variability is mostly addressed through the analysis of in-line monitoring features which are often designed to support robust measurements and as a consequence are not always very representative of critical design rules. CD-SEM is the main CD metrology technique used in chip manufacturing process but it is challenged when it comes to measure metrics like tip to tip, tip to line, areas or necking in high quantity and with robustness. CD-SEM images contain a lot of information that is not always used in metrology. Suppliers have provided tools that allow engineers to extract the SEM contours of their features and to convert them into a GDS. Contours can be seen as the signature of the shape as it contains all the dimensional data. Thus the methodology is to use the CD-SEM to take high quality images then generate SEM contours and create a data base out of them. Contours are used to feed an offline metrology tool that will process them to extract different metrics. It was shown in two previous papers that it is possible to perform complex measurements on hotspots at different process steps (lithography, etch, copper CMP) by using SEM contours with an in-house offline metrology tool. In the current paper, the methodology presented previously will be expanded to improve its robustness and combined with the use of phylogeny to classify the SEM images according to their geometrical proximities.

DMGD-compensated links based on few-mode and multimode fibers are investigated taking into account the impact of process variability. A 50μm-diameter-core multimode-fiber link with values ≤40ps/km for the first 36 usable spatial modes is reported.

We describe the design trade-offs that are at stake when optimizing few-mode fibers (FMFs) that support a high number ( $\ge$ 6) of LP modes. We particularly detail the design of 6-LP-mode fibers that allow to multiply the capacity by a tenfold factor (two modes being spatially non-degenerate and four modes being two times spatially degenerate). For low-differential-mode-group-delay (low-DMGD) FMFs adapted to strongly-coupled mode-division-multiplexed systems, trench-assisted graded-index-core profiles can be optimized to have Max $\vert$ DMGD $\vert$ 1.0 × 10 $^{-3}$ ) to limit mode coupling and $A_{\rm eff}$ >∼100 μm $^2$ to limit intra-mode non-linearity with good mode robustness. For such weakly-coupled FMFs, sensitivity to process variability is small and main characteristics do not significantly change when variations are within the manufacturing tolerances. We also briefly discuss experimental validations.

Generally, response surface designs are used (in quality improvement experiments) in estimating the optimal level combinations of the process parameters. In an industrial process, the most important problem is to predict the operating condition that optimize a response of interest, and simultaneously minimizes the process variability. In modern quality engineering, dual response surface approach was introduced to achieve this goal. Some researchers have proposed to use the generalized linear models to derive the joint mean and variance models, instead of separate mean and variance models as in the dual response surface approach. This article illustrates (based on two real examples) how the generalized linear models approach can be used to achieve the goal. The present analyses and interpretations (related to these two examples) are completely different from all the earlier research findings.

As robustness of any industrial process is an important issue, a standard procedure is used to determine the set point and to minimize the process variability of juice extraction to changes in values of some critical factors. This paper reports work to analyse the efficiency of the pulsed electrical fields carrot juice extraction process even when the control factors undergo slight random variation. The experiments were carried out on a laboratory experimental bench. The work concerned the choice of three factors which are the high voltage level V (kV), the number of pulses and the pulse duration T. Three ‘one-factor-at-a-time experiments’, followed by two factorials designs (one composite, the other fractional), were performed following a well-defined experimental procedure: (1) Fixing the variation domain of the input variables; (2) seeking the optimum set point and (3) analysing the robustness of the process i.e. testing whether the performance of the system remains high even when the factors vary slig...

we propose a process and device design strategy for Lg = 14 nm Si bulk n/p-FinFETs based on the effects of process-induced geometry variability on device performance. A calibrated TCAD simulation was used to design and optimize structures and these were also tested under various process split conditions. By comparing the I–V data from process-changed devices with nominal CMOS, relationships between process- induced geometry variation and device performance were investigated and analyzed. Moreover a DC/RF compact model was executed to observe the geometry variability effects on ring oscillator and RF applications. Finally key circuit design factors to mitigate process variability are suggested.

This paper presents a systematic review on the reported implementation of Statistical Process Control (SPC) in the food industry. The final selection comprehends 41 articles selected and comprehensively analysed to assess SPC development in the food industry through its motivations, benefits, challenges and limitations. Key outputs indicated from the review include: reduced process variability and conformance to the food regulations are the biggest motivations; resistance to accept SPC is the most cited challenge; lack of statistical knowledge is the most common limitation and the biggest benefits for implementing SPC in the food industry are improved food safety and reduced process variation.

We have developed a model which integrates calculation of InAlGaAs multiple quantum well (MQW) transition energies using the envelope function approximation with a statistical analysis of the PL emission wavelength, net strain and MQW period measured for a variety of MQW designs grown by MOCVD. The model relates the measured MQW parameters directly to MOCVD process parameters, allowing an accurate prediction of the process parameters required to grow a specified MQW design. This greatly reduces the need to grow and characterize individual calibration layers. The difference of the measured and predicted MQW parameters is recorded run-to-run over time, which allows process variability to be analyzed across a number of process parameters with intentional variations to grow different MQW designs. Crown Copyright © 2013.

This paper presents a systematic methodology to develop compact MOSFET models for process variability-aware VLSI circuit design. Process variability in scaled CMOS technologies severely impacts the functionality, yield, and reliability of advanced integrated circuit devices, circuits, and systems. Therefore, variability-aware circuit design techniques are required for realistic assessment of the impact of random and systematic process variability in advanced VLSI circuit performance. However, variability-aware circuit design requires compact MOSFET variability models for computer analysis of the impact of process variability in VLSI circuit design. This paper describes a generalized methodology to determine the major set of device parameters sensitive to random and systematic process variability in nanoscale MOSFET devices, map each variability-sensitive device parameter to the corresponding compact model parameter of the target compact model, and generate statistical compact MOSFET models for variability-aware VLSI circuit design.

Vehicle license number plate production in Nigeria faces high variability in terms of process times and inter-arrival times, resulting in poor production schedule reliability. This study aims to clarify the level of such variation and to provide process improvement strategies within plate production. The specific objectives herein include identifying assignable variables, estimating variability indices and minimizing variation by developing solutions to improve system performance. This study explores the variability pooling method in assessing potential cost-effective process improvements and a case study is conducted on four Nigerian vehicle license number plate production plants in order to demonstrate the applicability of the proposed technique. Structured questionnaires were circulated to plant workers and data collected from plant production records from 2012 to 2015 in seven production lines were analyzed. A preliminary study on the production lines revealed the coefficient of variation (CV) for the Awka, Gwagwalada, Lagos and Lagos State Plants, showing measured variability levels of 0.62, 0.67, 0.60 and 0.78, respectively. Comparatively, the results obtained after the variability pooling showed a significant improvement in performance characteristics, such as low CV levels, enabling a 68% increase in net annual income for each plant, as well as enhanced machine utilization.

The transistor array(TA)-style is a layout methodology where an analog layout is configured on the pattern such that unit-transistors of the same size form an array. It contributes to an easy implementation of design automation, and it also serves a design to mitigate the process variability in 90nm beyond. In this work, utilizing a phase locked loop(PLL) circuit as a motif, we verify the relationship between the fine processes and TA-style. We generate the layouts of the PLL based on the TA-style on 0.6um, 180nm, 65nm in three processes, and compare them with respect to the area and the post-layout simulation results of the control voltage of the VCO. Besides, we also generate a custom layout in 0.6um process, and report the comparison result with the TA-style one.

The springback is one of the major defects associated with sheet metal–forming industry. The objective of this study is to minimize the springback and the process variability in V-bending operation. In all, 11 process parameters, the bending angle, sheet thickness, material type, material texture, punch speed, punch holding time, sheet width, punch radius, lubrication, warm working, and repeat bending, have been considered, and their effect on springback has been studied. Based on Taguchi L12211 orthogonal array design, bending tests were conducted on two types of aluminum sheets (Al 1100 and Al 6061), and investigation was focused mainly on the effect of process variables on the springback. As springback is a process defect, the smaller the better signal-to-noise ratio is utilized in the optimization process. Based on the analysis of variance results, the percentage contribution of each factor to springback was calculated and optimum levels of entire factors were ascertained. The punch holding time, material type, and lubrication were found to be the most significant factors affecting springback. The combined effect of these parameters on springback was about 70%. From the confirmation tests, there has been significant improvement in the standard deviation of the mean value of springback.