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The nonlinearity problem of digital pixels restricts the reduction in power consumption at the pixel-level circuit. The main cause of nonlinearity is discussed in this article and low power consumption is attained by reducing the static current in capacitive transimpedance amplifiers (CTIAs) and comparators. Linearity was successfully improved through the use of an off-chip calibration method. A 64 × 64 array prototype digital readout integrated circuit (DROIC) was fabricated using a 0.18 μm 1P6M CMOS process. Experimental results indicated that the post-calibration linearity reached 99.6% with an input current of up to 1.5 μA. The static power consumption per digital pixel was 6 μW. [ABSTRACT FROM AUTHOR]

Summary: A new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper presents a background calibration method assisted with noise-shaping, for a 10-b bridged SAR ADC. It proposes calibrating the mismatches from the MSB capacitors using the LSBs. First-order noise-shaping has been employed to facilitate the calibration as well as the analog-to-digital conversion. Since noise-shaping is able to shape both the comparator input and quantization noise, it is expected to improve the calibration effects as well as the SNR, for the SAR ADC. Measurement results show, upon the proposed calibration, the SAR's INL and SNR are improved by 3 LSB and 9 dB, respectively, compared to when the noise shaping is off. Fabricated using a 55 nm CMOS MOMCAP technology and tested with a −2.5 dB sinewave input, the bridged SAR ADC achieves an SNR of 62.2 dB and an INL better than 1 LSB, when consuming a power of 7 2 μ W , at a supply voltage of 1.2 V and sampling frequency of 50 kHz. The ADC's active area is 3 0 0 × 3 8 0 μ m 2 . [ABSTRACT FROM AUTHOR]

Potential transformers are vital for measuring and protecting the power grid. Their accuracy and reliability directly impact the stability and security of the power system. To address the issues with traditional high-precision potential transformer calibrators, such as cumbersome operation and low efficiency, a high-precision potential transformer calibrator has been developed. The calibrator is based on an embedded system architecture of FPGA and ARM. It uses a high-precision current comparator along with feedback control technology. By monitoring and adjusting the error feedback voltage, it can perform the automated calibration of potential transformers with an accuracy class of 0.0001. The measurement ranges from 0.00001% to 200.0%. This study can be adapted to meet the development needs of modern digital measurement systems. [ABSTRACT FROM AUTHOR]

For the calibration of linear scales, comparators are generally used. Comparators are devices that enable the movement of an evaluation apparatus over a calibrated scale along a linear base with high precision. The construction of a comparator includes a movable carriage that carries the device for the evaluation of the position of the given edge of the line scale relative to the beginning of the scale. In principle, it involves a camera capturing the scale of the measurer, where the position of the camera's projection center is measured using an interferometer. This article addresses the development of a comparator assembled from low-cost components, as well as the description of systematic influences related to the movement of individual parts of the system, such as the inclination and rotation of the camera and directional and height deviations during the carriage's movement. This article also includes an evaluation of the edge of the given scale with subpixel accuracy, addressing distortion elimination and excluding the influences of impurities or imperfections on the scale. The proposed solution was applied to linear-scale measurers, such as leveling rods with coded and conventional scales and measuring tapes. The entire process of measurement and evaluation was automated. [ABSTRACT FROM AUTHOR]

Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system. [ABSTRACT FROM AUTHOR]

High-precision, continuous analog comparators are widely used in signal detection, alarm protection, and other fields. An auto offset calibration method for high-resolution continuous CMOS comparators (CMPs) was proposed. On the basis of the first output of the short-input format CMP, calibration logic will select the proper routine to calculate the best fix trim bit. Two calibration codes are added and averaged to obtain the actual code. This mainly takes into account the fact that there may be a certain delay in comparator flipping, which leads to deviations from the optimal calibration code. This part of the search error can be counteracted by averaging the results of searching from low to high and from high to low. According to different design needs, different trim step sizes can be obtained by adjusting the relative ratio of the smallest calibratio N-channel metal-oxide-semiconductor (NMOS) to the main input pair. Circuit implementation is based on the 110 nm flash process with a 5 V IO device. Analysis and simulation results show that a less than 1 mV offset can be easily achieved, which is suitable for commercial use. The proposed auto offset calibration method does not increase current consumption and can be easily shifted to other advanced technology processes, which make it promising for future use. [ABSTRACT FROM AUTHOR]

Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of CMOS image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 × 256 pixel resolution, the simulation results show that the row time of ADC is 5. 4 μ s , the column-level average power consumption is 129.5 μ W, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure. • The combination of Flash ADC and Single-Slope ADC. • Based on the concepts of time compression and multi-column sharing. • The coarse and fine quantization stages share two comparators. • Using the scheme of differential ramps further reduces the conversion time. • The digital calibration module adds only one redundant bit. [ABSTRACT FROM AUTHOR]

A high-speed dynamic comparator with preamplifier and automatic dc offset calibration in all stages is proposed in this paper. The offset compensation is applied in two stages, following a two-part sequential loop training topology, offering significant reduction of the dc offset in each stage. The final resolution is improved with a final value less than 800 μV operating at 7.5 GHz clock speed. The dynamic comparator stage is a double-tail topology while the calibration topology is based on a current injection technique, instead of the commonly used capacitive calibration which can reduce the operating speed. Designed in a CMOS 65 nm technology node, the circuit operates with 1 V supply voltage. Results of PVT Monte Carlo post-layout simulations verify the operation of the proposed topology. [ABSTRACT FROM AUTHOR]

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and $2\times $ time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper analyzes the principle of the input-referred off calibration using the auxiliary pair for Strong-Arm comparator as well as its impact from the additional common-mode current and parasitic capacitance on the input-referred noise, offset, and decision time in detail. The comparison with the simulation results demonstrates the accurate prediction with the proposed analysis. This paper also discusses the design guideline to optimize the Strong-Arm comparator with the auxiliary pair for offset calibration. [ABSTRACT FROM AUTHOR]

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude. [ABSTRACT FROM AUTHOR]

Analog-to-digital converters (ADCs) with different topologies respond differently to total ionizing dose (TID). A flexible behavioral modeling approach is proposed for system-level simulation of TID effects in successive-approximation-register (SAR) ADCs. The radiation-enabled approach can be adapted for a wide range of ADCs of various resolutions, clock speeds, and manufacturers. The empirical model is calibrated and validated, pre-rad and post-rad, for a particular ADC. Pre-rad calibration is performed by introducing distributions of static parameters corresponding to datasheet specifications. The post-rad calibration is accomplished by introducing error sources associated with the comparator and digital-to-analog converter (DAC), corresponding to experimental data. The calibrated model is used to examine the dynamic performance and to estimate the probability of parametric failure during the mission lifetime. [ABSTRACT FROM AUTHOR]

Copyright of Technisches Messen is the property of De Gruyter and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Angle calibrations are widely used in various fields of science and technology, while in the high-precision angle calibrations, a complete closure method which is complex and time-consuming is common. Therefore, in order to improve the measurement efficiency and maintain the accuracy of the complete closure method, an improved calibration method was proposed and verified by the calibration of a high-precision angle comparator with sub-arc-second level. Firstly, a basic principle and algorithm of angle calibration based on complete closure and symmetry connection theory was studied. Then, depending on the pre-established calibration system, the comparator was respectively calibrated by two calibration methods. Finally, by comparing En values of two calibration results, the effectiveness of the improved method was verified. The calibration results show that the angle comparator has a stable angle position error of 0:1700 and a measurement uncertainty of 0:0500 (k = 2). Through method comparisons, it was shown that the improved calibration method can greatly reduce calibration time and improve the calibration efficiency while ensuring the calibration accuracy, and with the decrease of measurement interval, the improvement of calibration efficiency was more obvious. [ABSTRACT FROM AUTHOR]

In this article, a long-range length comparator, applicable for both static- and dynamic-index calibrations of a linear displacement sensor, is presented. The comparator consists of an air-floating linear motion generator (LMG) and an interferometric optical length calibrator (OLC). A novel design of the LMG made by multisegment splicing is introduced, in which a two-level vibration isolation arrangement, a multiple sliders’ setup, and an exoskeleton framework are adopted. The resulting linear motion can be extremely ideal even with a large stroke. The angular error is within $11.89~\mu $ rad covering the 12-m range. The maximum operating speed and the acceleration of the LMG are 10 m/s and 20 m/s2, respectively. A dual-path optical design of the OLC is displayed, resulting in high environmental tolerance and a small trigger delay of 4.75 ns. The best accuracy of the comparator can be ±($0.041+ 0.106L) \mu \text{m}$ with a resolution of 0.3 nm. The maximum error and operation speed of a 2-m range exposed encoder were successfully calibrated, and the grating pitch deviation was also found, by which the effectiveness of the comparator is proven. The proposed length comparator introduces a possible solution, for how a long-range linear displacement sensor, can be calibrated with high accuracy, efficiency, and applicability. [ABSTRACT FROM AUTHOR]

Summary: This work presents a macro modeling approach for the time‐mode cyclic ADC. The proposed ADC macro model is realized using the time‐to‐voltage converter (TVC) and the voltage‐to‐time converter (VTC) that are the key building blocks of time‐mode ADCs. In addition, the effect of circuit nonidealities and error sources of the time‐mode ADC including parasitic capacitance, current source output resistance, switch on‐resistance, capacitor mismatch, and comparator offset are incorporated in the macro model. The simulation time of the proposed ADC macro model showed 87.1% reduction compared to the all transistor level ADC circuit. As a result, the proposed ADC macro model can facilitate the ADC design and leverage the ADC nonideality analysis. Furthermore, the proposed macro model can be used for ADC calibration scheme development. As a practical design example, the macro model for an 8‐bit time‐mode cyclic ADC has been realized, where the nonideality analysis, design optimization, and calibration scheme development based on the proposed macro model have been demonstrated. [ABSTRACT FROM AUTHOR]

This article reports a power-efficient $8\times $ time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, a pre-defined bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window. Second, to enhance the operation speed, two alternate comparators are adopted in each ADC channel, and an opportunistic adaptive comparator offset calibration is proposed to eliminate the conversion rate degradation caused by the dedicated calibration cycle. The comparator offset is calibrated only when the bit bypass is triggered with the calibration step size adaptively set to acquire both fast convergence and small algorithm noise. In addition, the reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without the introduction of power-hungry-distributed reference buffers. A test chip is fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) process with a core area of 0.11 mm2, including the reference charge reservoirs. Clocked at 2.4 GS/s, the proposed ADC measures a 49.02-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist while consuming only 9.8 mW from a 0.9-V supply, thus resulting in Walden and Schreier figures of merit (FOMs) of 17.7 fJ/conversion-step and 159.9 dB, respectively. [ABSTRACT FROM AUTHOR]

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a 1-GS/s 3.2-mW 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) using background-calibrated coarse and fine comparators. A coarse and fine comparator scheme is proposed for the bit cycling procedure of MSBs and LSBs to reduce the power consumption. By employing a capacitive digital-to-analog converter (DAC) with redundancy, the decision errors of the coarse comparators due to the thermal noise can be tolerated. Therefore, coarse comparators can have relaxed noise constraint and consume low power. In addition, a novel background calibration method is proposed to align the offsets between different comparators using a reference comparator. This background calibration technique requires no additional bit cycle for comparator calibration, thus improving the ADC’s conversion speed. The prototype ADC is implemented in a 28-nm CMOS technology and achieves an effective number of bits of 6.95 b (signal to noise and distortion ratio (SNDR) of 43.6 dB) near Nyquist frequency with the figure of merit (FOM) of 25.87 fJ/conversion-step. To the best of authors’ knowledge, this ADC achieves the highest SNDR among all single-channel SAR ADCs reported that operate above 1 GS/s. [ABSTRACT FROM AUTHOR]

An ultrastable low-noise current amplifier (ULCA) has been transferred between two laboratories, National Physical Laboratory (NPL) and Physikalisch-Technische Bundesanstalt, four times, with three of the transfers yielding a relative change in the transresistance gain of less than $2 \times 10^{-7}$. This is a new benchmark for interlaboratory transfer of small current. We describe in detail the use of a cryogenic current comparator to calibrate the ULCA at NPL, and the use of the ULCA to measure 1- $\text{G}\Omega $ resistors with relative uncertainties at the $10^{-7}$ level. [ABSTRACT FROM AUTHOR]

Summary: This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐Signal‐to‐noise plus Distortion Ratio [SNDR]). A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one‐half least‐significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15‐bit pipeline ADC using a novel calibrated dynamic‐latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications. [ABSTRACT FROM AUTHOR]

A signal-dependent dithering calibration exploiting noise quantiser (NQ) technique to correct capacitor mismatch and inter-stage gain error in pipelined successive approximation register (SAR) ADCs is proposed. With signal-dependent dithering injection, capacitor mismatch and gain error are extracted and subsequently calibrated as one error in the background. Besides, a novel NQ is proposed for a dithering injection only when the residue is near the threshold of the comparator, thereby allowing the injection of dithering without consuming the dynamic range. The simulation results show that the calibration can significantly improve the performance of pipelined SAR ADCs without extra hardware overhead and timing budget. [ABSTRACT FROM AUTHOR]

This paper presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration in a 13.56-MHz CMOS active rectifier. Unlike a conventional switched-offset comparator, the proposed voltage-mode switched-offset comparator reuses its bias current to generate continuously adjustable offset voltage, thereby reducing power loss. Offset calibration for accurate switching is adopted to improve power conversion efficiency (PCE) and voltage conversion ratio (VCR). The proposed switch controller for offset calibration uses dynamic logic circuits and reduces power overhead that NOR-based set-reset latches and edge detectors of conventional switch controllers cause. Under 200- ${\Omega }$ loading and 5-V output, the proposed comparator and controller reduce power consumption by up to 73% and 24% in simulations compared with the conventional comparator and controller, respectively. This paper is implemented with 5-V devices of a 0.35- ${\mu }\mathrm {m}$ CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200- ${\Omega }$ loading. [ABSTRACT FROM AUTHOR]

This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize the time value, a dynamic latch-based high precision time-domain comparator is proposed. Moreover, a redundancy technique is utilized to overcome the effect of nonideal factors, such as incomplete DAC settling, reference scale mismatch, and offset of comparators. A design example of 9-bit 700 MS/s SAR ADC in 65-nm CMOS technology is presented. Simulation results show that with a differential 600- ${\text {mV}}_{p-p}$ input, the spurious free dynamic range at Nyquist input is above 65 dB. The simulated effective number of bit is up to 8.3 bits at 10-MHz input with the presence of noise and mismatches calibration. [ABSTRACT FROM AUTHOR]

This paper presents a 1.25-GS/s 7-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of 41.4/51 dB, while the SNDR/SFDR at Nyquist is 40.1/52 dB and remains still 36.4/50.1 dB at a 5-GHz input frequency (eighth Nyquist zone) without any calibration. The high and nearly constant linearity is enabled by an improved bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34-dB SNDR single-channel SAR ADCs, is accomplished by a triple-tail dynamic comparator and a unit-switch-plus-cap (USPC) capacitive digital-to-analog converter (CDAC). To further enhance the ADC speed, the SAR logic operates in parallel to the comparator, eliminating its timing from the critical loop. The prototype chip in 28-nm bulk CMOS occupies a core area of 0.0071 mm2 and consumes 3.56 mW from a 1-V supply, leading to a Walden figure-of-merit of 34.4 fJ/conversion-step at Nyquist. [ABSTRACT FROM AUTHOR]

IBEX is a novel mixed-mode CMOS application-specific integrated circuit (ASIC), developed at DECTRIS Ltd., dedicated to the readout of hybrid photon counting semiconductor pixel detectors. The chip has been strictly designed in a radiation tolerant enclosed transistor layout and is fabricated in a 110-nm CMOS technology with eight metal layers. It consists of a $256\times 256$ matrix of $75\times 75\,\,\mu \text {m}^{2}$ pixels, which results in an overall chip size of $19.27\times 19.76$ mm2 with periphery, supply, and I/O pads included. A so-called merging mode allows for an increased pixel size of $150\times 150\,\,\mu \text {m}^{2}$. The pixel readout electronics supports electrons and holes collection, and consists of a charge sensitive preamplifier with programmable gain, a shaper, and two comparators that allow for two independent energy thresholds. In the merging mode, the number of energy thresholds is increased up to four. In order to minimize the pixel-to-pixel energy threshold variation, each pixel comparator can be adjusted with a 6-bit trim digital-to-analog converter. The ASIC can operate in a continuous readout mode with two independent 16-bit counters or in a high counting range mode with a single 32-bit counter per energy threshold level. The chip features counter overflow handling and an instant retrigger technology with an adjustable retrigger time for a significantly improved high-rate counting performance. The ASIC offers a selectable external data bus width of 4, 8, or 16-bit. The count rate limit of the readout chip dc-coupled with a silicon sensor lies at around 10 Mcts/s/pix. The measurements show an electronic pixel noise of $89\,\,e^{-}$ rms and the detectable photon energy range between 3 and 160 keV. [ABSTRACT FROM AUTHOR]

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18 µm standard TSMC CMOS process show that the designed comparator dissipates 135 µW of power consumption from a 1.2 V supply voltage and has the 1 mV accuracy while operating at 1 GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09 mV before and after offset cancellation, respectively. [ABSTRACT FROM AUTHOR]

A well-calibrated and highly shielded HPGe detector with considerable relative efficiency is an efficient tool for measurement of naturally occurring radioactive material (NORM) present at ultra low-level in the environmental samples. Efficiency calibration is standard protocol required for quantitative estimation of the activity of any radioactive sample. In the present work it has been shown that in the case of ultra-low level NORM measurement, one can comfortably by pass efficiency calibration by using comparator method i.e., comparing the peak area counts of different photopeaks of standard and samples provided they are counted in same geometry and comparable composition. [ABSTRACT FROM AUTHOR]

The vibration analysis of the length comparator which is operating in dynamic mode and measures lengths with micrometers precision is of a high importance. In this paper, the theory of covariance functions is applied for the analysis of intensity distributions of length comparator vibrational signals and parameters. The data from measurements of vibrational signals at four fixed points were obtained in a form of data arrays. The estimates of cross-covariance functions between the data arrays and the estimates of auto-covariance functions of single arrays were calculated upon varying the quantization interval in the time domain. The normed auto-covariance and cross-covariance functions at the principal points of the comparator that enable establishing changes of correlation between data vectors upon changing the quantization interval of signals are presented. The changes of correlation between the vectors of vibration signals at the points of the comparator on varying the quantization interval are presented in graphs. [ABSTRACT FROM AUTHOR]

A high-accuracy 500 kg mass comparator with a readability of 0.01 g has been developed at the NMIJ/AIST in order to improve calibration capabilities for large weights from 100 kg to 500 kg. This newly developed mass comparator uses a high-accuracy electronic balance as the sensor and a high-sensitivity two-stage lever system with knife-edges to expand the maximum weighing capacity. This design made it possible to reduce the calibration uncertainties of large weights by 34–45%. This paper reports the basic design of the mass comparator and the improved results for large weight calibrations at the NMIJ. [ABSTRACT FROM AUTHOR]

A 10-bit 1 MS/s pipelined SAR ADC for CZT-based imaging system is presented. The ADC is composed of three pipeline stages which are two 4-bit SAR-based Multiplying Digital Analog Converters (MDACs) and a 4-bit SAR ADC. In order to improve the performances of the proposed ADC, several techniques were proposed. Firstly, a novel 4-bit MDAC circuit which can eliminate the offset voltage of residue amplifier is proposed here. Secondly, digital correction technique is adopted for eliminating the error induced by offset voltage of comparator. As long as the offset voltage is less than 1/16 Vref, the offset voltage can be corrected. Thirdly, digital calibration technique is used to calibrate the gain errors due to capacitor mismatch, finite open-loop gain and finite gain band width (GBW) of residue amplifier and so on. The prototype chip was fabricated in a 0.35 µm CMOS process and occupies a core area of 960×1260 µm 2 . The proposed pipleined SAR ADC achieves 55.6 dB SNDR at 1 MS/s sampling rate and consumes 8.2 mW power. The FOM of the proposed ADC is 17.2pJ/conversion-step. [ABSTRACT FROM AUTHOR]

The Russian national humidity standard of gases has been modernized in order to increase the number of reproducible quantities of humidity (relative humidity, dew/frost-point temperature, mole fraction) and to extend the humidity and operating temperature ranges. The basis of the standard comprises two humidity generators with operating temperature ranges from $$5\,^{\circ }\hbox {C}$$ to $$90\,^{\circ }\hbox {C}$$ and from $$-60\,^{\circ }\hbox {C}$$ to $$15\,^{\circ }\hbox {C}$$ . The common working range (from $$5\,^{\circ }\hbox {C}$$ to $$15\,^{\circ }\hbox {C}$$ ) allows comparison of the generators. The generators use the two-pressure method to generate humid gas defined in terms of the relative humidity (from 5 %rh to 98 %rh at temperatures from $$90\,^{\circ }\hbox {C}$$ to $$-60\,^{\circ }\hbox {C}$$ ) and the one-pressure (or phase equilibrium) method to generate humid gas defined in terms of the vapor mole fraction (from 0.6 ppm to $$700\times 10^{3}$$ ppm) and dew/frost-point temperature (from $$-79\,^{\circ }\hbox {C}$$ to $$90\,^{\circ }\hbox {C}$$ ). The expanded uncertainty in the relative humidity is no more than 0.2 %rh, no more than 1.2 % in the vapor mole fraction, and no more than $$0.12\,^{\circ }\hbox {C}$$ in the dew/frost-point temperature. The ordinary hygrometers are traceable to the national primary standard in accordance with the state hierarchical chain for measuring means of gas humidity. The state hierarchical chain consists of three branches for means of measurements: (a) mole fraction, (b) dew/frost-point temperature, and (c) relative humidity with each branch represented as the scheme: primary standard-secondary standard-working standard-ordinary hygrometer. Calibration and verification of working standards and ordinary hygrometers, and their traceability to the primary standard use methods of (i) direct measurements, (ii) direct comparison, or (iii) comparison with a comparator. [ABSTRACT FROM AUTHOR]

With modern equipment it is possible to implement calibration during dynamic regime, when the location of raster elements of measured object is detected during the motion of movable components of measurement equipment. During this process it is acting external as well as internal sources of vibration. In this work the object of investigation is originally developed angle measurement comparator. The main aim of this research is to determine the dynamic characteristics of multibody mechanical systems of the angle comparator carriage on which optical system is attached to it and to compare the experiment with the results obtained by theoretical calculations. [ABSTRACT FROM AUTHOR]

This paper presents a $4 \times $ time-interleaved 6-bit 5 GS/s 3 b/cycle SAR analog-to-digital converter (ADC). Hardware overhead induced by a 3 b/cycle architecture is eased by an interpolation technique where around 1/3 of the hardware is saved. In addition, complicated switching controls are simplified with a proposed fractional DAC array switching scheme, thus reducing the design complexity and the hardware burden. A boundary detection code overriding (BDCO) is introduced to reduce error probability at the large error magnitude, by utilizing the extended time when the comparator is at reset and the DAC at settling. The floorplan of the front-end is optimized for important interleaving clock distributions, and a master-clock-control bootstrapped-switch technique is adopted to suppress the timing-skew effect among the channels. The unit capacitor has been designed to suit for the DAC structure which allows top-plate sharing in both directions, plus, the offset is calibrated on-chip with a clocking variable biasing transistor pair at the latch. Measurement results show that the prototype can achieve 5 GS/s with a total power consumption of 5.5 mW at 1 V supply in 65 nm CMOS technology. Besides, it exhibits a 30.76 dB SNDR and 43.12 dB SFDR at Nyquist, which yields a Walden FoM of 39 fJ/conversion-step. [ABSTRACT FROM PUBLISHER]

We present the latest improvements in the traceable measurement and generation of small electric currents. A central tool in our traceability chain for small direct currents is a new binary cryogenic current comparator (CCC) with a total of 18 276 turns. This 14-bit CCC is well suited for the calibration of high-value resistors and current amplifiers, but also for the direct amplification of small currents. A noise level of 5 fA/ \surd Hz at 0.05 Hz is routinely achieved. The systematic uncertainty due to noise rectification was exemplarily investigated in a ratio-error test configuration, showing that a total uncertainty of about one part in 10^{6} can be achieved at 100 pA. For further improvement, a new instrument was developed, the ultrastable low-noise current amplifier (ULCA). Its transfer coefficient is highly stable versus time, temperature, and current amplitude within a full dynamic range of ±5 nA. The ULCA is calibrated with the 14-bit CCC at high current amplitude, and allows the measurement or generation of 100-pA direct current with an uncertainty of one part in 10^{7}$ . The novel setup was successfully used to investigate the uncertainty of the established capacitor charging method. A quantum metrology triangle experiment based on the presented instruments is proposed. [ABSTRACT FROM PUBLISHER]

A setup based on a direct current (dc) comparator, typically employed in high-current low-resistance calibrations, has been developed for the accurate calibration of dc current ratios for dc currents up to 600 A. For primary currents above 100 A, multiple turns of the primary conductor are made through the device under test. A full uncertainty analysis reveals that the 1 part in 10^6 total expanded uncertainty ( $k = 2$ ) in a calibration of a zero-flux device is limited by the behavior of the device, in particular the instability and sensitivity to the position of the primary current conductor. [ABSTRACT FROM PUBLISHER]

Current-mode sense amplifiers (CSA) are commonly used in eNVM, because of their fast read speed at large bitline (BL) loads and small cell read currents. However, conventional CSAs are unable to achieve fast random read access time (TAC), due to significant summed input offsets (IOS\-SUM) at read-path. This work proposes a calibration-based asymmetric-voltage-biased CSA (AVB-CSA) to suppress IOS\-SUM and enable high-speed sensing without the need for run-time offset-cancellation operations. This work then fabricated two 90 nm AVB-CSA 1 Mb Flash testchips (with and without BL-length test-modes). The AVB-CSA eFlash macros with 512 rows achieved TAC of 3.9 ns at nominal VDD (1.2 V). The BL-length test-mode experiments confirmed a 1.53\times improvement in TAC using AVB-CSA with a BL-length of 2048-rows operating at VDD=0.8 V. [ABSTRACT FROM AUTHOR]

A new current-comparator-based dual-channel calibration system for AC currents and AC voltages in the millivolt range has been developed. The range of generated currents is 1 mA–5 A, and the range of generated voltages is 1–500 mV. The calibration system in-phase and quadrature expanded measurement uncertainties ( $k=2$ ) are within 25\cdot 10^{\mathrm {\mathbf {-6}}} . Although the system has been developed primarily for operation at power frequencies, it is also capable of operating at frequencies up to 1000 Hz with slightly increased uncertainties. The traceability to SI units is established through the calibration of AC voltage by means of AC/DC transfer and DC voltage reference, standard resistor, capacitor, and current comparator ratios. [ABSTRACT FROM PUBLISHER]

We present here the concept of three-arm current comparator impedance bridge, which allows one to perform comparisons among three unlike impedances. Its purpose is the calibration of impedances having arbitrary phase angles against calibrated nearly pure impedances. An analysis of the bridge optimal setting and proper operation is presented. To test the concept, a two-terminal-pair digitally assisted bridge has been realized; preliminary measurements of an air-core inductor and of an $RC$ network versus decadic resistance and capacitance standards, at kilohertz frequency, have been performed. The bridge measurements are compatible with previous knowledge of the standard values with relative deviations of parts in 10^{-5} . [ABSTRACT FROM PUBLISHER]

This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step. [ABSTRACT FROM AUTHOR]