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Current tapped delay line time to digital converters (TDL-TDC) use simple algorithms to correct the bubble error inherent in the TDL. There is interest in knowing if machine learning could improve upon those algorithms Time interval measurements, measures of time between a START event and STOP event, are used in many applications; for example, time-of-flight experiments. Currently, FieldProgrammable Gate Arrays (FPGAs) are preferred to implement Time-to-Digital Converters (TDCs), due to their low non-recurring costs. Nowadays, the preferred TDC architecture in FPGAs is the Tapped Delay-Line; unfortunately, it suffers from Bubble Errors (Bes). The current methods used to solve those BEs worsen the resolution and precision of the TDC; therefore, we propose multiple new methods of solving BEs, based on Machine Learning, to improve the resolution and precision. The ML methods proposed were tested in two Xilinx FPGAs, the Artix-7 and the Kintex UltraScale. The best ML method achieved a precision in the Artix-7 of 12.749 ps r.m.s, with respect to the 12.789 ps r.m.s of the traditional method; while in the Kintex UltraScale was 13.486 ps r.m.s and 13.481 ps r.m.s respectively. Medir intervalos de tiempo es necesario en muchas aplicaciones; por ejemplo, en experimentos que miden tiempos de vuelo. Hoy en día, los dispositivos conocidos como FPGA son los preferidos para implementar medidores de tiempo (TDC), debido a sus bajos costes no recurrentes; la arquitectura preferida para TDCs en FPGAs está basada en una línea de retardo (TDL), sin embargo, sufre de errores. Los métodos actuales para corregir los errores empeoran la precisión del instrumento. Por esto, en este trabajo proponemos nuevos métodos basados en Inteligencia Artificial (IA), para corregir los errores sin perder precisión. Los métodos propuestos han sido provados en dos FPGAs de Xilinx, la Artix-7 y la Kintex UltraScale. La mejor precisión obtenida con los métodos propuestos fue de 12.749 ps r.m.s en la Artix-7, frente a los 12.789 ps r.m.s del método tradicional; en la UltraScale, fue de 13.486 ps r.m.s y 13.481 ps r.m.s respectivamente. Mesurar intervals de temps és necessari en moltes aplicacions; per exemple, en experiments que mesuren temps de vol. Avui en dia, els dispositius coneguts com FPGA son els preferits per implementar mesuradors de temps (TDCs), degut als seus baixos costos no recurrents; la arquitectura preferida per TDCs en FPGAs esta basada en una línia de retard (TDL), però sofreix errors. Els mètodes actuals de correcció d?errors empitjoren la precisió del TDC. Per això, proposem nous mètodes basats en Inteligencia Artificial, per corregir errors sense perdre precisió. Els mètodes proposats han estat provats en dos FPGAs de Xilinx, la Artix-7 i la Kintex UltraScale. La millor precisió obtinguda amb els nous mètodes ha estat de 12.749 ps r.m.s en la Artix-7, enfront dels 12.789 ps r.m.s del mètode tradicional; en la UltraScale, ha estat de 13.486 ps r.m.s i 13.481 ps r.m.s respectivament.

A time-to-digital converter (TDC) often consists of sophisticated, multilevel, subgate delay structures, when time intervals need to be measured precisely. The resolution improvement is rewarding until integral nonlinearity (INL) and random jitter begins to limit the measurement performance. INL can then be minimized with calibration techniques and result postprocessing. The TDC architecture based on a counter and timing signal interpolation (the Nutt method) makes it possible to measure long time intervals precisely. It also offers an effective means of improving precision by averaging. Traditional averaging, however, demands several successive measurements, which increases the measurement time and power consumption. It is shown here that by using several interpolators that are sampled homogeneously over the clock period, the effects of limited resolution, interpolation nonlinearities, and random noise can be markedly reduced. The designed CMOS TDC utilizing internal systematic sampling technique achieves 3.0-ps root mean square (RMS) single-shot precision without any additional calibration or nonlinearity correction.

Successive approximation (SAR) type Analog to Digital Conveter (ADC) is a Nyquist Rate ADC which has acquired tremendous pupularity recently due to its digital nature , minimal complexity and tiny foot print .These merits make them the most energy ecient topology for analog to digital conversion available today well suited for battery powered applications like touch screen controllers , wireless communication systems , Motion detectors etc. Enhancements in these domains is greatly linked to breakthroughs improving speed as well as performance of SAR type ADCs . In this Work we tried to understand SAR topology in depth therby opening up a new 'time' dimesion to harness more information during the SAR conversion process. A new architecture is proposed in which this auxilliary dimension is employed to signicantly improve eciency and throughput over existing SAR ADC implementations .

The adoption of the digital/time converter (DTC) circuit has improved the performance of ΔΣ fractional-N phase-locked loops (PLLs). Accurate cancellation of ΔΣ quantization error via the DTC requires an automatic calibration made by an LMS loop. A high-order ΔΣ speeds up calibration convergence and improves PLL spectral purity, though at the price of larger quantization error and wider DTC range. To overcome this problem, we propose an innovative parallel segmentation scheme which reduces the range of quantization error without compromising spectral purity and convergence speed. The effectiveness of the proposed segmentation scheme is demonstrated via behavioral-level simulations of a digital PLL and compared to the conventional cascaded segmentation scheme.

This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.

The Phys. Inst. III A of RWTH Aachen University is involved in the development, production and tests of the Drift Tube (DT) muon chambers for the barrel muon system of the CMS detector at the LHC at CERN (Geneva). The thesis describes some test procedures which were developed and performed for the chamber local Data Acquisition (DAQ) system, as well as for parts of the Detector Control System (DCS). The test results were analyzed and discussed. Two main kinds of DAQ tests were done. On the one hand, to compare two different DAQ systems, the chamber signals were split and read out by both systems. This method allowed to validate them by demonstrating, that there were no relevant differences in the measured drift times, generated by the same muon event in the same chamber cells. On the other hand, after the systems were validated, the quality of the data was checked. For this purpose extensive noise studies were performed. The noise dependence on various parameters (threshold, HV) was investigated quantitatively. Also detailed studies on single cells, qualified as "dead" and "noisy" were done. For the DAQ tests a flexible hardware and software environment was needed. The organization and installation of the supplied electronics, as well as the software development was realized within the scope of this thesis. The DCS tests were focused on the local gas pressure read-out components, attached directly to the chamber: pressure senso r, manifolds and the pressure ADC (PADC). At first it was crucial to proof, that the calibration of the mentioned chamber components for the gas pressure measurement is valid. The sensor calibration data were checked and possible differences in their response to the same pressure were studied. The analysis of the results indicated that the sensor output depends also on the ambient temperature, a new experience which implied an additional pedestal measurement of the chamber gas pressure sensors at CMS. The second test sequence considered the gas pressure read-out quality. This kind of test used data obtained during the CMS Magnet Test and Cosmic Challenge (MTCC). The signal of two sensor types measuring the same gas pressure at the same time were compared. Also the stability of the sensor output, as well as of the sensor supply voltage were analyzed at different magnetic field values. To perform the mentioned DCS tests a complex software system was developed. This system merges the sensor and calibration data to obtain the final pressure values for each possible sensor/PADC/chamber combination. This proceeds fully automatically by connecting to the diverse internal and external databases, by finding proper data, performing calculations and creating the Look Up Tables (LUT).

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh cryogenic environment. The proposed architecture employs time-to-digital converters (TDCs) and phase interpolation techniques to reach a sampling rate, higher than the clock frequency (maximum 400 MHz), up to 1.2 GSa/s. The resulting FPGA ADC can achieve a 6 bit resolution (ENOB) over a 0.9 to 1.6 V input range and an effective resolution bandwidth (ERBW) of 15 MHz. This implies that the ADC has an effective Nyquist rate of 30 MHz, with an oversampling ratio of $40\times $. The system non-linearities are less than 1 LSB. The main advantages of this architecture are its scalability and reconfigurability, enabling applications with changing demands on one single platform.