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This article presents a wireless multi-channel sensor interface circuit for emerging e-skin applications. The proposed interface circuit uses a CDMA-like sensing method to simultaneously record 16-channel resistive sensors and 16-channel capacitive sensors. The code-modulated multi-channel signals are conditioned and wirelessly transmitted through an edge-encoded pulsewidth-modulation ultra-wideband (PWM UWB) transmitter in the time domain. The PWM UWB transmitter eliminates the need for digitization on the sensor node, reducing the number of data to be sent. This improves the sensing and wireless transmission efficiency. With the proposed edge-encoding technique, the PWM UWB transmitter can recover the sensor data with SNR above 70 dB despite 20% data loss under a lossy environment. Fabricated in 130-nm technology, the wireless multi-channel sensor node occupies a die area of 1.35 mm2 and consumes a power of 70 $\mu \text{W}$. It achieves an energy efficiency of 0.87 pJ/Conversion-step per channel. [ABSTRACT FROM AUTHOR]

This article presents a multi-channel capacitance-to-digital converter (CDC) circuits using the continuous-time Walsh coding multiplexing. The proposed circuits modulate the input capacitive sensors with orthogonal codes, enable simultaneous read-in of 16 capacitive sensors, and provide the combined 16 digitized outputs in a single conversion. By correlating 16 successive digitized outputs with the corresponding orthogonal codes in post-processing, the 16 capacitive channels can then be demodulated separately. The proposed continuous-time Walsh coding modulation preserves temporal information with minimum circuitry duplication and bandwidth requirement. This chip is fabricated in 130-nm CMOS technology and occupies an area of 0.14 mm2. With a reference clock of 4 MHz, the proposed multi-channel CDC achieves 11.4 ENOB with an average conversion time of 482 $\mu \text{s}$. It consumes 0.51 $\mu \text{W}$ /channel and achieves an FoM of 87 fJ/conversion step. [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (∼3× faster while simultaneously consuming ∼3× less energy) compared to Si/SiGe FinFET. The ATOs provide <50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm2of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length. [ABSTRACT FROM AUTHOR]

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-of-line (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric \kappa -value is the most sensitive parameter. Regarding the patterning options, the BEOL process using self-aligned quadruple pattering with positive tone process requires more than a $4\times $ process margin and suffers from 50% parametric yield loss. The required guardband for litho-etch litho-etch becomes as critical as for the self-aligned double patterning process when the overlay control is $6\times $ higher than the critical dimension control. For trench patterning using spacer-defined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%. [ABSTRACT FROM PUBLISHER]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

Biosynthetic production of vanillin via microbial biotransformation offers a low-cost alternative for manufacturers to meet the consumer demands for natural vanillin. However, identifying the high vanillin-producing microbial strains among multitudinous samples using the current analytical techniques such as liquid chromatography (LC) and mass spectroscopy (MS) is time consuming, cumbersome and costly. Here, we propose an alternative low-cost and rapid aptamer-based capacitive assay for sensitive and selective vanillin recognition based on the preferential binding affinity and stability of the aptamer-vanillin complex. This redox-free approach measures the changes in non-faradaic capacitance of transducing graphene-oxide (GO) activated gold electrodes immobilized with vanillin-specific aptamer. Aptamer-vanillin interaction on the GO surface alters the aptamer conformation causing surface charge redistribution detected via capacitance-frequency characteristics. The aptasensor showed a wide dynamic detection range of 10 pM-10 nM and a low limit of detection (LOD) of ~9.91 pM, which is the best reported so far. Finally, validation of the capacitive aptasensing against high-performance LC (HPLC) reference containing vanillin dissolved in a complex M9 medium with interfering compounds (ferulic acid and glycerol), to mimic typical microbial biotransformation, demonstrated good sensitivity and selectivity. The successful proof-of-concept can be translated to high-throughput electronic multi-analyte screening kits supplementary to existing analytical tools. Unlabelled Image • Label-free non-faradaic capacitive detection of vanillin by graphene oxide aptasensor. • Redox-free augmentation of bare GO vanillin response (6-fold) achieved using hybridized aptamer receptor. • The graphene oxide aptasensor showed a wide dynamic detection range (10 pM-10 nM). • The sensor showed a very low detection limit (9.91 pM) for vanillin detection. • The excellent sensor selectivity in a real complex biosynthesis HPLC matrix. [ABSTRACT FROM AUTHOR]